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    ID
    Family
    Category
    Related To
  • PAC-Designer: How can I set up the simulation time in PAC Designer ?
    1467
    All Mixed Signal
    PAC-Designer
    Simulation
  • What is a SYN File?
    1460
    All Devices
    Inquiries
    Ref. Design
  • Diamond / Power Calculator: How do users include the heat sink information for power calculation in…
    1461
    All Devices
    Implementation
    Power Calculator
  • My PC died, can I get a replacement license for my new PC?
    861
    All Devices
    Licensing
    ispLEVER
  • PAC-Designer: How do PAC-Designer's project archiving functions work?
    1490
    All Mixed Signal
    PAC-Designer
    LogiBuilder
  • Lattice ispLever: How to specify where ispLEVER places a register through "synthesis LOC\u201D…
    1494
    All FPGA
    Implementation
    MAP
  • Which HDL entry methods are available for Lattice Platform Manager devices?
    1496
    Platform Manager
    Entry
    Mixed Language
  • Power Manager II: Is there an "Boundary Scan Descriptive Language"  (BSDL) file available?  
    1495
    All Mixed Signal
    Device Modeling
    BSDL
  • LatticeMicoSystem: Does the LatticeMico8 Microcontroller Support Interrupts?
    1493
    All Devices
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • Synplify Pro: How do users prevent the Synplify synthesis tool from removing an unused input pin…
    1492
    All FPGA
    Implementation
    Synplicity
  • Should I add a series inductor between my voltage regulator output and VCC core?
    848
    All Devices
    Power
  • What can I do to maximize the emulated LVDS data rate?
    843
    All FPGA
    Architecture
    IO
  • My original design used GAL "A" devices, do I need to change my design to use the "D" devices?
    842
    GAL/ispGAL
    Architecture
    Configuration/Programming
  • My design includes mature devices, how long will they be available?
    845
    All Devices
    Inquiries
    PCN
  • Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?
    833
    LatticeECP2/M
    Implementation
    Design Planner
  • PAC-Designer: What is the best way to get started on using Lattice PAC-Designer Mixed Signal…
    830
    All Power Management
    PAC-Designer
    LogiBuilder
  • PAC-Designer: How do I convert my Logi-Builder design code to ABEL?
    831
    All Power Management
    PAC-Designer
    ABEL
  • Power Manager II: How to implement multiple POWR1220AT8 Power Manager devices on a board?
    832
    Power Manager II
    Customer Board Design
    Schematic
  • Power Manager II: Can I use an ispPAC-POWR1220 for -48V hot-swap control?
    1476
    Power Manager II
    Customer Board Design
    Schematic
  • Why am I getting the error message "Failed to verify ID" during Full Scan using DL3A/B/C cable?
    1479
    All Devices
    Device Programming
    ispVM System
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