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    ID
    Family
    Category
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  • We have the SiI164 from Lattice in use, now with the EMI / EMV measurement we see that we are over…
    5857
    ASSP-Wired (Silicon Image)
    Customer Board Design
    Board Debug
  • [DPHY-TX of CrossLink] What happen if the length of a long packet is not multiple of 8 bytes?
    5855
    CrossLink
    Lattice IP/Reference Design
    MIPI CSI2 TX
  • [All Devices] Why is there no file attachment in license email?
    5858
    MachXO2
  • All Devices: Can Lattice FPGA IO pins be left Floating?
    5846
    MachXO2
    Architecture
    IO
  • Diamond: Is Diamond 2.1 and 3.10 compatible with Windows 10 (64-bit)?
    5848
    MachXO2
    Installation
    Other
  • LatticeECP3: How to drive ECLK  located in left and right side of the device, with single PLL?
    3480
    LatticeECP3
    Architecture
    IO
  • ispMACH 4000: Why did the ispMACH datasheet not provide rise and fall time?
    5835
    ispMACH 4000
  • Diamond ECP5: Is it possible to program the LFE5U-85F-8BG381C into an ECP5 Evaluation Board that has…
    5832
    LatticeECP5
    Device Programming
  • iCEcube2: Can iCE40UP5k support tristates?
    5398
    iCE40 UltraPlus
    Implementation
    Synthesis
  • Where can I find the document for volatility for the USB programming cable?
    5307
    All Devices
    Device Programming
    Cables
  • All Devices: Can we access any NON-JTAG port (Wishbone, I2C, SPI or CPU) while SED is running in…
    5304
    MACHXO3
    Architecture
    Soft Error Detection (SED)
  • ispMACH4000: How to define "block-level initialization term" in Verilog?
    5303
    ispMACH 4000
    Entry
  • What is the difference between QFN32 described in the package diagrams document…
    5302
    MachXO2
    Inquiries
    Appnote/Technote
  • Diamond / Programmer / MachXO2: How do you communicate with MachXO2 via SSPI when it is in user…
    5371
    MachXO2
    Device Programming
  • Does Lattice provide an RTL model of the L-ASC10 device to be used for simulation?
    5383
    MachXO2
    QuestaSim/Modelsim
    Closed-loop Trim/Fault Logger
  • CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver…
    5389
    CrossLink
    MIPI D-PHY RX/TX
  • MachXO3LF: How do you generate internal Vref generator in the device?
    5368
    MACHXO3
    Implementation
  • Diamond Programmer: Does Diamond Programmer software have versions that support 32-bit Windows?
    5330
    MachXO2
    Device Programming
    Diamond Programmer
  • All FPGA: Does Non-JTAG TransFR support I/O release during TranFR?
    5335
    MACHXO3
    Architecture
    Configuration/Programming
  • Can I set ODCLK frequency lower than recommended minimum frequency?
    5342
    Other Mixed Signal
    Inquiries
    Appnote/Technote
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