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  • How to identify true (positive) and complementary (negative) ball functions for Low Voltage…
    3862
    iCE40
    Inquiries
    Appnote/Technote
  • Are Lattice IP (Intellectual Property) reset signals connected to the GSR (Global Set/Reset) modules…
    3843
    All FPGA
    Lattice IP/Reference Design
    All
  • Can I create a VHDL output from a schematic file in Lattice Diamond software?
    3845
    MachXO2
    Entry
    Schematic
  • Do iCE devices support LatticeMico8/LatticeMico32 Soft-Processor?
    3882
    iCE40
    Implementation
    Mico32(MSB)
  • How to do background programming of external SPI flash connected to XP2?
    3887
    LatticeXP2
    Device Programming
    Configuration/Programming
  • Is it possible with the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) to…
    3881
    iCE40
    Architecture
    IO
  • Can I use Reveal Logic Analyzer in a JTAG chain with multiple devices?
    380
    All FPGA
    Debugging
    Reveal
  • For the MachXO2 device, how to make dynamic changes to the PLL output frequency? Can the PLL be…
    3815
    MachXO2
    Architecture
    PLL/DLL/Clock Routing
  • What is the differencebetween solder ball diameter and solder ball land diameter in TN1074, PCB…
    3813
    All FPGA
    Customer Board Design
    Layout
  • Does Lattice have a reference design to support Reduced Gigabit Media Independent Interface…
    3819
    LatticeECP3
    Lattice IP/Reference Design
    RGMII to GMII Bridge
  • How to find the number of gates available for a Lattice device?
    3812
    LatticeXP2
    Inquiries
    Datasheet
  • How to have consistent bus signal names while switching between Synplify Pro and Lattice Synthesis…
    3816
    All FPGA
    Implementation
    LSE (Lattice Synthesis Engine)
  • Which development tool/software should be used to implement a design on ispLSI3320 device?
    3811
    ispLSI2000
  • How to compile/map Lattice libraries into Modelsim for running the simulation?
    3739
    All Devices
    Simulation
    MTI
  • Why does the below errors appear when trying to simulate the design in Active-HDL?
    3777
    MachXO2
    Simulation
    Aldec
  • Why am I not able to make Reveal Analyzer to work? Are there any steps to follow..?
    3775
    MachXO2
    Debugging
    Reveal
  • How are the allowance and the percentage related in the Lattice Diamond tool's SSO (Simultaneous…
    3772
    MachXO2
    Implementation
    SSO Analysis
  • ispVM System Software, cannot reload the Lattice demo code to the 4256ZE Breakout Board, that I…
    3786
    ispMACH 4000
    Device Programming
    ispVM System
  • How to use IEEE_PROPOSED library in my VHDLcode in Synplify Pro that comes with Lattice Diamond…
    3782
    All FPGA
    Entry
    Synopsys
  • What is the limit of writing or reading of Single Port RAM for MachXO2 devices? Why can't I find the…
    3767
    MachXO2
    Architecture
    Memory EBR/Distributed
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