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  • Topic
    ID
    Family
    Category
    Related To
  • What is the origin of my device?
    926
    All Devices
    Reliability and Materials
    Device Materials
  • For LatticeSC/M, when do I select "User Master Sync to Systembus Clock" in the System Bus IPexpress…
    976
    LatticeSC/M
    Architecture
    Configuration/Programming
  • How can I determine if I have an authentic Lattice device?
    924
    All Devices
    Reliability and Materials
    Reliability
  • What is Auto hold-time correction setting in PAR?
    929
    All FPGA
    Implementation
    PAR
  • Where can I find the mechanical drawing for a device?
    923
    All Devices
    Customer Board Design
    Layout
  • How can I determine what clock resources are being used?
    928
    All FPGA
    Architecture
    PLL/DLL/Clock Routing
  • What is the pin composition?
    922
    All Devices
    Reliability and Materials
    Device Materials
  • How can I determine if there is a lead free package option for a FPGA device?
    921
    All Devices
    Reliability and Materials
    Device Materials
  • How can I create a schematic symbol for a bus in an ABEL module?
    902
    All CPLD
    Entry
    ABEL
  • How many generic routing signals can be used as primary clocks in a LatticeECP2/M device?
    908
    LatticeECP2/M
    Implementation
    PAR
  • What's the best way to place and route a very congested design?
    900
    All FPGA
    Implementation
    PAR
  • How is the configuration file (.txt) generated by IPexpress being used?
    906
    All FPGA
    Implementation
    IPexpress
  • How do I modify the memory CAS latency value when using  LatticeMico32 with a DDR SDRAM memory…
    957
    All FPGA
    Lattice IP/Reference Design
    LatticeMico32
  • What is the difference between a .bit file and a .jed file?
    952
    All Devices
    Device Programming
    Configuration/Programming
  • Can a non encrypted Bit file be programmed into the LatticeECP2/M S series devices with a encryption…
    951
    LatticeECP2/M
    Device Programming
    Configuration/Programming
  • What is the detailed power up sequence for a MachXO device?
    950
    MachXO
    Architecture
    Power Sequence
  • Why do I get Synopsys VCS simulator errors related to GSR/PUR ?
    956
    All Devices
    Simulation
    Synopsys (VCS)
  • Why can't I deploy LatticeMico32 code to a non-volatile memory with the JTAG UART active?
    958
    All FPGA
    Implementation
    Mico32(MSB)
  • Why does Map report errors about inputs connecting to both PAD and non PAD loads?
    953
    All Devices
    Implementation
    MAP
  • Why won't Lattice software recognize "ES" type devices in a Project File?
    954
    All Devices
    Implementation
    Project Navigator
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