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    ID
    Family
    Category
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  • LatticeECP3:  Why only 7 out of 8 Secondary clocks can be assigned in a clock region for LatticeECP3…
    2251
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • LatticeECP3:  I have a DCS feeding a PLL and when it switches in simulation my PLL loses lock.
    2253
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • LatticeSC/M: How should I setup my SPI4.2 IP core power-on reset sequence?
    222
    LatticeSC/M
    Lattice IP/Reference Design
    SPI4.2
  • Are there any existing software tutorials and manuals for ispLEVER installation?
    227
    All CPLD
    Inquiries
    Tutorials
  • LatticeECP2/ECP3: What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region text is…
    2220
    LatticeECP2/M
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • PAC Designer: How to change the timer value when using an ABEL design?
    2228
    Power Manager II
    PAC-Designer
    ABEL
  • ECP3: Is there a way to actively select the configuration bitstream the LatticeECP3 loads from the…
    2212
    LatticeECP3
    Device Programming
    Configuration/Programming
  • Where can I find the related documentation ans source code to program my Lattice Device using the…
    2213
    All Devices
    Device Programming
    ispVM System
  • LatticeECP2/ECP3: What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region data is…
    2219
    All Devices
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • Diamond: What is the procedure to prevent unused IO logic from getting optimized out during…
    2214
    All Devices
    Implementation
    Attributes/Directives
  • LatticeECP3/DDR3 SDRAM Controller v1.3.0 and up: For DDR3 controller IP core v1.3, why does the…
    2218
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • Why do I get an error  stating "FTDI port is busy", when ispVM System opens?
    2217
    All Devices
    Device Programming
    ispVM System
  • [LatticeECP2/N] What are the factors affecting the CCLK frequency setting for Lattice ECP2M SPI…
    2200
    LatticeECP2/M
    Architecture
    Configuration/Programming
  • [Platform Manager 2] Does VCCD and VCCA need to be above 3.0V when programming the device since the…
    2209
    Power Manager II
    Architecture
    Configuration/Programming
  • Why does the USB ispDOWNLOAD cable raise the VCCJ voltage when I connect it to my low power board…
    2205
    All Devices
    Device Programming
    Cables
  • When using Global Set/Reset (GSR), what is the reset to out delay value?
    2248
    LatticeSC/M
    Implementation
    Timing Analysis
  • LatticeECP3: I need to use four chip select signals while the Lattice DDR3 controller IP core…
    2244
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • Lattice ECP3: Is it OK to loop XAUI data from the RX XGMII to TX XGMII if the IPG is always between…
    2245
    All FPGA
    Lattice IP/Reference Design
    XAUI 10Gb Ethernet AUI
  • LatticeECP3: How can I get around the error "trace: Mangled ncd file before signal read"?
    2243
    LatticeECP3
    Implementation
    PAR
  • MachXO2:  Why does my XO2 EFB SPI / I2C Interface Lock Up when operating as a slave?
    2240
    MachXO2
    Architecture
    Embedded Functional Block (EFB)
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