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    ID
    Family
    Category
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  • The LatticeXP2 device does not have a sub-LVDS input type, can I still receive sub-LVDS output…
    881
    LatticeXP2
  • The XP2 device does not have a mini-LVDS output type, can I still drive mini-LVDS inputs with the…
    879
    LatticeXP2
  • Should I add external series resistors to my parallel bus to improve the signal integrity?
    852
    All Devices
  • Why can't I drive a long PCB trace with a low current setting and get good signal quality?
    850
    All Devices
  • Should I add a series inductor between my voltage regulator output and VCC core?
    848
    All Devices
  • My device has a 3.3v VCCIO, can the device IO drive an LED directly?
    840
    All Devices
  • What is the difference between a .bit file and a .jed file?
    617
    All Devices
    Other
  • Why does the following error occur: "ERROR - Environment variable 'TEMP' is set to a non-writable…
    492
    All FPGA
    Other
  • I configure a Lattice ECP2/M device with an Atmel SPI Flash. Supposedly the CCLK should run 120…
    424
    LatticeECP2/M
    Architecture
  • Is there a recommended way of choosing AES (Advanced Encryption Standard) encryption key?
    1644
    LatticeECP3
    Device Programming
  • How can the default/recent projects (.xcf) be cleared in the File menu of ispVM?
    1318
    All Devices
  • Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
    1315
    All Devices
  • How many DDR memory interfaces can be implemented on a single part?
    1076
    All FPGA
  • In PCI Express x4 core v3.3, when do we need to set VCO auto-band options in the auto-configure text…
    1062
    LatticeECP2/M
  • I have a 3-stage shift register, the software always implement it in a dual-port RAM, how can I…
    1060
    All FPGA
  • Why do I receive notices that my evaluation version of Aldec is about to expire. I upgraded to…
    1053
    All Devices
  • What is the difference between "External feedback" and "internal feedback" when…
    3740
    ispMACH 4000
    Inquiries
    Datasheet
  • How to get the working license file for the DS-PCIE-ST-U1 IP suite?  
    3688
    Other FPGA
    Licensing
    Lattice Diamond
  • Does Lattice provide a Fast Fourier Transform (FFT) Compiler IP Core with VHDL as the target…
    3666
    LatticeXP2
    Lattice IP/Reference Design
    FFT Compiler
  • How to define even or odd parity while using Universal Asynchronous Receiver Transmitter (UART)…
    3665
    LatticeXP2
    Lattice IP/Reference Design
    UART
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