Lattice Solutions

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

Lattice Sentry QSPI Monitor IP Core for MachXO3D

Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.

MachXO3D 

APB, SPI, Security, Lattice Sentry PFR IP Package, Lattice Sentry, Lattice Propel, Defense 

IP Core

PCI Express x1 & x4 IP Core for Nexus-based FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive 

IP Core

Convolutional Neural Network (CNN) Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.

ECP5 / ECP5-5G 

Machine Learning/AI, Lattice sensAI, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 

IP Core

I3C Controller IP Core

I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, iCE40 UltraPlus 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive 

IP Core

I3C Target IP Core

I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.

CertusPro-NX, CrossLink-NX, Certus-NX, MachXO5-NX, iCE40 UltraPlus 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive 

IP Core

Tri-Speed Ethernet MAC IP Core

The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 

Connectivity IP Suite, Data Communication, Ethernet, Value IP Suite, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB 

IP Core

UART IP Core

Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.

MachXO3D, Certus-NX, CrossLink-NX, Mach-NX 

APB, RS-232, AMBA, Lattice Propel, UART, TOR Switch, Defense, Automotive 

IP Core

SPI Master IP Core

Lattice SPI Master IP Core is used to communicate with external SPI slave devices such as display drivers, SPI EPROMS, and analog-to-digital converters.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 

SPI, AHB-Lite, APB, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 

IP Core

PCI Express Endpoint Core

Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer

ECP5 / ECP5-5G, LatticeECP3 

Bus Controllers, Connectivity IP Suite, PCIe, PCIe IP Suite, Defense, Automotive 

IP Core

LatticeMico32 Open, Free 32-Bit Soft Processor

A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.

LatticeECP3, LatticeXP2, LatticeECP2/M 

GPIO Control, Mico, Soft Processor, UART, Wishbone, TOR Switch, Defense 

IP Core

10Gb+ Ethernet MAC IP Core

Transmits and receives data between a host processor and an Ethernet network, compliant to IEEE 802.3-2005 standard

ECP5 / ECP5-5G, LatticeECP3, LatticeSC/M, LatticeECP2/M, CertusPro-NX 

Connectivity IP Suite, Ethernet, Defense 

IP Core

Scatter-Gather DMA Controller

Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, CertusPro-NX, CrossLink-NX 

Bus Controllers, Connectivity IP Suite, DMA, PCIe IP Suite, Defense 

IP Core

XAUI 10Gb Ethernet Attachment Unit Interface IP Core

10Gb Ethernet Attachment Unit Interface or XAUI includes support for the XAUI which is used to interface with physical layer devices in 10GbE networks.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, CertusPro-NX 

Connectivity IP Suite, Data Communication, Ethernet, X/S/RGMII, XAUI, Defense 

IP Core

2D Scaler IP Core

Highly-configurable design to convert input video frames of one size to output video frames of a different size

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX 

DSP IP Suite, Image Processing, Video Bridge, Video IP Suite, DSP, Lattice mVision, Defense, UAVs, Automotive 

IP Core

Lattice Mico8 Open, Free Soft Microcontroller

8-bit microcontroller primarilyi targeted to the MachXO2 and MachXO3 families, but portable to other FPGAs. Full 18-bit wide instruction set and 32 registers

LatticeECP3, MachXO2, MachXO3 

I2C, Mico, Soft Processor, SPI, UART, Wishbone, TOR Switch, Defense 

IP Core

Crest Factor Reduction IP

Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.

ECP5 / ECP5-5G, LatticeECP3 

CFR, Data Communication, Defense, SDR 

IP Core

SPI4.2

Enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores

LatticeECP3, LatticeSC/M 

SPI, SPI-4, Defense