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  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • Convolutional Neural Network (CNN) Accelerator IP

    IP Core

    Convolutional Neural Network (CNN) Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Accelerator IP
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • UART IP Core

    IP Core

    UART IP Core

    Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.
    UART IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • PCI Express Endpoint Core

    IP Core

    PCI Express Endpoint Core

    Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
    PCI Express Endpoint Core
  • LatticeMico32 Open, Free 32-Bit Soft Processor

    IP Core

    LatticeMico32 Open, Free 32-Bit Soft Processor

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32 Open, Free 32-Bit Soft Processor
  • 10Gb+ Ethernet MAC

    IP Core

    10Gb+ Ethernet MAC

    Transmits and receives data between a host processor and an Ethernet network, compliant to IEEE 802.3-2005 standard
    10Gb+ Ethernet MAC
  • Scatter-Gather DMA Controller

    IP Core

    Scatter-Gather DMA Controller

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller
  • XAUI 10Gb Ethernet Attachment Unit Interface

    IP Core

    XAUI 10Gb Ethernet Attachment Unit Interface

    A complete configurable XAUI-to-XGMII solution. Implements 10Gb Ethernet (XGXS - IEEE 802.3ae-2002) and SERES-based PCS.
    XAUI 10Gb Ethernet Attachment Unit Interface
  • 2D Scaler IP Core

    IP Core

    2D Scaler IP Core

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler IP Core
  • Crest Factor Reduction IP

    IP Core

    Crest Factor Reduction IP

    Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.
    Crest Factor Reduction IP
  • Lattice Mico8 Open, Free Soft Microcontroller

    IP Core

    Lattice Mico8 Open, Free Soft Microcontroller

    8-bit microcontroller primarilyi targeted to the MachXO2 and MachXO3 families, but portable to other FPGAs. Full 18-bit wide instruction set and 32 registers
    Lattice Mico8 Open, Free Soft Microcontroller
  • SPI4.2

    IP Core

    SPI4.2

    Enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores
    SPI4.2
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    Distributed Arithmetic FIR Filter Generator
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