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  • Advanced CNN Accelerator IP

    IP Core

    Advanced CNN Accelerator IP

    Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
    Advanced CNN Accelerator IP
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Convolutional Neural Network (CNN) Accelerator IP

    IP Core

    Convolutional Neural Network (CNN) Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Accelerator IP
  • Convolutional Neural Network (CNN) Compact Accelerator

    IP Core

    Convolutional Neural Network (CNN) Compact Accelerator

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Compact Accelerator
  • Byte to Pixel Converter IP Core

    IP Core

    Byte to Pixel Converter IP Core

    Lattice Semiconductor Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format
    Byte to Pixel Converter IP Core
  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

    CSI-2/DSI D-PHY Transmitter IP Core

    The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
    CSI-2/DSI D-PHY Transmitter IP Core
  • I3C Controller IP Core

    IP Core

    I3C Controller IP Core

    I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
    I3C Controller IP Core
  • I3C Target IP Core

    IP Core

    I3C Target IP Core

    I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
    I3C Target IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Lattice SPI Master IP Core is used to communicate with external SPI slave devices such as display drivers, SPI EPROMS, and analog-to-digital converters.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

    SPI Slave IP Core

    The SPI is a high-speed synchronous interface allowing a serial bit stream of configured length to be shifted into and out of the device.
    SPI Slave IP Core
  • I2C Master IP Core

    IP Core

  • I2C Slave IP Core

    IP Core

  • CNN Co-Processor Accelerator IP

    IP Core

    CNN Co-Processor Accelerator IP

    A CNN co-processor accelerator engine for use with low power Lattice FPGAs. The engine can be used with a RISC-V processor to create an SOC and implement TF Lite-based acceleration applications that leverage the parallel compute and distributed resource capabilities of Lattice FPGAs.
    CNN Co-Processor Accelerator IP
  • LPDDR3 SDRAM Controller

    IP Core

    LPDDR3 SDRAM Controller

    A general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices and modules compliant with the JESD-209.3 specification
    LPDDR3 SDRAM Controller
  • Video Frame Buffer IP Core

    IP Core

    Video Frame Buffer IP Core

    The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, etc
    Video Frame Buffer IP Core
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