Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support











Tags

































Providers
Clear All
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Convolutional Neural Network (CNN) Accelerator IP

    IP Core

    Convolutional Neural Network (CNN) Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Accelerator IP
  • Convolutional Neural Network (CNN) Compact Accelerator

    IP Core

    Convolutional Neural Network (CNN) Compact Accelerator

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Compact Accelerator
  • Byte to Pixel Converter IP Core

    IP Core

    Byte to Pixel Converter IP Core

    Lattice Semiconductor Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format
    Byte to Pixel Converter IP Core
  • CSI-2/DSI D-PHY Receiver

    IP Core

  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • CNN Co-Processor Accelerator IP

    IP Core

    CNN Co-Processor Accelerator IP

    A CNN co-processor accelerator engine for use with low power Lattice FPGAs. The engine can be used with a RISC-V processor to create an SOC and implement TF Lite-based acceleration applications that leverage the parallel compute and distributed resource capabilities of Lattice FPGAs.
    CNN Co-Processor Accelerator IP
  • LPDDR3 SDRAM Controller

    IP Core

    LPDDR3 SDRAM Controller

    A general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices and modules compliant with the JESD-209.3 specification
    LPDDR3 SDRAM Controller
  • Video Frame Buffer IP Core

    IP Core

    Video Frame Buffer IP Core

    Highly-configurable solution buffers video data in external memory, supports image sizes up to 4K x 4K with YCbCr 4:2:2, 4:4:4 and RGB video formats
    Video Frame Buffer IP Core
  • Page 1 of 1
    First Previous
    1
    Next Last