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  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

    CSI-2/DSI D-PHY Transmitter IP Core

    The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
    CSI-2/DSI D-PHY Transmitter IP Core
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    ​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​
    UART 16550 IP Core
  • GRHSSL - High Speed Serial Link Controller IP Core

    IP Core

    GRHSSL - High Speed Serial Link Controller IP Core

    The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
    GRHSSL - High Speed Serial Link Controller IP Core
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • GRSPW_CODEC SpaceWire Codec IP Core

    IP Core

    GRSPW_CODEC SpaceWire Codec IP Core

    The GRSPW_CODEC core implements a SpaceWire encoder decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C). Data is transmitted and received through FIFOs with configurable depth.
    GRSPW_CODEC SpaceWire Codec IP Core
  • GRSPW2 SpaceWire Link IP Core

    IP Core

    GRSPW2 SpaceWire Link IP Core

    The GRSPW2 implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C) and RMAP protocol (ECSS-E-ST-50-52C).
    GRSPW2 SpaceWire Link IP Core
  • NOEL-V RISC-V Processor IP Core

    IP Core

    NOEL-V RISC-V Processor IP Core

    The NOEL-V is a VHDL model of a processor that implements the RISC-V architecture, which can be configured to conform to the RV32 or RV64 architectures.
    NOEL-V RISC-V Processor IP Core
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