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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 
    Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 
    DSP, Guidance Systems, Automotive, DSP Bundle, SDR 
    FIR Filter Generator IP Core
  • ​​JESD204B IP Core​

    IP Core

    ​​JESD204B IP Core​

    ​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​
    ECP5 / ECP5-5G, LatticeECP3, CertusPro-NX 
    ADC/DAC, DSP, SDR 
    ​​JESD204B IP Core​
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    Avant-G, Avant-X, CertusPro-NX 
    Ethernet, PCS, XGMII, AXI4, Ethernet Bundle, SDR 
    10Gb Ethernet MAC+PHY IP Core
  • 25Gb Ethernet MAC+PHY IP Core

    IP Core

    25Gb Ethernet MAC+PHY IP Core

    The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    Avant-X 
    Ethernet, Lattice Avant, IEEE 802.3, Ethernet Bundle, SDR 
    25Gb Ethernet MAC+PHY IP Core
  • PCI Express x1, x4 Root Complex Lite IP Core

    IP Core

    PCI Express x1, x4 Root Complex Lite IP Core

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 
    PCIe, Guidance Systems, Automotive, PCIe Bundle, SDR 
    PCI Express x1, x4 Root Complex Lite IP Core
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
    APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 
    PCI Express for Nexus FPGAs
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 
    AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 
    AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 
    RISC-V SM CPU IP Core
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    Avant-G, Avant-X 
    AXI, AHB, AHB-Lite, RTL, PCIe, Bus Controllers, Defense, Automotive, Lattice Avant, PCI, PCIe Bundle, SDR 
    PCI Express for Avant FPGAs
  • Crest Factor Reduction IP

    IP Core

    Crest Factor Reduction IP

    Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.
    ECP5 / ECP5-5G, LatticeECP3 
    CFR, Data Communication, Defense, SDR 
    Crest Factor Reduction IP
  • JESD204A IP Core

    IP Core

    JESD204A IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    LatticeECP3 
    ADC/DAC, DSP, SDR 
    JESD204A IP Core
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