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  • Lattice Sentry Root of Trust Reference Design for MachXO3D

    Reference Design

    Lattice Sentry Root of Trust Reference Design for MachXO3D

    This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
    Lattice Sentry Root of Trust Reference Design for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for Mach-NX

    Reference Design

    Lattice Sentry Root of Trust Reference Design for Mach-NX

    This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.
    Lattice Sentry Root of Trust Reference Design for Mach-NX
  • Lattice Sentry 2.2 BKC Reference Design

    Reference Design

    Lattice Sentry 2.2 BKC Reference Design

    The Lattice Sentry Best-Known Configuration (BKC) Reference Design provides a basic framework to implement a PFR design.
    Lattice Sentry 2.2 BKC Reference Design
  • Single Wire Signal Aggregation Reference Design

    Reference Design

    Single Wire Signal Aggregation Reference Design

    Single Wire Signal Aggregation Reference Design is configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted.
    Single Wire Signal Aggregation Reference Design
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • MachXO3D ESB Implementing AES128/AES256 Encryption and Decryption

    Reference Design

    MachXO3D ESB Implementing AES128/AES256 Encryption and Decryption

    Shows how to use the MachXO3D Embedded Security Block (ESB) to implement AES128 or AES256 encryption or decryption.
    MachXO3D ESB Implementing AES128/AES256 Encryption and Decryption
  • RGMII to GMII Bridge Reference Design

    Reference Design

    RGMII to GMII Bridge Reference Design

    Lattice RGMII to GMII Bridge Reference Design provides a bi-directional bridge function for transferring data between RGMII and GMII.
    RGMII to GMII Bridge Reference Design
  • Image Sensor Bridge

    Reference Design

    Image Sensor Bridge

    Interfaces a CMOS camera to a Digital Video Port (DVP) for a low-power low-footprint solution.
    Image Sensor Bridge
  • Cyclic Redundancy Check Reference Design

    Reference Design

    Cyclic Redundancy Check Reference Design

    Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64
    Cyclic Redundancy Check Reference Design
  • NOR Flash Memory Controller - WISHBONE Compatible

    Reference Design

    NOR Flash Memory Controller - WISHBONE Compatible

    Provides a NOR flash memory controller through WISHBONE bus. It supports several common operational modes of a NOR flash
    NOR Flash Memory Controller - WISHBONE Compatible
  • SMBus Controller

    Reference Design

    SMBus Controller

    Provides a bridge between the SMBus (System Management Bus) master and the WISHBONE bus. SMBus is a 2-wire interface similar to I2C.
    SMBus Controller
  • LatticeMico8 to WISHBONE Interface Adapter

    Reference Design

    LatticeMico8 to WISHBONE Interface Adapter

    Provides logic to adapt the Lattice Mico8 (LM8) external I/O to a WISHBONE master interface
    LatticeMico8 to WISHBONE Interface Adapter
  • PCI Target 32-bit/33MHz

    Reference Design

    PCI Target 32-bit/33MHz

    Fully Compliant with PCI 2.2 specification.
    PCI Target 32-bit/33MHz
  • Power Management Bus

    Reference Design

    Power Management Bus

    Implements the Data Link Layer protocol of the Power Management Bus, conneting to a WISHBONE interface
    Power Management Bus
  • HDMI/DVI Video Interface

    Reference Design

    HDMI/DVI Video Interface

    SERDES-based DVI and HDMI interface supports data rate up to 1.65 Gbps
    HDMI/DVI Video Interface
  • 12V Hot Swap Control

    Reference Design

    12V Hot Swap Control

    Demonstrates how a Power Manager II ispPAC-POWR1220AT8 can be used to implement the functions required for +12V hot-swap applications
    12V Hot Swap Control
  • 5V & 3.3V Hot Swap Controller

    Reference Design

    5V & 3.3V Hot Swap Controller

    Implements a hot swap controller design within a Power Manager II mixed-signal PLD
    5V & 3.3V Hot Swap Controller
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