Lattice Solutions

Reference Design

Lattice Sentry Root of Trust Reference Design for MachXO3D

This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.

MachXO3D 

NIST, RISC-V, Lattice Propel, Lattice Sentry, Security, Defense 

Reference Design

Lattice Sentry Root of Trust Reference Design for Mach-NX

This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.

Mach-NX 

GPIO Control, I2C, RISC-V, SPI, UART, NIST, Lattice Propel, Lattice Sentry, Defense 

Reference Design

Single Wire Signal Aggregation Reference Design

Single Wire Signal Aggregation Reference Design is configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted.

iCE40 UltraPlus 

Bus Controllers, Signal Aggregation, Single Wire, Defense 

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.

iCE40 UltraPlus 

Machine Learning/AI, Object Detection, Lattice sensAI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 

Reference Design

Object Counting AI

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine

ECP5 / ECP5-5G, CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Object Counting, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 

Reference Design

MIPI CSI-2 Virtual Channel Aggregation with CrossLink-NX

Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.

CrossLink, CrossLinkPlus, CrossLink-NX 

CSI-2, MIPI, Modular MIPI/D-PHY, Lattice mVision, Signal Aggregation, Video Tx/Rx, Video Aggregation, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 

Reference Design

N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Modular MIPI/D-PHY Reference Design - Aggregate multiple MIPI CSI-2 inputs up to 5 channels horizontally line by line to a single CSI-2 output

CrossLink, CrossLinkPlus, CrossLink-NX 

CSI-2, MIPI, Modular MIPI/D-PHY, Lattice mVision, Signal Aggregation, Video Tx/Rx, Video Aggregation, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 

Reference Design

MachXO3D ESB Implementing AES128/AES256 Encryption and Decryption

Shows how to use the MachXO3D Embedded Security Block (ESB) to implement AES128 or AES256 encryption or decryption.

MachXO3D 

Encryption, AES, Security, Defense 

Reference Design

RGMII to GMII Bridge Reference Design

Lattice RGMII to GMII Bridge Reference Design provides a bi-directional bridge function for transferring data between RGMII and GMII.

LatticeECP3, ECP5 / ECP5-5G, CertusPro-NX, MachXO5-NX 

Ethernet, X/S/RGMII, Defense 

Reference Design

Image Sensor Bridge

Interfaces a CMOS camera to a Digital Video Port (DVP) for a low-power low-footprint solution.

iCE40 UltraPlus 

DVP, Parallel Video, Video Bridge, Video Tx/Rx, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 

Reference Design

Cyclic Redundancy Check

Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64

MachXO2, MachXO 

CRC, Data Communication, Defense 

Reference Design

NOR Flash Memory Controller - WISHBONE Compatible

Provides a NOR flash memory controller through WISHBONE bus. It supports several common operational modes of a NOR flash

MachXO, MachXO2 

NOR Flash, Wishbone, Defense 

Reference Design

SMBus Controller

Provides a bridge between the SMBus (System Management Bus) master and the WISHBONE bus. SMBus is a 2-wire interface similar to I2C.

MachXO, MachXO2 

I2C, Power Management Bus, SMBus, Temperature Sensor, Wishbone, TOR Switch, Defense 

Reference Design

LatticeMico8 to WISHBONE Interface Adapter

Provides logic to adapt the Lattice Mico8 (LM8) external I/O to a WISHBONE master interface

LatticeXP2, MachXO 

Mico, Soft Processor, Wishbone, TOR Switch, Defense 

Reference Design

PCI Target 32-bit/33MHz

Fully Compliant with PCI 2.2 specification.

ispMACH 4000ZE, MachXO, LatticeXP2, LatticeECP3 

Bus Controllers, PCI, Defense 

Reference Design

Power Management Bus

Implements the Data Link Layer protocol of the Power Management Bus, conneting to a WISHBONE interface

MachXO, MachXO2, Platform Manager 

Bus Controllers, Mixed-Signal, Power Management Bus, Wishbone, Defense 

Reference Design

HDMI/DVI Video Interface

SERDES-based DVI and HDMI interface supports data rate up to 1.65 Gbps

LatticeECP3 

DVI, HDMI, SERDES, Defense 

Reference Design

12V Hot Swap Control

Demonstrates how a Power Manager II ispPAC-POWR1220AT8 can be used to implement the functions required for +12V hot-swap applications

Power Manager II 

Mixed-Signal, Power Management, Defense 

Reference Design

5V & 3.3V Hot Swap Controller

Implements a hot swap controller design within a Power Manager II mixed-signal PLD

Power Manager II 

Mixed-Signal, Power Management, Defense 

Reference Design

Machine Learning / On-device AI

Uses artificial intelligence (AI) to implement a human detection algorithm

iCE40 UltraPlus 

Machine Learning/AI, Object Detection, Defense