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  • Close Loop BLDC Motion Control Reference Design

    Reference Design

    Close Loop BLDC Motion Control Reference Design

    Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system
    Close Loop BLDC Motion Control Reference Design
  • CrossLinkU-NX UVC Streaming Reference Design

    Reference Design

    CrossLinkU-NX UVC Streaming Reference Design

    UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.
    CrossLinkU-NX UVC Streaming Reference Design
  • Lattice QSPI to NXP MPU Interface Reference Design

    Reference Design

    Lattice QSPI to NXP MPU Interface Reference Design

    This Lattice and NXP joint solution is designed to implement FlexSPI communication and expedite deployment using the Lattice ECP5 Evaluation Board.
    Lattice QSPI to NXP MPU Interface Reference Design
  • DisplayPort & Video Scaler Reference Design

    Reference Design

    DisplayPort & Video Scaler Reference Design

    The Lattice Drive DisplayPort & Video Scaler Reference Design implements easy evaluation of various DisplayPort interface.
    DisplayPort & Video Scaler Reference Design
  • MIPI CSI-2 to Ethernet Reference Design

    Reference Design

    MIPI CSI-2 to Ethernet Reference Design

    The MIPI CSI-2 to Ethernet reference design is an advanced system that integrates two camera sensors with each Lattice Avant™ Versa board.
    MIPI CSI-2 to Ethernet Reference Design
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

    Reference Design

    Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

    Reference Design that shows transfer of sensor data to the computer memory and rendering of the data as video on the computer screen using the software driver.
    Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design
  • Multi-Channel Motor Control with Predictive Maintenance Reference Design

    Reference Design

    Multi-Channel Motor Control with Predictive Maintenance Reference Design

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance Reference Design
  • SMBus Controller

    Reference Design

    SMBus Controller

    Provides a bridge between the SMBus (System Management Bus) master and the WISHBONE bus. SMBus is a 2-wire interface similar to I2C.
    SMBus Controller
  • Power Management Bus

    Reference Design

    Power Management Bus

    Implements the Data Link Layer protocol of the Power Management Bus, conneting to a WISHBONE interface
    Power Management Bus
  • 1553 Encoder/Decoder

    Reference Design

    1553 Encoder/Decoder

    Implements Manchester II encoding and decoding required by the 1553 along with synchronization pattern insertion and identification.
     
    1553 Encoder/Decoder
  • ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​

    Reference Design

    ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​

    MLE Robo/TSN virtualizes multi-Gigabit TSN and protocols, linking factory floor to cloud with SmartNICs scalable to 100 Gbps and beyond.​
    ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​
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