Lattice Solutions

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

iCE40 UltraPlus, MachXO2 

UART, Bus Controllers, TOR Switch 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master Controller

Implements an I2C Master Controller in Verilog

iCE40 LP/HX 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Slave Controller Reference Design

Implements an I2C Slave in Verilog

iCE40 LP/HX 

I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

UART Reference Design - WISHBONE Compatible

UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.

MachXO, LatticeXP2, MachXO2, MachXO3 

Bus Controllers, UART, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

SPI Master Controller

Implements a SPI Master Controller in VHDL and uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.

iCE40 LP/HX 

SPI, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

SPI Slave Controller Reference Design

Implements a SPI Slave Controller in VHDL

iCE40 LP/HX 

SPI, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

SPI-to-UART Expander

Acts as a SPI port expander, multiplexing and demultiplexing read/write data through the SPI slave to multiple UARTs

iCE40 LP/HX 

Bus Controllers, SPI, UART, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

I2C Slave/Peripheral

Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment

LatticeECP3, LatticeXP2, MachXO, Platform Manager, ispMACH 4000ZE, ECP5 / ECP5-5G 

I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

SPI Controller - WISHBONE Compatible

Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.

ispMACH 4000ZE, MachXO, LatticeXP2, MachXO2, MachXO3 

SPI, Wishbone, TOR Switch 

Reference Design

SPI Slave Peripheral using Embedded Function Block

Implements intuitive interface between an external SPI master and the XO2 internal registers (user logic) or memory extension in XO2.

MachXO2, MachXO3 

SPI, TOR Switch 

Reference Design

I2C Slave Peripheral using Embedded Function Block

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2

MachXO2, MachXO3 

Bus Controllers, I2C, TOR Switch, Guidance Systems 

Reference Design

LPC (Low Pin Count) Bus Controller

Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)

MachXO2, LatticeXP2, LatticeECP3, ispMACH 4000ZE, MachXO 

Bus Controllers, LPC, Signal Aggregation, TOR Switch 

Reference Design

SPI Flash Controller with Wear Leveling

Implements the wear leveling control of data storage for SPI Flash memory - stores the number of erases, logic-map-physical table, and the valid page pointers.

MachXO2 

SPI, SPI Flash, Wishbone, TOR Switch 

Reference Design

I2C Slave to SPI Master Bridge

Implements an I2C slave to SPI master bridge.

MachXO, Platform Manager 

I2C, SPI, TOR Switch 

Reference Design

SMBus Controller

Provides a bridge between the SMBus (System Management Bus) master and the WISHBONE bus. SMBus is a 2-wire interface similar to I2C.

MachXO, MachXO2 

I2C, Power Management Bus, SMBus, Temperature Sensor, Wishbone, TOR Switch, Defense