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  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Reference Design

    MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Modular MIPI/D-PHY Reference Design - Converts MIPI CSI-2 input to Parallel data type output
    MIPI DSI/CSI-2 to Parallel Bridge Reference Design
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

  • SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
    SubLVDS to MIPI CSI-2 Image Sensor Bridge
  • Multi-Channel Motor Control with Predictive Maintenance

    Reference Design

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
  • MIPI CSI-2 Receive Bridge

    Reference Design

    MIPI CSI-2 Receive Bridge

    Enables a mobile CSI-2 (Camera Serial Interface) image sensor to interface to an embedded Image Signal Processor. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Receive Bridge
  • MIPI CSI-2 Transmit Bridge

    Reference Design

    MIPI CSI-2 Transmit Bridge

    Enables bridging of image inputs like subLVDS or HiSPI to MIPI CSI-2. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Transmit Bridge
  • MIPI DSI Receive Bridge

    Reference Design

    MIPI DSI Receive Bridge

    Allows an AP (Application Processor) or other DSI source to interface to a non-DSI (such as LVDS) display. Up to 4 data lanes at 900 Mbps per lane
    MIPI DSI Receive Bridge
  • Sensor Extender

    Reference Design

    Sensor Extender

    Transmits 720p60 or 1080p30 video over 8 meters of CAT5e/6 cable using two MachXO2 FPGAs, one next to the image sensor and the other just before the ISP.
    Sensor Extender
  • Aptina HiSPi to Parallel Sensor Bridge

    Reference Design

  • Dual HiSPi Sensor Interface Bridge

    Reference Design

    Dual HiSPi Sensor Interface Bridge

    Merges two video streams into a single one. Supports multiple sensor types - HiSpi, sub-LVDS or Parallel
    Dual HiSPi Sensor Interface Bridge
  • Sony subLVDS to Parallel Bridge

    Reference Design

    Sony subLVDS to Parallel Bridge

    Provides a bridge from subLVDS sensors to parallel data for futher processing.
    Sony subLVDS to Parallel Bridge
  • 7:1 LVDS Video Interface

    Reference Design

    7:1 LVDS Video Interface

    Implements standard 7:1 LVDS interfaces using the FPGA I/O structure
    7:1 LVDS Video Interface
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