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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator

    IP Core

    FIR Filter Generator

    Highly configurable, multi-channel FIR filter. Supports up to 256 channels each with 2048 taps. Input and coefficient widths from 4 to 32 bits.
    FIR Filter Generator
  • Coordinate Rotational Digital Computer (CORDIC) IP Core

    IP Core

    Coordinate Rotational Digital Computer (CORDIC) IP Core

    The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.
    Coordinate Rotational Digital Computer (CORDIC) IP Core
  • 2D Scaler IP Core

    IP Core

    2D Scaler IP Core

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler IP Core
  • Numerically Controlled Oscillator

    IP Core

    Numerically Controlled Oscillator

    Also called a Direct Digital Synthesizer (DDS). Supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, plus other usual configurations
    Numerically Controlled Oscillator
  • Interleaver/De-Interleaver

    IP Core

    Interleaver/De-Interleaver

    Supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix
    Interleaver/De-Interleaver
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    Distributed Arithmetic FIR Filter Generator
  • Divider IP Core

    IP Core

    Divider IP Core

    The Lattice Divider IP core uses a non-restoring division algorithm to implement the integer division operation.
    Divider IP Core
  • Turbo Decoder

    IP Core

    Turbo Decoder

    Flexible and compliant with 3GPP and CCSDS
    Turbo Decoder
  • Turbo Encoder

    IP Core

    Turbo Encoder

    Flexible and compliant with 3GPP, 3GPP2 and CCSDS
    Turbo Encoder
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Parameterizable decoding different combinations of convolutionally encoded sequences.
    Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter

    IP Core

    Cascaded Integrator-Comb (CIC) Filter

    Widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters (aka Hogenauer Filter).
    Cascaded Integrator-Comb (CIC) Filter
  • Dynamic Block Reed-Solomon Decoder

    IP Core

    Dynamic Block Reed-Solomon Decoder

    Highly configurable, and compliant with several industry standards including IEEE 802.16-2004
    Dynamic Block Reed-Solomon Decoder
  • Dynamic Block Reed-Solomon Encoder

    IP Core

    Dynamic Block Reed-Solomon Encoder

    Used to perform Forward Error Correction (FEC) in data communications and digital video broadcasting. Highly configurable.
    Dynamic Block Reed-Solomon Encoder
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