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  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • DDR3 PHY

    IP Core

    DDR3 PHY

    Connects a DDR3 memory Controller (MC) to a DDR3 memory device (JESD79-3). Contains all the logic required for functions dependent on FPGA DDR IO primitives
    DDR3 PHY
  • DDR3 SDRAM Controller

    IP Core

    DDR3 SDRAM Controller

    General-purpose complete memory controller interfaces with industry standard DDR3 memory (JESD79-3 Standard), and provides a generic command interface
    DDR3 SDRAM Controller
  • LPDDR3 SDRAM Controller

    IP Core

    LPDDR3 SDRAM Controller

    A general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices and modules compliant with the JESD-209.3 specification
    LPDDR3 SDRAM Controller
  • PCI Express Endpoint Core

    IP Core

    PCI Express Endpoint Core

    Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
    PCI Express Endpoint Core
  • PCI Express x1, x4 Root Complex Lite IP Core

    IP Core

    PCI Express x1, x4 Root Complex Lite IP Core

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1, x4 Root Complex Lite IP Core
  • SGMII and Gb Ethernet PCS IP Core

    IP Core

    SGMII and Gb Ethernet PCS IP Core

    SGMII and Gb Ethernet PCS IP core is used as an interface for a discrete Ethernet PHY chip & can be used in bridging applications and/or PHY implementation.
    SGMII and Gb Ethernet PCS IP Core
  • 10Gb+ Ethernet MAC

    IP Core

    10Gb+ Ethernet MAC

    Transmits and receives data between a host processor and an Ethernet network, compliant to IEEE 802.3-2005 standard
    10Gb+ Ethernet MAC
  • Scatter-Gather DMA Controller

    IP Core

    Scatter-Gather DMA Controller

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller
  • LPDDR2 SDRAM Controller Lite IP Core

    IP Core

    LPDDR2 SDRAM Controller Lite IP Core

    General-purpose memory controller that interfaces with industry standard LPDDR2 memory devices and modules compliant with the JESD209-2B specification
    LPDDR2 SDRAM Controller Lite IP Core
  • XAUI 10Gb Ethernet Attachment Unit Interface

    IP Core

    XAUI 10Gb Ethernet Attachment Unit Interface

    A complete configurable XAUI-to-XGMII solution. Implements 10Gb Ethernet (XGXS - IEEE 802.3ae-2002) and SERES-based PCS.
    XAUI 10Gb Ethernet Attachment Unit Interface
  • JESD204B IP Core

    IP Core

    JESD204B IP Core

    Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
    JESD204B IP Core
  • Common Public Radio Interface - IP Core

    IP Core

    Common Public Radio Interface - IP Core

    Implements the physical layer of the CPRI specification (basic function) and link delay accuracy (low latency character).
    Common Public Radio Interface - IP Core
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