The Lattice™ MIPI® CSI/DSI IP provides a flexible solution for transmission and reception of high-speed video data over a Mobile Industry Processor Interface (MIPI)-compatible D-PHY interface in FPGA designs. MIPI enables high-speed, low-power video transmission between components like cameras and displays, and is widely used in smartphones, automotive systems, industrial equipment, and IoT devices.
Features
- Supports MIPI D-PHY with 1, 2, or 4 data lanes and 1 clock lane.
- Supports Soft D‑PHY bandwidth up to 1.5 Gbps per lane, for a total bandwidth of 6 Gbps
- Supports continuous and non‑continuous MIPI D‑PHY clock operation
-
MIPI CSI/DSI IP on Transmitter Mode
- Supports MIPI CSI‑2
- Supports 1, 2, and 4 pixels per clock (PPC)
-
MIPI CSI/DSI IP on Receiver Mode
- Supports MIPI CSI‑2 and DSI‑2
- Supports 1, 2, and 4 pixels per clock
| Feature / Aspect | Legacy CSI/DSI D-PHY Receiver and Transmitter IP Core | New MIPI CSI/DSI IP Core |
|---|---|---|
| What it Implements? | PHY to Packetizer/Depacketizer layer: receives/transmits CSI/DSI; optional packet processing, stays in byte domain | PHY to Pixel layer: receives/transmits CSI/DSI, translates to UVSI (AXI4 Stream pixel domain |
| Input/Output Data Interface | Parallel byte data (8/16/32/64 bit) | UVSI video stream (AXI4 Stream compliant RGB/RAW pixel domain) |
| Video Format Handling | Video format handling not part of IP; only passes CSI/DSI payload (protocol decode optional) | Supports RGB888, RGB565, RAW10, RAW12 |
| Directional Control | Separate Rx and Tx IP cores | Single IP, one direction active at a time (RX or TX) |
