Pixel to Byte Converter IP Core

Convert Pixel Format Data to Parallel Byte Format

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The Lattice Semiconductor Pixel-to-Byte Converter IP converts a standard parallel video interface to DSI or CSI-2 data for Lattice Semiconductor CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO5TM-NX, Lattice Avant™, and Certus-N2 FPGA family devices.

The Pixel-to-Byte Converter IP converts a standard parallel video interface to either DSI or CSI-2 byte packets. The input interface for the design consists of a pixel clock and pixel bus. For DSI, the packets also include vertical and horizontal sync flags, and a data enable. For CSI-2, they consist of frame, line, and data valid flags.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Support for RGB888, RGB666, RGB444, RGB555, RGB565, RAW8, RAW10, RAW12, RAW14, RAW16, YUV420/YUV422 8/10-bit video formats
  • Conversion of 1, 2, 4, 6, 8, or 10 pixels per pixel clock into MIPI D-PHY byte packet compatible format
  • Support for byte arrangement for 1, 2, or 4 MIPI D-PHY data lanes
  • Optional AXI4 Streaming interface for pixel and byte data
  • APB Interface for configuration and status

Block Diagram

Byte to Pixel Converter Block DiagramExpand Image

Performace and Size

Resource Utilization
Device LUTs Registers sysMEM EBRs Programmable I/O
Default 455 259 1 4
DSI, RGB666, Number of TX Lanes 2 553 296 1 12
CSI-2, RGB888, Number of TX Lanes 4 503 372 1 28
CSI-2, RAW8, Number of TX Lanes 4 394 319 1 28
DSI, RGB888, Number of TX Lanes 4, Number of Input Pixel Per Clock 4, TX Gear 16 689 562 2 60
CSI-2, RGB888, Number of TX Lanes 2, TX Gear 16 503 372 1 28
CSI-2, RAW10, Number of TX Lanes 2, Number of Input Pixel Per Clock 2 471 281 1 12
CSI-2, RAW14, Numbber of TX Lanes 4, Number of Input Pixel Per Clock 2, TX Gear 16 913 696 2 60

Note: The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distributed among logic, distributed RAM, and ripple logic.

Ordering Information

The Pixel to Byte core is available for FREE for use in Diamond design software.

For Radiant design software, the Pixel to Byte core must be purchased:

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 - -
Avant-G PIXEL-BYTE-AVG-UT PIXEL-BYTE-AVG-US
Avant-X PIXEL-BYTE-AVX-UT PIXEL-BYTE-AVX-US
Avant-E PIXEL-BYTE-AVE-UT PIXEL-BYTE-AVE-US
MachXO5-NX PIXEL-BYTE-XO5-UT PIXEL-BYTE-XO5-US
CertusPro-NX PIXEL-BYTE-CPNX-UT PIXEL-BYTE-CPNX-US
Certus-NX PIXEL-BYTE-CTNX-UT PIXEL-BYTE-CTNX-US
CrossLink-NX PIXEL-BYTE-CNX-UT PIXEL-BYTE-CNX-US
Bundled MIPI-BNDL-US MIPI-BNDL-UT

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Pixel-to-Byte IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Pixel-to-Byte Converter IP Core - Lattice Diamond Software
FPGA-IPUG-02026 1.3 3/20/2020 PDF 2.1 MB
Pixel-to-Byte Converter IP User Guide
FPGA-IPUG-02094 1.9 12/20/2024 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Pixel-to-Byte Converter IP Release Notes
FPGA-RN-02020 1.0 12/20/2024 PDF 213 KB

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