Convolutional Neural Network (CNN) Accelerator IP

Rapidly Implement Machine Learning Inferencing

Take advantage of the power of FPGA’s parallel processing to implement CNNs. This IP enables you to implement your own custom network or use many of the commonly used networks published by others.

Our IP provides the flexibility to adjust the number of acceleration engines. By adjusting the numbers of engines and allocated memory, users can trade speed of operation with FPGA’s capacity to obtain the best match for their application.

The CNN Accelerator IP is paired with the Lattice Neural Network Complier Tool. The compiler takes the networks developed common machine learning frameworks, analyzes for resource usage, simulates for performance and functionality, and the compile for the CNN Accelerator IP.

  • Support convolution layer, max pooling layer, batch normalization layer and full connect layer
  • Configurable bit width of weight (16 bit, 1 bit)
  • Configurable bit width of activation (16 bit, 8 bit, 1 bit)
  • Dynamically support 16 bit and 8 bit width of activation
  • Configurable number of memory blocks for tradeoff between resource and performance
  • Configurable number of convolution engines for tradeoff between resource and performance
  • Automatic quantization and fraction settings support
Lattice sensAI

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Block Diagram

Performance and Size

ECP5 Performance and Resource Utilization 1
No. of Convolution Engines No. of Internal Storage of Blob  Registers LUTs Slices Block RAMs clk Fmax (MHz) 2
1 2 3607 4829 3601 25 150.218
4 8 9064 13661 9890 76 144.509
8 16 16482 25889 18456 144 121.892

1. Generated using Lattice Diamond with Synthesis Tool: Synplify Pro targeting a LFE5UM-85F-8BG756I. Performance may vary when using a different software version or targeting a different device density or speed grade.
2. Fmax is generated when the FPGA design only contains the CNN Accelerator IP Core. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Family Part Number Description
ECP5 CNN-ACCEL-E5-U Single Design License
ECP5 CNN-ACCEL-E5-UT Site License


Quick Reference
CNN Accelerator IP User Guide
FPGA-IPUG-02037 2.1 10/24/2019 PDF 1.3 MB
CNN Accelerator IP User Guide
FPGA-IPUG-02037 2.0 9/24/2018 PDF 809.9 KB

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