1:2 MIPI DSI Display Interface Bandwidth Reducer

Bridges an input video stream into two streams or one lower resolution stream

Important: For new designs, Lattice recommends using the following modular IP blocks to implement this function:

The following Reference Design provides an integration example using these modular IP blocks

The Mobile Industry Processor Interface (MIPI®) Alliance has developed the MIPI Display Serial Interface (DSI) and MIPI D-PHY specifications to create a standardized interface for all displays used in the mobile industry. As the industry evolves, bandwidth requirements exceed what display manufacturers are capable of manufacturing, while applications processor vendors continue to provide very fast interfacing devices. CrossLink IP can help solve these challenges.

For a cost effective solution, displays can later be replaced with newer displays, while keeping the current generation processor. Also, multiple displays have gained popularity and extending the output to two display interfaces from a single source becomes a key requirement to support these applications. For high-bandwidth applications processors interfacing with low resolution displays, the bandwidth can be reduced by distributing the input to multiple displays. Lattice’s 1:2 MIPI DSI Display Interface Bandwidth Reducer IP allows users to resolve these interfacing problems.


  • Interfaces a MIPI DSI compliant receiver to two MIPI DSI transmitters
  • Supports up to 4.8 Gb/s MIPI DSI receive interface
  • Supports four data lanes and one clock lane per MIPI DSI interface
  • Supports D-PHY continuous and non-continuous clock modes
  • Compliant with MIPI D-PHY v1.1 and MIPI DSI v1.1 specifications

Block Diagram

1:2 MIPI DSI Display Interface Bandwidth Reducer


Quick Reference
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1:2 MIPI DSI Display Interface Bandwidth Reducer IP
FPGA-IPUG-02028 1.1 5/10/2019 PDF 2.4 MB

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