
// This interface file generated using ORSPI FPSC KIT: 3.0

`timescale 1ns/ 100 ps

module mycore (

ALVCTAP1, ALVCTAP2, ALVCTAP3, ALVCTAP4, ALVCTAP5,
BLVCTAP1, BLVCTAP2, BLVCTAP3, BLVCTAP4, BLVCTAP5,
REF10, REF14, EXT_1K, RESLO, RESHI,
//SPIA RX Interface Inputs. All Banks in 32-bit mode.
SPIA_RX32_CLK_0, SPIA_RX32_CLK_1, SPIA_RX32_CLK_2, SPIA_RX32_CLK_3,
SPIA_RX32_RD_0, SPIA_RX32_RD_1, SPIA_RX32_RD_2, SPIA_RX32_RD_3,
SPIA_RX32_ADDR_0, SPIA_RX32_ADDR_1, SPIA_RX32_ADDR_2, SPIA_RX32_ADDR_3,
SPIA_RX32_PORT_ID, SPIA_RX32_EXT_STAT_EN, SPIA_RX32_STAT, 
SPIA_RX32_PSS_WE, SPIA_RX32_PSS_CLK,

//SPIA RX Interface Outputs. All Banks in 32-bit mode.

SPIA_RX32_DATA_0, SPIA_RX32_DATA_1, SPIA_RX32_DATA_2, SPIA_RX32_DATA_3,
SPIA_RX32_BE_0, SPIA_RX32_BE_1, SPIA_RX32_BE_2, SPIA_RX32_BE_3, 
SPIA_RX32_CTL_0, SPIA_RX32_CTL_1, SPIA_RX32_CTL_2, SPIA_RX32_CTL_3,
SPIA_RX32_ERR_0, SPIA_RX32_ERR_1, SPIA_RX32_ERR_2, SPIA_RX32_ERR_3,
SPIA_RX32_SOP_0, SPIA_RX32_SOP_1, SPIA_RX32_SOP_2, SPIA_RX32_SOP_3,
SPIA_RX32_EOP_0, SPIA_RX32_EOP_1, SPIA_RX32_EOP_2, SPIA_RX32_EOP_3,
SPIA_RX32_FIFO_EMPTY_0, SPIA_RX32_FIFO_EMPTY_1,
SPIA_RX32_FIFO_EMPTY_2, SPIA_RX32_FIFO_EMPTY_3,


//SPIB RX Interface Inputs. All Banks in 32-bit mode.

SPIB_RX32_CLK_0, SPIB_RX32_CLK_1, SPIB_RX32_CLK_2, SPIB_RX32_CLK_3,
SPIB_RX32_RD_0, SPIB_RX32_RD_1, SPIB_RX32_RD_2, SPIB_RX32_RD_3,
SPIB_RX32_ADDR_0, SPIB_RX32_ADDR_1, SPIB_RX32_ADDR_2, SPIB_RX32_ADDR_3,
SPIB_RX32_PORT_ID, SPIB_RX32_EXT_STAT_EN, SPIB_RX32_STAT, SPIB_RX32_PSS_WE,
SPIB_RX32_PSS_CLK,
SPIB_RX32_FIFO_EMPTY_0, SPIB_RX32_FIFO_EMPTY_1,
SPIB_RX32_FIFO_EMPTY_2, SPIB_RX32_FIFO_EMPTY_3,

//SPIB RX Interface Outputs. All Banks in 32-bit mode.

SPIB_RX32_DATA_0, SPIB_RX32_DATA_1, SPIB_RX32_DATA_2, SPIB_RX32_DATA_3,
SPIB_RX32_BE_0, SPIB_RX32_BE_1, SPIB_RX32_BE_2, SPIB_RX32_BE_3,
SPIB_RX32_CTL_0, SPIB_RX32_CTL_1, SPIB_RX32_CTL_2, SPIB_RX32_CTL_3,
SPIB_RX32_ERR_0, SPIB_RX32_ERR_1, SPIB_RX32_ERR_2, SPIB_RX32_ERR_3,
SPIB_RX32_SOP_0, SPIB_RX32_SOP_1, SPIB_RX32_SOP_2, SPIB_RX32_SOP_3,
SPIB_RX32_EOP_0, SPIB_RX32_EOP_1, SPIB_RX32_EOP_2, SPIB_RX32_EOP_3,





//SPIA TX Interface Inputs. All Banks in 32-bit mode.
SPIA_TX32_DATA_0, SPIA_TX32_DATA_1, SPIA_TX32_DATA_2, SPIA_TX32_DATA_3,
SPIA_TX32_PORT_0, SPIA_TX32_PORT_1, SPIA_TX32_PORT_2, SPIA_TX32_PORT_3,
SPIA_TX32_BE_0, SPIA_TX32_BE_1, SPIA_TX32_BE_2, SPIA_TX32_BE_3,
SPIA_TX32_CLK_0, SPIA_TX32_CLK_1, SPIA_TX32_CLK_2, SPIA_TX32_CLK_3,
SPIA_TX32_ERR_0, SPIA_TX32_ERR_1, SPIA_TX32_ERR_2, SPIA_TX32_ERR_3,
SPIA_TX32_SOP_0, SPIA_TX32_SOP_1, SPIA_TX32_SOP_2, SPIA_TX32_SOP_3,
SPIA_TX32_EOP_0, SPIA_TX32_EOP_1, SPIA_TX32_EOP_2, SPIA_TX32_EOP_3,
SPIA_TX32_WE_0, SPIA_TX32_WE_1, SPIA_TX32_WE_2, SPIA_TX32_WE_3,
SPIA_TX32_ADDR_0, SPIA_TX32_ADDR_1, SPIA_TX32_ADDR_2, SPIA_TX32_ADDR_3,
SPIA_TX32_WD_CNT_RST_0, SPIA_TX32_WD_CNT_RST_1, 
SPIA_TX32_WD_CNT_RST_2, SPIA_TX32_WD_CNT_RST_3,
SPIA_TX32_LINK_DIS_0, SPIA_TX32_LINK_DIS_1,
SPIA_TX32_LINK_DIS_2, SPIA_TX32_LINK_DIS_3, SPIA_TREFCLK_X8,

//SPIA TX Interface Outputs. All Banks in 32-bit mode.

SPIA_TX32_PORT_ID, SPIA_TX32_STAT, SPIA_TX32_BURST_VAL,
SPIA_TX32_FIFO_FULL_0, SPIA_TX32_FIFO_FULL_1,
SPIA_TX32_FIFO_FULL_2, SPIA_TX32_FIFO_FULL_3, 


//SPIB TX Interface Inputs. All Banks in 32-bit mode.
SPIB_TX32_DATA_0, SPIB_TX32_DATA_1, SPIB_TX32_DATA_2, SPIB_TX32_DATA_3,
SPIB_TX32_PORT_0, SPIB_TX32_PORT_1, SPIB_TX32_PORT_2, SPIB_TX32_PORT_3,
SPIB_TX32_BE_0, SPIB_TX32_BE_1, SPIB_TX32_BE_2, SPIB_TX32_BE_3,
SPIB_TX32_CLK_0, SPIB_TX32_CLK_1, SPIB_TX32_CLK_2, SPIB_TX32_CLK_3,
SPIB_TX32_ERR_0, SPIB_TX32_ERR_1, SPIB_TX32_ERR_2, SPIB_TX32_ERR_3,
SPIB_TX32_SOP_0, SPIB_TX32_SOP_1, SPIB_TX32_SOP_2, SPIB_TX32_SOP_3,
SPIB_TX32_EOP_0, SPIB_TX32_EOP_1, SPIB_TX32_EOP_2, SPIB_TX32_EOP_3,
SPIB_TX32_WE_0, SPIB_TX32_WE_1, SPIB_TX32_WE_2, SPIB_TX32_WE_3,
SPIB_TX32_ADDR_0, SPIB_TX32_ADDR_1, SPIB_TX32_ADDR_2, SPIB_TX32_ADDR_3,
SPIB_TX32_WD_CNT_RST_0, SPIB_TX32_WD_CNT_RST_1, 
SPIB_TX32_WD_CNT_RST_2, SPIB_TX32_WD_CNT_RST_3,
SPIB_TX32_LINK_DIS_0, SPIB_TX32_LINK_DIS_1,
SPIB_TX32_LINK_DIS_2, SPIB_TX32_LINK_DIS_3, SPIB_TREFCLK_X8,

//SPIB TX Interface Outputs. All Banks in 32-bit mode.

SPIB_TX32_PORT_ID, SPIB_TX32_STAT, SPIB_TX32_BURST_VAL,
SPIB_TX32_FIFO_FULL_0, SPIB_TX32_FIFO_FULL_1,
SPIB_TX32_FIFO_FULL_2, SPIB_TX32_FIFO_FULL_3, 






TESTMDN, PDN, TRISTN, TESTCLK,
ARLSCLK_F, ATREFCLK_F, SPI_SATM_A, SPI_DATM_A, SPI_DLYTAP_A, FPGA_RESET_S4A,
ASTOP_ON_EOP0, ASTOP_ON_EOP1, ASTOP_ON_EOP2, ASTOP_ON_EOP3,
BRLSCLK_F, BTREFCLK_F, SPI_SATM_B, SPI_DATM_B, SPI_DLYTAP_B, FPGA_RESET_S4B,
BSTOP_ON_EOP0, BSTOP_ON_EOP1, BSTOP_ON_EOP2, BSTOP_ON_EOP3,
//SPIA RX APIO
ARDATN, ARDATP, ARCTLN, ARCTLP,
ARDCLKN, ARDCLKP,
RSCLKA, RSTATA, 
ARSTATN, ARSTATP, ARSCLKN, ARSCLKP,

//SPIB RX APIO
BRDATN, BRDATP, BRCTLN, BRCTLP,
BRDCLKN, BRDCLKP, 
RSCLKB, RSTATB, 
BRSTATN, BRSTATP, BRSCLKN, BRSCLKP,

//SPIA TX APIO
ATDATN, ATDATP, ATCTLN, ATCTLP,
ATDCLKN, ATDCLKP, ATREFCLK,
TSCLKA, TSTATA, 
ATSCLKN, ATSCLKP, ATSTATN, ATSTATP,

//SPIB TX APIO
BTDATN, BTDATP, BTCTLN, BTCTLP,
BTDCLKN, BTDCLKP, BTREFCLK,
TSCLKB, TSTATB, 
BTSCLKN, BTSCLKP, BTSTATN, BTSTATP,
SYS_RST_N,
//SYSBUS CONNECTS
DONE, GSRN_TOA,  HADDR, HBURST, HCLK, HREADY_IN, HRESET_N, 
HSEL, HSIZE, HTRANS, HWDATA, HWRITE, PWRUPRES,
HRDATA, HREADY_OUT, HRESP, ASB_EN_SLI, ASB_IRQ_SLI, TRI_IO,
//Serdes APIO

//Inputs
REFCLKN, REFCLKP, 
HDINN_A, HDINN_B, HDINN_C, HDINN_D,
HDINP_A, HDINP_B, HDINP_C, HDINP_D,

//Outputs
HDOUTN_A, HDOUTN_B, HDOUTN_C, HDOUTN_D,
HDOUTP_A, HDOUTP_B, HDOUTP_C, HDOUTP_D,

REXT, REXTN,
//Memory Controller

//APIOs
PMIC, PMICN, PMIQ, MCREFCLK, PMIA, PMID, PMIWN, PMIRN, PMIK, PMIKN, RESETN,

//Interface
F_MC_WD, F_MC_WI, F_MC_RI, F_MC_WCLK, F_MC_RCLK, F_MC_WIFIFO_WE, F_MC_WDFIFO_WE,
F_MC_RIFIFO_WE, F_MC_RDFIFO_RE, MC_RD, MC_RDFIFO_EMPTY, MC_RIFIFO_FULL,
MC_WDFIFO_FULL, MC_WIFIFO_FULL, MC_SYSCLK, F_MC_REFCLK, FPGA_RESET_MC,
); // exemplar attribute mycore dont_touch TRUE 

// Ports

// Misc TAPs

input	ALVCTAP1, ALVCTAP2, ALVCTAP3, ALVCTAP4, ALVCTAP5;
input	BLVCTAP1, BLVCTAP2, BLVCTAP3, BLVCTAP4, BLVCTAP5;
input	REF10, REF14, EXT_1K, RESLO, RESHI;
//SPIA RX Interface Inputs. All Banks in 32-bit mode.
input	SPIA_RX32_CLK_0, SPIA_RX32_CLK_1, SPIA_RX32_CLK_2, SPIA_RX32_CLK_3;
input   SPIA_RX32_RD_0, SPIA_RX32_RD_1, SPIA_RX32_RD_2, SPIA_RX32_RD_3;
input	[2:0]	SPIA_RX32_ADDR_0;
input	[2:0]	SPIA_RX32_ADDR_1;
input   [2:0]   SPIA_RX32_ADDR_2;
input	[2:0]	SPIA_RX32_ADDR_3;
input   [7:0]	SPIA_RX32_PORT_ID;
input		SPIA_RX32_EXT_STAT_EN;
input	[1:0]	SPIA_RX32_STAT;
input		SPIA_RX32_PSS_WE;
input		SPIA_RX32_PSS_CLK;
//SPIA RX Interface Outputs. All Banks in 32-bit mode.
output	[31:0]	SPIA_RX32_DATA_0;
output	[31:0]  SPIA_RX32_DATA_1;
output	[31:0]  SPIA_RX32_DATA_2;
output	[31:0]	SPIA_RX32_DATA_3;
output  [3:0]	SPIA_RX32_BE_0, SPIA_RX32_BE_1, SPIA_RX32_BE_2, SPIA_RX32_BE_3;
output		SPIA_RX32_CTL_0, SPIA_RX32_CTL_1, SPIA_RX32_CTL_2, SPIA_RX32_CTL_3;
output		SPIA_RX32_ERR_0, SPIA_RX32_ERR_1, SPIA_RX32_ERR_2, SPIA_RX32_ERR_3;
output		SPIA_RX32_SOP_0, SPIA_RX32_SOP_1, SPIA_RX32_SOP_2, SPIA_RX32_SOP_3;
output		SPIA_RX32_EOP_0, SPIA_RX32_EOP_1, SPIA_RX32_EOP_2, SPIA_RX32_EOP_3;
output		SPIA_RX32_FIFO_EMPTY_0, SPIA_RX32_FIFO_EMPTY_1;
output		SPIA_RX32_FIFO_EMPTY_2, SPIA_RX32_FIFO_EMPTY_3;

//SPIB RX Interface Inputs. All Banks in 32-bit mode.
input	SPIB_RX32_CLK_0, SPIB_RX32_CLK_1, SPIB_RX32_CLK_2, SPIB_RX32_CLK_3;
input   SPIB_RX32_RD_0, SPIB_RX32_RD_1, SPIB_RX32_RD_2, SPIB_RX32_RD_3;
input	[2:0]	SPIB_RX32_ADDR_0;
input	[2:0]	SPIB_RX32_ADDR_1;
input   [2:0]   SPIB_RX32_ADDR_2;
input	[2:0]	SPIB_RX32_ADDR_3;
input   [7:0]	SPIB_RX32_PORT_ID;
input		SPIB_RX32_EXT_STAT_EN;
input	[1:0]	SPIB_RX32_STAT;
input		SPIB_RX32_PSS_WE;
input		SPIB_RX32_PSS_CLK;
//SPIB RX Interface Outputs. All Banks in 32-bit mode.
output		SPIB_RX32_FIFO_EMPTY_0, SPIB_RX32_FIFO_EMPTY_1;
output		SPIB_RX32_FIFO_EMPTY_2, SPIB_RX32_FIFO_EMPTY_3;
output	[31:0]	SPIB_RX32_DATA_0;
output	[31:0]  SPIB_RX32_DATA_1;
output	[31:0]  SPIB_RX32_DATA_2;
output	[31:0]	SPIB_RX32_DATA_3;
output  [3:0]	SPIB_RX32_BE_0, SPIB_RX32_BE_1, SPIB_RX32_BE_2, SPIB_RX32_BE_3;
output		SPIB_RX32_CTL_0, SPIB_RX32_CTL_1, SPIB_RX32_CTL_2, SPIB_RX32_CTL_3;
output		SPIB_RX32_ERR_0, SPIB_RX32_ERR_1, SPIB_RX32_ERR_2, SPIB_RX32_ERR_3;
output		SPIB_RX32_SOP_0, SPIB_RX32_SOP_1, SPIB_RX32_SOP_2, SPIB_RX32_SOP_3;
output		SPIB_RX32_EOP_0, SPIB_RX32_EOP_1, SPIB_RX32_EOP_2, SPIB_RX32_EOP_3;
//SPIA TX Interface Inputs. All Banks in 32-bit mode.
input	[31:0]	SPIA_TX32_DATA_0;
input	[31:0]	SPIA_TX32_DATA_1;
input	[31:0]	SPIA_TX32_DATA_2;
input	[31:0]	SPIA_TX32_DATA_3;
input	[7:0]	SPIA_TX32_PORT_0;
input	[7:0]	SPIA_TX32_PORT_1;
input	[7:0]	SPIA_TX32_PORT_2;
input	[7:0]	SPIA_TX32_PORT_3;
input	[3:0]	SPIA_TX32_BE_0;
input	[3:0]	SPIA_TX32_BE_1;
input	[3:0]	SPIA_TX32_BE_2;
input	[3:0]	SPIA_TX32_BE_3;
input		SPIA_TX32_CLK_0, SPIA_TX32_CLK_1;
input		SPIA_TX32_CLK_2, SPIA_TX32_CLK_3;
input		SPIA_TX32_ERR_0, SPIA_TX32_ERR_1;
input		SPIA_TX32_ERR_2, SPIA_TX32_ERR_3;
input		SPIA_TX32_SOP_0, SPIA_TX32_SOP_1;
input		SPIA_TX32_SOP_2, SPIA_TX32_SOP_3;
input		SPIA_TX32_EOP_0, SPIA_TX32_EOP_1;
input		SPIA_TX32_EOP_2, SPIA_TX32_EOP_3;
input		SPIA_TX32_WE_0, SPIA_TX32_WE_1;
input		SPIA_TX32_WE_2, SPIA_TX32_WE_3;
input	[2:0]	SPIA_TX32_ADDR_0, SPIA_TX32_ADDR_1;
input	[2:0]	SPIA_TX32_ADDR_2, SPIA_TX32_ADDR_3;
input		SPIA_TX32_WD_CNT_RST_0, SPIA_TX32_WD_CNT_RST_1;
input		SPIA_TX32_WD_CNT_RST_2, SPIA_TX32_WD_CNT_RST_3;
input           SPIA_TX32_LINK_DIS_0, SPIA_TX32_LINK_DIS_1;
input           SPIA_TX32_LINK_DIS_2, SPIA_TX32_LINK_DIS_3;
input		SPIA_TREFCLK_X8;
//SPIA TX Interface Outputs. All Banks in 32-bit mode.
output	[7:0]	SPIA_TX32_PORT_ID ;
output	[1:0]   SPIA_TX32_STAT;
output	[3:0]	SPIA_TX32_BURST_VAL;
output		SPIA_TX32_FIFO_FULL_0, SPIA_TX32_FIFO_FULL_1;
output		SPIA_TX32_FIFO_FULL_2, SPIA_TX32_FIFO_FULL_3;
//SPIB TX Interface Inputs. All Banks in 32-bit mode.
input	[31:0]	SPIB_TX32_DATA_0;
input	[31:0]	SPIB_TX32_DATA_1;
input	[31:0]	SPIB_TX32_DATA_2;
input	[31:0]	SPIB_TX32_DATA_3;
input	[7:0]	SPIB_TX32_PORT_0;
input	[7:0]	SPIB_TX32_PORT_1;
input	[7:0]	SPIB_TX32_PORT_2;
input	[7:0]	SPIB_TX32_PORT_3;
input	[3:0]	SPIB_TX32_BE_0;
input	[3:0]	SPIB_TX32_BE_1;
input	[3:0]	SPIB_TX32_BE_2;
input	[3:0]	SPIB_TX32_BE_3;
input		SPIB_TX32_CLK_0, SPIB_TX32_CLK_1;
input		SPIB_TX32_CLK_2, SPIB_TX32_CLK_3;
input		SPIB_TX32_ERR_0, SPIB_TX32_ERR_1;
input		SPIB_TX32_ERR_2, SPIB_TX32_ERR_3;
input		SPIB_TX32_SOP_0, SPIB_TX32_SOP_1;
input		SPIB_TX32_SOP_2, SPIB_TX32_SOP_3;
input		SPIB_TX32_EOP_0, SPIB_TX32_EOP_1;
input		SPIB_TX32_EOP_2, SPIB_TX32_EOP_3;
input		SPIB_TX32_WE_0, SPIB_TX32_WE_1;
input		SPIB_TX32_WE_2, SPIB_TX32_WE_3;
input	[2:0]	SPIB_TX32_ADDR_0, SPIB_TX32_ADDR_1;
input	[2:0]	SPIB_TX32_ADDR_2, SPIB_TX32_ADDR_3;
input		SPIB_TX32_WD_CNT_RST_0, SPIB_TX32_WD_CNT_RST_1;
input		SPIB_TX32_WD_CNT_RST_2, SPIB_TX32_WD_CNT_RST_3;
input           SPIB_TX32_LINK_DIS_0, SPIB_TX32_LINK_DIS_1;
input           SPIB_TX32_LINK_DIS_2, SPIB_TX32_LINK_DIS_3;
input		SPIB_TREFCLK_X8;
//SPIB TX Interface Outputs. All Banks in 32-bit mode.
output	[7:0]	SPIB_TX32_PORT_ID;
output	[1:0]   SPIB_TX32_STAT;
output	[3:0]	SPIB_TX32_BURST_VAL;
output		SPIB_TX32_FIFO_FULL_0, SPIB_TX32_FIFO_FULL_1;
output		SPIB_TX32_FIFO_FULL_2, SPIB_TX32_FIFO_FULL_3;


//Misc Pins.
input	[1:0]	TESTMDN;
input		PDN, TRISTN, TESTCLK;

output		ARLSCLK_F;
output		ATREFCLK_F;
input		SPI_SATM_A, SPI_DATM_A;
input	[2:0]	SPI_DLYTAP_A;
input		FPGA_RESET_S4A;
input		ASTOP_ON_EOP0, ASTOP_ON_EOP1, ASTOP_ON_EOP2, ASTOP_ON_EOP3;
output		BRLSCLK_F;
output		BTREFCLK_F;
input		SPI_SATM_B, SPI_DATM_B;
input	[2:0]	SPI_DLYTAP_B;
input		FPGA_RESET_S4B;
input		BSTOP_ON_EOP0, BSTOP_ON_EOP1, BSTOP_ON_EOP2, BSTOP_ON_EOP3;
//SPIA RX APIO
input	[15:0]	ARDATN;
input	[15:0]	ARDATP;
input		ARCTLN, ARCTLP;
input		ARDCLKN, ARDCLKP;
output		RSCLKA;
output	[1:0]	RSTATA;
output		ARSCLKN, ARSCLKP;
output	[1:0]	ARSTATN, ARSTATP;
//SPIB RX APIO
input	[15:0]	BRDATN;
input	[15:0]	BRDATP;
input		BRCTLN, BRCTLP;
input		BRDCLKN, BRDCLKP;
output		RSCLKB;
output	[1:0]	RSTATB;
output		BRSCLKN, BRSCLKP;
output	[1:0]	BRSTATN, BRSTATP;
input		SYS_RST_N;
//SPIA TX APIO
input		TSCLKA;
input	[1:0]	TSTATA; 
input		ATSCLKN, ATSCLKP;
input	[1:0]	ATSTATN, ATSTATP;
output	[15:0]	ATDATN, ATDATP;
output		ATCTLN, ATCTLP;
output		ATDCLKN, ATDCLKP;
input		ATREFCLK;
//SPIB TX APIO
input		TSCLKB;
input	[1:0]	TSTATB; 
input		BTSCLKN, BTSCLKP;
input	[1:0]	BTSTATN, BTSTATP;
output	[15:0]	BTDATN, BTDATP;
output		BTCTLN, BTCTLP;
output		BTDCLKN, BTDCLKP;
input		BTREFCLK;
// SYSBUS CONNECTS
input  		DONE;
input  		GSRN_TOA;
input  [17:0] 	HADDR;
input  		HBURST;
input  		HCLK;
input  		HREADY_IN;
input  		HRESET_N;
input  		HSEL;
input  [1:0] 	HSIZE;
input  [1:0] 	HTRANS;
input  [35:0] 	HWDATA;
input  		HWRITE;
input  		PWRUPRES;
input  		TRI_IO;
output 		ASB_EN_SLI;
output 		ASB_IRQ_SLI;
output [35:0] 	HRDATA;
output 		HREADY_OUT;
output [1:0] 	HRESP;
//Serdes APIO
//Inputs
input		HDINN_A, HDINN_B, HDINN_C, HDINN_D;
input		HDINP_A, HDINP_B, HDINP_C, HDINP_D;
input		REFCLKN, REFCLKP;
output		HDOUTN_A, HDOUTN_B, HDOUTN_C, HDOUTN_D;
output		HDOUTP_A, HDOUTP_B, HDOUTP_C, HDOUTP_D;
output		REXT, REXTN;
//Memory Controller
//APIOs
inout		PMIC, PMICN;
inout	[35:0]	PMIQ;
inout		MCREFCLK;
inout	[17:0]	PMIA;
inout	[35:0]	PMID;
inout		PMIWN, PMIRN;
inout		PMIK, PMIKN;
input		RESETN;
//Memory Controller Interface
input	[73:0]	F_MC_WD;
input	[31:0]	F_MC_WI;
input	[31:0]	F_MC_RI;
input		F_MC_WCLK, F_MC_RCLK;
input		F_MC_WIFIFO_WE, F_MC_WDFIFO_WE;
input		F_MC_RIFIFO_WE, F_MC_RDFIFO_RE;
output	[71:0]	MC_RD;
output		MC_RDFIFO_EMPTY, MC_RIFIFO_FULL, MC_WDFIFO_FULL, MC_WIFIFO_FULL;
output		MC_SYSCLK;
input		F_MC_REFCLK, FPGA_RESET_MC;
wire  fpsc_vlo;
wire  fpsc_vhi;

VLO fpsc_vlo_inst (.Z(fpsc_vlo));
VHI fpsc_vhi_inst (.Z(fpsc_vhi));


//Instantiate Core

orspi_core	orspi_core_inst (

 .ALVCTAP1(ALVCTAP1),
 .ALVCTAP2(ALVCTAP2),
 .ALVCTAP3(ALVCTAP3),
 .ALVCTAP4(ALVCTAP4),
 .ALVCTAP5(ALVCTAP5),
 .ARCTLN(ARCTLN),
 .ARCTLP(ARCTLP),
 .ARDAT0N(ARDATN[0]),
 .ARDAT0P(ARDATP[0]),
 .ARDAT10N(ARDATN[10]),
 .ARDAT10P(ARDATP[10]),
 .ARDAT11N(ARDATN[11]),
 .ARDAT11P(ARDATP[11]),
 .ARDAT12N(ARDATN[12]),
 .ARDAT12P(ARDATP[12]),
 .ARDAT13N(ARDATN[13]),
 .ARDAT13P(ARDATP[13]),
 .ARDAT14N(ARDATN[14]),
 .ARDAT14P(ARDATP[14]),
 .ARDAT15N(ARDATN[15]),
 .ARDAT15P(ARDATP[15]),
 .ARDAT1N(ARDATN[1]),
 .ARDAT1P(ARDATP[1]),
 .ARDAT2N(ARDATN[2]),
 .ARDAT2P(ARDATP[2]),
 .ARDAT3N(ARDATN[3]),
 .ARDAT3P(ARDATP[3]),
 .ARDAT4N(ARDATN[4]),
 .ARDAT4P(ARDATP[4]),
 .ARDAT5N(ARDATN[5]),
 .ARDAT5P(ARDATP[5]),
 .ARDAT6N(ARDATN[6]),
 .ARDAT6P(ARDATP[6]),
 .ARDAT7N(ARDATN[7]),
 .ARDAT7P(ARDATP[7]),
 .ARDAT8N(ARDATN[8]),
 .ARDAT8P(ARDATP[8]),
 .ARDAT9N(ARDATN[9]),
 .ARDAT9P(ARDATP[9]),
 .ARDCLKN(ARDCLKN),
 .ARDCLKP(ARDCLKP),
 .ASTOP_ON_EOP0(ASTOP_ON_EOP0),
 .ASTOP_ON_EOP1(ASTOP_ON_EOP1),
 .ASTOP_ON_EOP2(ASTOP_ON_EOP2),
 .ASTOP_ON_EOP3(ASTOP_ON_EOP3),
 .ARX_A0_2(SPIA_RX32_ADDR_0[2]),
 .ARX_A0_1(SPIA_RX32_ADDR_0[1]),
 .ARX_A0_0(SPIA_RX32_ADDR_0[0]),
 .ARX_A1_2(SPIA_RX32_ADDR_1[2]),
 .ARX_A1_1(SPIA_RX32_ADDR_1[1]),
 .ARX_A1_0(SPIA_RX32_ADDR_1[0]),
 .ARX_A2_2(SPIA_RX32_ADDR_2[2]),
 .ARX_A2_1(SPIA_RX32_ADDR_2[1]),
 .ARX_A2_0(SPIA_RX32_ADDR_2[0]),
 .ARX_A3_2(SPIA_RX32_ADDR_3[2]),
 .ARX_A3_1(SPIA_RX32_ADDR_3[1]),
 .ARX_A3_0(SPIA_RX32_ADDR_3[0]),
 .ARX_CLK0(SPIA_RX32_CLK_0),
 .ARX_CLK1(SPIA_RX32_CLK_1),
 .ARX_CLK2(SPIA_RX32_CLK_2),
 .ARX_CLK3(SPIA_RX32_CLK_3),
 .ARX_EXT_STATUS_ENABLE(SPIA_RX32_EXT_STAT_EN),
 .ARX_FPGA_PORT_ID_7(SPIA_RX32_PORT_ID[7]),
 .ARX_FPGA_PORT_ID_6(SPIA_RX32_PORT_ID[6]),
 .ARX_FPGA_PORT_ID_5(SPIA_RX32_PORT_ID[5]),
 .ARX_FPGA_PORT_ID_4(SPIA_RX32_PORT_ID[4]),
 .ARX_FPGA_PORT_ID_3(SPIA_RX32_PORT_ID[3]),
 .ARX_FPGA_PORT_ID_2(SPIA_RX32_PORT_ID[2]),
 .ARX_FPGA_PORT_ID_1(SPIA_RX32_PORT_ID[1]),
 .ARX_FPGA_PORT_ID_0(SPIA_RX32_PORT_ID[0]),
 .ARX_PORT_STATUS_1(SPIA_RX32_STAT[1]),
 .ARX_PORT_STATUS_0(SPIA_RX32_STAT[0]),
 .ARX_PSS_CLK(SPIA_RX32_PSS_CLK),
 .ARX_PSS_WE(SPIA_RX32_PSS_WE),
 .ARX_RE0(SPIA_RX32_RD_0),
 .ARX_RE1(SPIA_RX32_RD_1),
 .ARX_RE2(SPIA_RX32_RD_2),
 .ARX_RE3(SPIA_RX32_RD_3),
 .ATREFCLK(ATREFCLK),
 .ATX_A0_2(SPIA_TX32_ADDR_0[2]),
 .ATX_A0_1(SPIA_TX32_ADDR_0[1]),
 .ATX_A0_0(SPIA_TX32_ADDR_0[0]),
 .ATX_A1_2(SPIA_TX32_ADDR_1[2]),
 .ATX_A1_1(SPIA_TX32_ADDR_1[1]),
 .ATX_A1_0(SPIA_TX32_ADDR_1[0]),
 .ATX_A2_2(SPIA_TX32_ADDR_2[2]),
 .ATX_A2_1(SPIA_TX32_ADDR_2[1]),
 .ATX_A2_0(SPIA_TX32_ADDR_2[0]),
 .ATX_A3_2(SPIA_TX32_ADDR_3[2]),
 .ATX_A3_1(SPIA_TX32_ADDR_3[1]),
 .ATX_A3_0(SPIA_TX32_ADDR_3[0]),
 .ATX_CLK0(SPIA_TX32_CLK_0),
 .ATX_CLK1(SPIA_TX32_CLK_1),
 .ATX_CLK2(SPIA_TX32_CLK_2),
 .ATX_CLK3(SPIA_TX32_CLK_3),
 .ATX_D0_39(fpsc_vlo),
 .ATX_D0_38(SPIA_TX32_ERR_0),
 .ATX_D0_37(SPIA_TX32_BE_0[3]),
 .ATX_D0_36(SPIA_TX32_BE_0[2]),
 .ATX_D0_35(SPIA_TX32_BE_0[1]),
 .ATX_D0_34(SPIA_TX32_BE_0[0]),
 .ATX_D0_33(SPIA_TX32_EOP_0),
 .ATX_D0_32(SPIA_TX32_SOP_0),
 .ATX_D0_31(SPIA_TX32_DATA_0[31]),
 .ATX_D0_30(SPIA_TX32_DATA_0[30]),
 .ATX_D0_29(SPIA_TX32_DATA_0[29]),
 .ATX_D0_28(SPIA_TX32_DATA_0[28]),
 .ATX_D0_27(SPIA_TX32_DATA_0[27]),
 .ATX_D0_26(SPIA_TX32_DATA_0[26]),
 .ATX_D0_25(SPIA_TX32_DATA_0[25]),
 .ATX_D0_24(SPIA_TX32_DATA_0[24]),
 .ATX_D0_23(SPIA_TX32_DATA_0[23]),
 .ATX_D0_22(SPIA_TX32_DATA_0[22]),
 .ATX_D0_21(SPIA_TX32_DATA_0[21]),
 .ATX_D0_20(SPIA_TX32_DATA_0[20]),
 .ATX_D0_19(SPIA_TX32_DATA_0[19]),
 .ATX_D0_18(SPIA_TX32_DATA_0[18]),
 .ATX_D0_17(SPIA_TX32_DATA_0[17]),
 .ATX_D0_16(SPIA_TX32_DATA_0[16]),
 .ATX_D0_15(SPIA_TX32_DATA_0[15]),
 .ATX_D0_14(SPIA_TX32_DATA_0[14]),
 .ATX_D0_13(SPIA_TX32_DATA_0[13]),
 .ATX_D0_12(SPIA_TX32_DATA_0[12]),
 .ATX_D0_11(SPIA_TX32_DATA_0[11]),
 .ATX_D0_10(SPIA_TX32_DATA_0[10]),
 .ATX_D0_9(SPIA_TX32_DATA_0[9]),
 .ATX_D0_8(SPIA_TX32_DATA_0[8]),
 .ATX_D0_7(SPIA_TX32_DATA_0[7]),
 .ATX_D0_6(SPIA_TX32_DATA_0[6]),
 .ATX_D0_5(SPIA_TX32_DATA_0[5]),
 .ATX_D0_4(SPIA_TX32_DATA_0[4]),
 .ATX_D0_3(SPIA_TX32_DATA_0[3]),
 .ATX_D0_2(SPIA_TX32_DATA_0[2]),
 .ATX_D0_1(SPIA_TX32_DATA_0[1]),
 .ATX_D0_0(SPIA_TX32_DATA_0[0]),
 .ATX_D1_39(fpsc_vlo),
 .ATX_D1_38(SPIA_TX32_ERR_1),
 .ATX_D1_37(SPIA_TX32_BE_1[3]),
 .ATX_D1_36(SPIA_TX32_BE_1[2]),
 .ATX_D1_35(SPIA_TX32_BE_1[1]),
 .ATX_D1_34(SPIA_TX32_BE_1[0]),
 .ATX_D1_33(SPIA_TX32_EOP_1),
 .ATX_D1_32(SPIA_TX32_SOP_1),
 .ATX_D1_31(SPIA_TX32_DATA_1[31]),
 .ATX_D1_30(SPIA_TX32_DATA_1[30]),
 .ATX_D1_29(SPIA_TX32_DATA_1[29]),
 .ATX_D1_28(SPIA_TX32_DATA_1[28]),
 .ATX_D1_27(SPIA_TX32_DATA_1[27]),
 .ATX_D1_26(SPIA_TX32_DATA_1[26]),
 .ATX_D1_25(SPIA_TX32_DATA_1[25]),
 .ATX_D1_24(SPIA_TX32_DATA_1[24]),
 .ATX_D1_23(SPIA_TX32_DATA_1[23]),
 .ATX_D1_22(SPIA_TX32_DATA_1[22]),
 .ATX_D1_21(SPIA_TX32_DATA_1[21]),
 .ATX_D1_20(SPIA_TX32_DATA_1[20]),
 .ATX_D1_19(SPIA_TX32_DATA_1[19]),
 .ATX_D1_18(SPIA_TX32_DATA_1[18]),
 .ATX_D1_17(SPIA_TX32_DATA_1[17]),
 .ATX_D1_16(SPIA_TX32_DATA_1[16]),
 .ATX_D1_15(SPIA_TX32_DATA_1[15]),
 .ATX_D1_14(SPIA_TX32_DATA_1[14]),
 .ATX_D1_13(SPIA_TX32_DATA_1[13]),
 .ATX_D1_12(SPIA_TX32_DATA_1[12]),
 .ATX_D1_11(SPIA_TX32_DATA_1[11]),
 .ATX_D1_10(SPIA_TX32_DATA_1[10]),
 .ATX_D1_9(SPIA_TX32_DATA_1[9]),
 .ATX_D1_8(SPIA_TX32_DATA_1[8]),
 .ATX_D1_7(SPIA_TX32_DATA_1[7]),
 .ATX_D1_6(SPIA_TX32_DATA_1[6]),
 .ATX_D1_5(SPIA_TX32_DATA_1[5]),
 .ATX_D1_4(SPIA_TX32_DATA_1[4]),
 .ATX_D1_3(SPIA_TX32_DATA_1[3]),
 .ATX_D1_2(SPIA_TX32_DATA_1[2]),
 .ATX_D1_1(SPIA_TX32_DATA_1[1]),
 .ATX_D1_0(SPIA_TX32_DATA_1[0]),
 .ATX_D2_39(fpsc_vlo),
 .ATX_D2_38(SPIA_TX32_ERR_2),
 .ATX_D2_37(SPIA_TX32_BE_2[3]),
 .ATX_D2_36(SPIA_TX32_BE_2[2]),
 .ATX_D2_35(SPIA_TX32_BE_2[1]),
 .ATX_D2_34(SPIA_TX32_BE_2[0]),
 .ATX_D2_33(SPIA_TX32_EOP_2),
 .ATX_D2_32(SPIA_TX32_SOP_2),
 .ATX_D2_31(SPIA_TX32_DATA_2[31]),
 .ATX_D2_30(SPIA_TX32_DATA_2[30]),
 .ATX_D2_29(SPIA_TX32_DATA_2[29]),
 .ATX_D2_28(SPIA_TX32_DATA_2[28]),
 .ATX_D2_27(SPIA_TX32_DATA_2[27]),
 .ATX_D2_26(SPIA_TX32_DATA_2[26]),
 .ATX_D2_25(SPIA_TX32_DATA_2[25]),
 .ATX_D2_24(SPIA_TX32_DATA_2[24]),
 .ATX_D2_23(SPIA_TX32_DATA_2[23]),
 .ATX_D2_22(SPIA_TX32_DATA_2[22]),
 .ATX_D2_21(SPIA_TX32_DATA_2[21]),
 .ATX_D2_20(SPIA_TX32_DATA_2[20]),
 .ATX_D2_19(SPIA_TX32_DATA_2[19]),
 .ATX_D2_18(SPIA_TX32_DATA_2[18]),
 .ATX_D2_17(SPIA_TX32_DATA_2[17]),
 .ATX_D2_16(SPIA_TX32_DATA_2[16]),
 .ATX_D2_15(SPIA_TX32_DATA_2[15]),
 .ATX_D2_14(SPIA_TX32_DATA_2[14]),
 .ATX_D2_13(SPIA_TX32_DATA_2[13]),
 .ATX_D2_12(SPIA_TX32_DATA_2[12]),
 .ATX_D2_11(SPIA_TX32_DATA_2[11]),
 .ATX_D2_10(SPIA_TX32_DATA_2[10]),
 .ATX_D2_9(SPIA_TX32_DATA_2[9]),
 .ATX_D2_8(SPIA_TX32_DATA_2[8]),
 .ATX_D2_7(SPIA_TX32_DATA_2[7]),
 .ATX_D2_6(SPIA_TX32_DATA_2[6]),
 .ATX_D2_5(SPIA_TX32_DATA_2[5]),
 .ATX_D2_4(SPIA_TX32_DATA_2[4]),
 .ATX_D2_3(SPIA_TX32_DATA_2[3]),
 .ATX_D2_2(SPIA_TX32_DATA_2[2]),
 .ATX_D2_1(SPIA_TX32_DATA_2[1]),
 .ATX_D2_0(SPIA_TX32_DATA_2[0]),
 .ATX_D3_39(fpsc_vlo),
 .ATX_D3_38(SPIA_TX32_ERR_3),
 .ATX_D3_37(SPIA_TX32_BE_3[3]),
 .ATX_D3_36(SPIA_TX32_BE_3[2]),
 .ATX_D3_35(SPIA_TX32_BE_3[1]),
 .ATX_D3_34(SPIA_TX32_BE_3[0]),
 .ATX_D3_33(SPIA_TX32_EOP_3),
 .ATX_D3_32(SPIA_TX32_SOP_3),
 .ATX_D3_31(SPIA_TX32_DATA_3[31]),
 .ATX_D3_30(SPIA_TX32_DATA_3[30]),
 .ATX_D3_29(SPIA_TX32_DATA_3[29]),
 .ATX_D3_28(SPIA_TX32_DATA_3[28]),
 .ATX_D3_27(SPIA_TX32_DATA_3[27]),
 .ATX_D3_26(SPIA_TX32_DATA_3[26]),
 .ATX_D3_25(SPIA_TX32_DATA_3[25]),
 .ATX_D3_24(SPIA_TX32_DATA_3[24]),
 .ATX_D3_23(SPIA_TX32_DATA_3[23]),
 .ATX_D3_22(SPIA_TX32_DATA_3[22]),
 .ATX_D3_21(SPIA_TX32_DATA_3[21]),
 .ATX_D3_20(SPIA_TX32_DATA_3[20]),
 .ATX_D3_19(SPIA_TX32_DATA_3[19]),
 .ATX_D3_18(SPIA_TX32_DATA_3[18]),
 .ATX_D3_17(SPIA_TX32_DATA_3[17]),
 .ATX_D3_16(SPIA_TX32_DATA_3[16]),
 .ATX_D3_15(SPIA_TX32_DATA_3[15]),
 .ATX_D3_14(SPIA_TX32_DATA_3[14]),
 .ATX_D3_13(SPIA_TX32_DATA_3[13]),
 .ATX_D3_12(SPIA_TX32_DATA_3[12]),
 .ATX_D3_11(SPIA_TX32_DATA_3[11]),
 .ATX_D3_10(SPIA_TX32_DATA_3[10]),
 .ATX_D3_9(SPIA_TX32_DATA_3[9]),
 .ATX_D3_8(SPIA_TX32_DATA_3[8]),
 .ATX_D3_7(SPIA_TX32_DATA_3[7]),
 .ATX_D3_6(SPIA_TX32_DATA_3[6]),
 .ATX_D3_5(SPIA_TX32_DATA_3[5]),
 .ATX_D3_4(SPIA_TX32_DATA_3[4]),
 .ATX_D3_3(SPIA_TX32_DATA_3[3]),
 .ATX_D3_2(SPIA_TX32_DATA_3[2]),
 .ATX_D3_1(SPIA_TX32_DATA_3[1]),
 .ATX_D3_0(SPIA_TX32_DATA_3[0]),
 .ATX_LINK_DIS0(SPIA_TX32_LINK_DIS_0),
 .ATX_LINK_DIS1(SPIA_TX32_LINK_DIS_1),
 .ATX_LINK_DIS2(SPIA_TX32_LINK_DIS_2),
 .ATX_LINK_DIS3(SPIA_TX32_LINK_DIS_3),
 .SPIA_TREFCLK_X8(SPIA_TREFCLK_X8),
 .ATX_PORT0_7(SPIA_TX32_PORT_0[7]),
 .ATX_PORT0_6(SPIA_TX32_PORT_0[6]),
 .ATX_PORT0_5(SPIA_TX32_PORT_0[5]),
 .ATX_PORT0_4(SPIA_TX32_PORT_0[4]),
 .ATX_PORT0_3(SPIA_TX32_PORT_0[3]),
 .ATX_PORT0_2(SPIA_TX32_PORT_0[2]),
 .ATX_PORT0_1(SPIA_TX32_PORT_0[1]),
 .ATX_PORT0_0(SPIA_TX32_PORT_0[0]),
 .ATX_PORT1_7(SPIA_TX32_PORT_1[7]),
 .ATX_PORT1_6(SPIA_TX32_PORT_1[6]),
 .ATX_PORT1_5(SPIA_TX32_PORT_1[5]),
 .ATX_PORT1_4(SPIA_TX32_PORT_1[4]),
 .ATX_PORT1_3(SPIA_TX32_PORT_1[3]),
 .ATX_PORT1_2(SPIA_TX32_PORT_1[2]),
 .ATX_PORT1_1(SPIA_TX32_PORT_1[1]),
 .ATX_PORT1_0(SPIA_TX32_PORT_1[0]),
 .ATX_PORT2_7(SPIA_TX32_PORT_2[7]),
 .ATX_PORT2_6(SPIA_TX32_PORT_2[6]),
 .ATX_PORT2_5(SPIA_TX32_PORT_2[5]),
 .ATX_PORT2_4(SPIA_TX32_PORT_2[4]),
 .ATX_PORT2_3(SPIA_TX32_PORT_2[3]),
 .ATX_PORT2_2(SPIA_TX32_PORT_2[2]),
 .ATX_PORT2_1(SPIA_TX32_PORT_2[1]),
 .ATX_PORT2_0(SPIA_TX32_PORT_2[0]),
 .ATX_PORT3_7(SPIA_TX32_PORT_3[7]),
 .ATX_PORT3_6(SPIA_TX32_PORT_3[6]),
 .ATX_PORT3_5(SPIA_TX32_PORT_3[5]),
 .ATX_PORT3_4(SPIA_TX32_PORT_3[4]),
 .ATX_PORT3_3(SPIA_TX32_PORT_3[3]),
 .ATX_PORT3_2(SPIA_TX32_PORT_3[2]),
 .ATX_PORT3_1(SPIA_TX32_PORT_3[1]),
 .ATX_PORT3_0(SPIA_TX32_PORT_3[0]),
 .ATX_WE0(SPIA_TX32_WE_0),
 .ATX_WE1(SPIA_TX32_WE_1),
 .ATX_WE2(SPIA_TX32_WE_2),
 .ATX_WE3(SPIA_TX32_WE_3),
 .AWD_CNT_RST0(SPIA_TX32_WD_CNT_RST_0),
 .AWD_CNT_RST1(SPIA_TX32_WD_CNT_RST_1),
 .AWD_CNT_RST2(SPIA_TX32_WD_CNT_RST_2),
 .AWD_CNT_RST3(SPIA_TX32_WD_CNT_RST_3),
 .BLVCTAP1(BLVCTAP1),
 .BLVCTAP2(BLVCTAP2),
 .BLVCTAP3(BLVCTAP3),
 .BLVCTAP4(BLVCTAP4),
 .BLVCTAP5(BLVCTAP5),
 .BRCTLN(BRCTLN),
 .BRCTLP(BRCTLP),
 .BRDAT0N(BRDATN[0]),
 .BRDAT0P(BRDATP[0]),
 .BRDAT10N(BRDATN[10]),
 .BRDAT10P(BRDATP[10]),
 .BRDAT11N(BRDATN[11]),
 .BRDAT11P(BRDATP[11]),
 .BRDAT12N(BRDATN[12]),
 .BRDAT12P(BRDATP[12]),
 .BRDAT13N(BRDATN[13]),
 .BRDAT13P(BRDATP[13]),
 .BRDAT14N(BRDATN[14]),
 .BRDAT14P(BRDATP[14]),
 .BRDAT15N(BRDATN[15]),
 .BRDAT15P(BRDATP[15]),
 .BRDAT1N(BRDATN[1]),
 .BRDAT1P(BRDATP[1]),
 .BRDAT2N(BRDATN[2]),
 .BRDAT2P(BRDATP[2]),
 .BRDAT3N(BRDATN[3]),
 .BRDAT3P(BRDATP[3]),
 .BRDAT4N(BRDATN[4]),
 .BRDAT4P(BRDATP[4]),
 .BRDAT5N(BRDATN[5]),
 .BRDAT5P(BRDATP[5]),
 .BRDAT6N(BRDATN[6]),
 .BRDAT6P(BRDATP[6]),
 .BRDAT7N(BRDATN[7]),
 .BRDAT7P(BRDATP[7]),
 .BRDAT8N(BRDATN[8]),
 .BRDAT8P(BRDATP[8]),
 .BRDAT9N(BRDATN[9]),
 .BRDAT9P(BRDATP[9]),
 .BRDCLKN(BRDCLKN),
 .BRDCLKP(BRDCLKP),
 .BRX_A0_2(SPIB_RX32_ADDR_0[2]),
 .BRX_A0_1(SPIB_RX32_ADDR_0[1]),
 .BRX_A0_0(SPIB_RX32_ADDR_0[0]),
 .BRX_A1_2(SPIB_RX32_ADDR_1[2]),
 .BRX_A1_1(SPIB_RX32_ADDR_1[1]),
 .BRX_A1_0(SPIB_RX32_ADDR_1[0]),
 .BRX_A2_2(SPIB_RX32_ADDR_2[2]),
 .BRX_A2_1(SPIB_RX32_ADDR_2[1]),
 .BRX_A2_0(SPIB_RX32_ADDR_2[0]),
 .BRX_A3_2(SPIB_RX32_ADDR_3[2]),
 .BRX_A3_1(SPIB_RX32_ADDR_3[1]),
 .BRX_A3_0(SPIB_RX32_ADDR_3[0]),
 .BRX_CLK0(SPIB_RX32_CLK_0),
 .BRX_CLK1(SPIB_RX32_CLK_1),
 .BRX_CLK2(SPIB_RX32_CLK_2),
 .BRX_CLK3(SPIB_RX32_CLK_3),
 .BRX_EXT_STATUS_ENABLE(SPIB_RX32_EXT_STAT_EN),
 .BRX_FPGA_PORT_ID_7(SPIB_RX32_PORT_ID[7]),
 .BRX_FPGA_PORT_ID_6(SPIB_RX32_PORT_ID[6]),
 .BRX_FPGA_PORT_ID_5(SPIB_RX32_PORT_ID[5]),
 .BRX_FPGA_PORT_ID_4(SPIB_RX32_PORT_ID[4]),
 .BRX_FPGA_PORT_ID_3(SPIB_RX32_PORT_ID[3]),
 .BRX_FPGA_PORT_ID_2(SPIB_RX32_PORT_ID[2]),
 .BRX_FPGA_PORT_ID_1(SPIB_RX32_PORT_ID[1]),
 .BRX_FPGA_PORT_ID_0(SPIB_RX32_PORT_ID[0]),
 .BRX_PORT_STATUS_1(SPIB_RX32_STAT[1]),
 .BRX_PORT_STATUS_0(SPIB_RX32_STAT[0]),
 .BRX_PSS_CLK(SPIB_RX32_PSS_CLK),
 .BRX_PSS_WE(SPIB_RX32_PSS_WE),
 .BRX_RE0(SPIB_RX32_RD_0),
 .BRX_RE1(SPIB_RX32_RD_1),
 .BRX_RE2(SPIB_RX32_RD_2),
 .BRX_RE3(SPIB_RX32_RD_3),
 .BS_CPTBSR(fpsc_vlo),
 .BS_MD(fpsc_vlo),
 .BS_SHBSRN(fpsc_vhi),
 .BS_TRESET(fpsc_vhi),
 .BS_UPDTBSR(fpsc_vlo),
 .BTREFCLK(BTREFCLK),
 .BTX_A0_2(SPIB_TX32_ADDR_0[2]),
 .BTX_A0_1(SPIB_TX32_ADDR_0[1]),
 .BTX_A0_0(SPIB_TX32_ADDR_0[0]),
 .BTX_A1_2(SPIB_TX32_ADDR_1[2]),
 .BTX_A1_1(SPIB_TX32_ADDR_1[1]),
 .BTX_A1_0(SPIB_TX32_ADDR_1[0]),
 .BTX_A2_2(SPIB_TX32_ADDR_2[2]),
 .BTX_A2_1(SPIB_TX32_ADDR_2[1]),
 .BTX_A2_0(SPIB_TX32_ADDR_2[0]),
 .BTX_A3_2(SPIB_TX32_ADDR_3[2]),
 .BTX_A3_1(SPIB_TX32_ADDR_3[1]),
 .BTX_A3_0(SPIB_TX32_ADDR_3[0]),
 .BTX_CLK0(SPIB_TX32_CLK_0),
 .BTX_CLK1(SPIB_TX32_CLK_1),
 .BTX_CLK2(SPIB_TX32_CLK_2),
 .BTX_CLK3(SPIB_TX32_CLK_3),
 .BTX_D0_39(fpsc_vlo),
 .BTX_D0_38(SPIB_TX32_ERR_0),
 .BTX_D0_37(SPIB_TX32_BE_0[3]),
 .BTX_D0_36(SPIB_TX32_BE_0[2]),
 .BTX_D0_35(SPIB_TX32_BE_0[1]),
 .BTX_D0_34(SPIB_TX32_BE_0[0]),
 .BTX_D0_33(SPIB_TX32_EOP_0),
 .BTX_D0_32(SPIB_TX32_SOP_0),
 .BTX_D0_31(SPIB_TX32_DATA_0[31]),
 .BTX_D0_30(SPIB_TX32_DATA_0[30]),
 .BTX_D0_29(SPIB_TX32_DATA_0[29]),
 .BTX_D0_28(SPIB_TX32_DATA_0[28]),
 .BTX_D0_27(SPIB_TX32_DATA_0[27]),
 .BTX_D0_26(SPIB_TX32_DATA_0[26]),
 .BTX_D0_25(SPIB_TX32_DATA_0[25]),
 .BTX_D0_24(SPIB_TX32_DATA_0[24]),
 .BTX_D0_23(SPIB_TX32_DATA_0[23]),
 .BTX_D0_22(SPIB_TX32_DATA_0[22]),
 .BTX_D0_21(SPIB_TX32_DATA_0[21]),
 .BTX_D0_20(SPIB_TX32_DATA_0[20]),
 .BTX_D0_19(SPIB_TX32_DATA_0[19]),
 .BTX_D0_18(SPIB_TX32_DATA_0[18]),
 .BTX_D0_17(SPIB_TX32_DATA_0[17]),
 .BTX_D0_16(SPIB_TX32_DATA_0[16]),
 .BTX_D0_15(SPIB_TX32_DATA_0[15]),
 .BTX_D0_14(SPIB_TX32_DATA_0[14]),
 .BTX_D0_13(SPIB_TX32_DATA_0[13]),
 .BTX_D0_12(SPIB_TX32_DATA_0[12]),
 .BTX_D0_11(SPIB_TX32_DATA_0[11]),
 .BTX_D0_10(SPIB_TX32_DATA_0[10]),
 .BTX_D0_9(SPIB_TX32_DATA_0[9]),
 .BTX_D0_8(SPIB_TX32_DATA_0[8]),
 .BTX_D0_7(SPIB_TX32_DATA_0[7]),
 .BTX_D0_6(SPIB_TX32_DATA_0[6]),
 .BTX_D0_5(SPIB_TX32_DATA_0[5]),
 .BTX_D0_4(SPIB_TX32_DATA_0[4]),
 .BTX_D0_3(SPIB_TX32_DATA_0[3]),
 .BTX_D0_2(SPIB_TX32_DATA_0[2]),
 .BTX_D0_1(SPIB_TX32_DATA_0[1]),
 .BTX_D0_0(SPIB_TX32_DATA_0[0]),
 .BTX_D1_39(fpsc_vlo),
 .BTX_D1_38(SPIB_TX32_ERR_1),
 .BTX_D1_37(SPIB_TX32_BE_1[3]),
 .BTX_D1_36(SPIB_TX32_BE_1[2]),
 .BTX_D1_35(SPIB_TX32_BE_1[1]),
 .BTX_D1_34(SPIB_TX32_BE_1[0]),
 .BTX_D1_33(SPIB_TX32_EOP_1),
 .BTX_D1_32(SPIB_TX32_SOP_1),
 .BTX_D1_31(SPIB_TX32_DATA_1[31]),
 .BTX_D1_30(SPIB_TX32_DATA_1[30]),
 .BTX_D1_29(SPIB_TX32_DATA_1[29]),
 .BTX_D1_28(SPIB_TX32_DATA_1[28]),
 .BTX_D1_27(SPIB_TX32_DATA_1[27]),
 .BTX_D1_26(SPIB_TX32_DATA_1[26]),
 .BTX_D1_25(SPIB_TX32_DATA_1[25]),
 .BTX_D1_24(SPIB_TX32_DATA_1[24]),
 .BTX_D1_23(SPIB_TX32_DATA_1[23]),
 .BTX_D1_22(SPIB_TX32_DATA_1[22]),
 .BTX_D1_21(SPIB_TX32_DATA_1[21]),
 .BTX_D1_20(SPIB_TX32_DATA_1[20]),
 .BTX_D1_19(SPIB_TX32_DATA_1[19]),
 .BTX_D1_18(SPIB_TX32_DATA_1[18]),
 .BTX_D1_17(SPIB_TX32_DATA_1[17]),
 .BTX_D1_16(SPIB_TX32_DATA_1[16]),
 .BTX_D1_15(SPIB_TX32_DATA_1[15]),
 .BTX_D1_14(SPIB_TX32_DATA_1[14]),
 .BTX_D1_13(SPIB_TX32_DATA_1[13]),
 .BTX_D1_12(SPIB_TX32_DATA_1[12]),
 .BTX_D1_11(SPIB_TX32_DATA_1[11]),
 .BTX_D1_10(SPIB_TX32_DATA_1[10]),
 .BTX_D1_9(SPIB_TX32_DATA_1[9]),
 .BTX_D1_8(SPIB_TX32_DATA_1[8]),
 .BTX_D1_7(SPIB_TX32_DATA_1[7]),
 .BTX_D1_6(SPIB_TX32_DATA_1[6]),
 .BTX_D1_5(SPIB_TX32_DATA_1[5]),
 .BTX_D1_4(SPIB_TX32_DATA_1[4]),
 .BTX_D1_3(SPIB_TX32_DATA_1[3]),
 .BTX_D1_2(SPIB_TX32_DATA_1[2]),
 .BTX_D1_1(SPIB_TX32_DATA_1[1]),
 .BTX_D1_0(SPIB_TX32_DATA_1[0]),
 .BTX_D2_39(fpsc_vlo),
 .BTX_D2_38(SPIB_TX32_ERR_2),
 .BTX_D2_37(SPIB_TX32_BE_2[3]),
 .BTX_D2_36(SPIB_TX32_BE_2[2]),
 .BTX_D2_35(SPIB_TX32_BE_2[1]),
 .BTX_D2_34(SPIB_TX32_BE_2[0]),
 .BTX_D2_33(SPIB_TX32_EOP_2),
 .BTX_D2_32(SPIB_TX32_SOP_2),
 .BTX_D2_31(SPIB_TX32_DATA_2[31]),
 .BTX_D2_30(SPIB_TX32_DATA_2[30]),
 .BTX_D2_29(SPIB_TX32_DATA_2[29]),
 .BTX_D2_28(SPIB_TX32_DATA_2[28]),
 .BTX_D2_27(SPIB_TX32_DATA_2[27]),
 .BTX_D2_26(SPIB_TX32_DATA_2[26]),
 .BTX_D2_25(SPIB_TX32_DATA_2[25]),
 .BTX_D2_24(SPIB_TX32_DATA_2[24]),
 .BTX_D2_23(SPIB_TX32_DATA_2[23]),
 .BTX_D2_22(SPIB_TX32_DATA_2[22]),
 .BTX_D2_21(SPIB_TX32_DATA_2[21]),
 .BTX_D2_20(SPIB_TX32_DATA_2[20]),
 .BTX_D2_19(SPIB_TX32_DATA_2[19]),
 .BTX_D2_18(SPIB_TX32_DATA_2[18]),
 .BTX_D2_17(SPIB_TX32_DATA_2[17]),
 .BTX_D2_16(SPIB_TX32_DATA_2[16]),
 .BTX_D2_15(SPIB_TX32_DATA_2[15]),
 .BTX_D2_14(SPIB_TX32_DATA_2[14]),
 .BTX_D2_13(SPIB_TX32_DATA_2[13]),
 .BTX_D2_12(SPIB_TX32_DATA_2[12]),
 .BTX_D2_11(SPIB_TX32_DATA_2[11]),
 .BTX_D2_10(SPIB_TX32_DATA_2[10]),
 .BTX_D2_9(SPIB_TX32_DATA_2[9]),
 .BTX_D2_8(SPIB_TX32_DATA_2[8]),
 .BTX_D2_7(SPIB_TX32_DATA_2[7]),
 .BTX_D2_6(SPIB_TX32_DATA_2[6]),
 .BTX_D2_5(SPIB_TX32_DATA_2[5]),
 .BTX_D2_4(SPIB_TX32_DATA_2[4]),
 .BTX_D2_3(SPIB_TX32_DATA_2[3]),
 .BTX_D2_2(SPIB_TX32_DATA_2[2]),
 .BTX_D2_1(SPIB_TX32_DATA_2[1]),
 .BTX_D2_0(SPIB_TX32_DATA_2[0]),
 .BTX_D3_39(fpsc_vlo),
 .BTX_D3_38(SPIB_TX32_ERR_3),
 .BTX_D3_37(SPIB_TX32_BE_3[3]),
 .BTX_D3_36(SPIB_TX32_BE_3[2]),
 .BTX_D3_35(SPIB_TX32_BE_3[1]),
 .BTX_D3_34(SPIB_TX32_BE_3[0]),
 .BTX_D3_33(SPIB_TX32_EOP_3),
 .BTX_D3_32(SPIB_TX32_SOP_3),
 .BTX_D3_31(SPIB_TX32_DATA_3[31]),
 .BTX_D3_30(SPIB_TX32_DATA_3[30]),
 .BTX_D3_29(SPIB_TX32_DATA_3[29]),
 .BTX_D3_28(SPIB_TX32_DATA_3[28]),
 .BTX_D3_27(SPIB_TX32_DATA_3[27]),
 .BTX_D3_26(SPIB_TX32_DATA_3[26]),
 .BTX_D3_25(SPIB_TX32_DATA_3[25]),
 .BTX_D3_24(SPIB_TX32_DATA_3[24]),
 .BTX_D3_23(SPIB_TX32_DATA_3[23]),
 .BTX_D3_22(SPIB_TX32_DATA_3[22]),
 .BTX_D3_21(SPIB_TX32_DATA_3[21]),
 .BTX_D3_20(SPIB_TX32_DATA_3[20]),
 .BTX_D3_19(SPIB_TX32_DATA_3[19]),
 .BTX_D3_18(SPIB_TX32_DATA_3[18]),
 .BTX_D3_17(SPIB_TX32_DATA_3[17]),
 .BTX_D3_16(SPIB_TX32_DATA_3[16]),
 .BTX_D3_15(SPIB_TX32_DATA_3[15]),
 .BTX_D3_14(SPIB_TX32_DATA_3[14]),
 .BTX_D3_13(SPIB_TX32_DATA_3[13]),
 .BTX_D3_12(SPIB_TX32_DATA_3[12]),
 .BTX_D3_11(SPIB_TX32_DATA_3[11]),
 .BTX_D3_10(SPIB_TX32_DATA_3[10]),
 .BTX_D3_9(SPIB_TX32_DATA_3[9]),
 .BTX_D3_8(SPIB_TX32_DATA_3[8]),
 .BTX_D3_7(SPIB_TX32_DATA_3[7]),
 .BTX_D3_6(SPIB_TX32_DATA_3[6]),
 .BTX_D3_5(SPIB_TX32_DATA_3[5]),
 .BTX_D3_4(SPIB_TX32_DATA_3[4]),
 .BTX_D3_3(SPIB_TX32_DATA_3[3]),
 .BTX_D3_2(SPIB_TX32_DATA_3[2]),
 .BTX_D3_1(SPIB_TX32_DATA_3[1]),
 .BTX_D3_0(SPIB_TX32_DATA_3[0]),
 .BTX_LINK_DIS0(SPIB_TX32_LINK_DIS_0),
 .BTX_LINK_DIS1(SPIB_TX32_LINK_DIS_1),
 .BTX_LINK_DIS2(SPIB_TX32_LINK_DIS_2),
 .BTX_LINK_DIS3(SPIB_TX32_LINK_DIS_3),
 .SPIB_TREFCLK_X8(SPIB_TREFCLK_X8),
 .BTX_PORT0_7(SPIB_TX32_PORT_0[7]),
 .BTX_PORT0_6(SPIB_TX32_PORT_0[6]),
 .BTX_PORT0_5(SPIB_TX32_PORT_0[5]),
 .BTX_PORT0_4(SPIB_TX32_PORT_0[4]),
 .BTX_PORT0_3(SPIB_TX32_PORT_0[3]),
 .BTX_PORT0_2(SPIB_TX32_PORT_0[2]),
 .BTX_PORT0_1(SPIB_TX32_PORT_0[1]),
 .BTX_PORT0_0(SPIB_TX32_PORT_0[0]),
 .BTX_PORT1_7(SPIB_TX32_PORT_1[7]),
 .BTX_PORT1_6(SPIB_TX32_PORT_1[6]),
 .BTX_PORT1_5(SPIB_TX32_PORT_1[5]),
 .BTX_PORT1_4(SPIB_TX32_PORT_1[4]),
 .BTX_PORT1_3(SPIB_TX32_PORT_1[3]),
 .BTX_PORT1_2(SPIB_TX32_PORT_1[2]),
 .BTX_PORT1_1(SPIB_TX32_PORT_1[1]),
 .BTX_PORT1_0(SPIB_TX32_PORT_1[0]),
 .BTX_PORT2_7(SPIB_TX32_PORT_2[7]),
 .BTX_PORT2_6(SPIB_TX32_PORT_2[6]),
 .BTX_PORT2_5(SPIB_TX32_PORT_2[5]),
 .BTX_PORT2_4(SPIB_TX32_PORT_2[4]),
 .BTX_PORT2_3(SPIB_TX32_PORT_2[3]),
 .BTX_PORT2_2(SPIB_TX32_PORT_2[2]),
 .BTX_PORT2_1(SPIB_TX32_PORT_2[1]),
 .BTX_PORT2_0(SPIB_TX32_PORT_2[0]),
 .BTX_PORT3_7(SPIB_TX32_PORT_3[7]),
 .BTX_PORT3_6(SPIB_TX32_PORT_3[6]),
 .BTX_PORT3_5(SPIB_TX32_PORT_3[5]),
 .BTX_PORT3_4(SPIB_TX32_PORT_3[4]),
 .BTX_PORT3_3(SPIB_TX32_PORT_3[3]),
 .BTX_PORT3_2(SPIB_TX32_PORT_3[2]),
 .BTX_PORT3_1(SPIB_TX32_PORT_3[1]),
 .BTX_PORT3_0(SPIB_TX32_PORT_3[0]),
 .BTX_WE0(SPIB_TX32_WE_0),
 .BTX_WE1(SPIB_TX32_WE_1),
 .BTX_WE2(SPIB_TX32_WE_2),
 .BTX_WE3(SPIB_TX32_WE_3),
 .BWD_CNT_RST0(SPIB_TX32_WD_CNT_RST_0),
 .BWD_CNT_RST1(SPIB_TX32_WD_CNT_RST_1),
 .BWD_CNT_RST2(SPIB_TX32_WD_CNT_RST_2),
 .BWD_CNT_RST3(SPIB_TX32_WD_CNT_RST_3),
 .DIVIDE_1(fpsc_vlo),
 .DIVIDE_0(fpsc_vlo),
 .DONE(DONE),
 .ENABLE_SPI4_B(fpsc_vhi),
 .EXT_1K(EXT_1K),
 //Memory Controller Interface inputs pins
 .FPGA_RESET_MC(FPGA_RESET_MC),
 .F_MC_WCLK(F_MC_WCLK),
 .F_MC_RCLK(F_MC_RCLK),
 .F_MC_RDFIFO_RE(F_MC_RDFIFO_RE),
 .F_MC_REFCLK(F_MC_REFCLK),
 .F_MC_RI_31(F_MC_RI[31]),
 .F_MC_RI_30(F_MC_RI[30]),
 .F_MC_RI_29(F_MC_RI[29]),
 .F_MC_RI_28(F_MC_RI[28]),
 .F_MC_RI_27(F_MC_RI[27]),
 .F_MC_RI_26(F_MC_RI[26]),
 .F_MC_RI_25(F_MC_RI[25]),
 .F_MC_RI_24(F_MC_RI[24]),
 .F_MC_RI_23(F_MC_RI[23]),
 .F_MC_RI_22(F_MC_RI[22]),
 .F_MC_RI_21(F_MC_RI[21]),
 .F_MC_RI_20(F_MC_RI[20]),
 .F_MC_RI_19(F_MC_RI[19]),
 .F_MC_RI_18(F_MC_RI[18]),
 .F_MC_RI_17(F_MC_RI[17]),
 .F_MC_RI_16(F_MC_RI[16]),
 .F_MC_RI_15(F_MC_RI[15]),
 .F_MC_RI_14(F_MC_RI[14]),
 .F_MC_RI_13(F_MC_RI[13]),
 .F_MC_RI_12(F_MC_RI[12]),
 .F_MC_RI_11(F_MC_RI[11]),
 .F_MC_RI_10(F_MC_RI[10]),
 .F_MC_RI_9(F_MC_RI[9]),
 .F_MC_RI_8(F_MC_RI[8]),
 .F_MC_RI_7(F_MC_RI[7]),
 .F_MC_RI_6(F_MC_RI[6]),
 .F_MC_RI_5(F_MC_RI[5]),
 .F_MC_RI_4(F_MC_RI[4]),
 .F_MC_RI_3(F_MC_RI[3]),
 .F_MC_RI_2(F_MC_RI[2]),
 .F_MC_RI_1(F_MC_RI[1]),
 .F_MC_RI_0(F_MC_RI[0]),
 .F_MC_WD_73(F_MC_WD[73]),
 .F_MC_WD_72(F_MC_WD[72]),
 .F_MC_WD_71(F_MC_WD[71]),
 .F_MC_WD_70(F_MC_WD[70]),
 .F_MC_WD_69(F_MC_WD[69]),
 .F_MC_WD_68(F_MC_WD[68]),
 .F_MC_WD_67(F_MC_WD[67]),
 .F_MC_WD_66(F_MC_WD[66]),
 .F_MC_WD_65(F_MC_WD[65]),
 .F_MC_WD_64(F_MC_WD[64]),
 .F_MC_WD_63(F_MC_WD[63]),
 .F_MC_WD_62(F_MC_WD[62]),
 .F_MC_WD_61(F_MC_WD[61]),
 .F_MC_WD_60(F_MC_WD[60]),
 .F_MC_WD_59(F_MC_WD[59]),
 .F_MC_WD_58(F_MC_WD[58]),
 .F_MC_WD_57(F_MC_WD[57]),
 .F_MC_WD_56(F_MC_WD[56]),
 .F_MC_WD_55(F_MC_WD[55]),
 .F_MC_WD_54(F_MC_WD[54]),
 .F_MC_WD_53(F_MC_WD[53]),
 .F_MC_WD_52(F_MC_WD[52]),
 .F_MC_WD_51(F_MC_WD[51]),
 .F_MC_WD_50(F_MC_WD[50]),
 .F_MC_WD_49(F_MC_WD[49]),
 .F_MC_WD_48(F_MC_WD[48]),
 .F_MC_WD_47(F_MC_WD[47]),
 .F_MC_WD_46(F_MC_WD[46]),
 .F_MC_WD_45(F_MC_WD[45]),
 .F_MC_WD_44(F_MC_WD[44]),
 .F_MC_WD_43(F_MC_WD[43]),
 .F_MC_WD_42(F_MC_WD[42]),
 .F_MC_WD_41(F_MC_WD[41]),
 .F_MC_WD_40(F_MC_WD[40]),
 .F_MC_WD_39(F_MC_WD[39]),
 .F_MC_WD_38(F_MC_WD[38]),
 .F_MC_WD_37(F_MC_WD[37]),
 .F_MC_WD_36(F_MC_WD[36]),
 .F_MC_WD_35(F_MC_WD[35]),
 .F_MC_WD_34(F_MC_WD[34]),
 .F_MC_WD_33(F_MC_WD[33]),
 .F_MC_WD_32(F_MC_WD[32]),
 .F_MC_WD_31(F_MC_WD[31]),
 .F_MC_WD_30(F_MC_WD[30]),
 .F_MC_WD_29(F_MC_WD[29]),
 .F_MC_WD_28(F_MC_WD[28]),
 .F_MC_WD_27(F_MC_WD[27]),
 .F_MC_WD_26(F_MC_WD[26]),
 .F_MC_WD_25(F_MC_WD[25]),
 .F_MC_WD_24(F_MC_WD[24]),
 .F_MC_WD_23(F_MC_WD[23]),
 .F_MC_WD_22(F_MC_WD[22]),
 .F_MC_WD_21(F_MC_WD[21]),
 .F_MC_WD_20(F_MC_WD[20]),
 .F_MC_WD_19(F_MC_WD[19]),
 .F_MC_WD_18(F_MC_WD[18]),
 .F_MC_WD_17(F_MC_WD[17]),
 .F_MC_WD_16(F_MC_WD[16]),
 .F_MC_WD_15(F_MC_WD[15]),
 .F_MC_WD_14(F_MC_WD[14]),
 .F_MC_WD_13(F_MC_WD[13]),
 .F_MC_WD_12(F_MC_WD[12]),
 .F_MC_WD_11(F_MC_WD[11]),
 .F_MC_WD_10(F_MC_WD[10]),
 .F_MC_WD_9(F_MC_WD[9]),
 .F_MC_WD_8(F_MC_WD[8]),
 .F_MC_WD_7(F_MC_WD[7]),
 .F_MC_WD_6(F_MC_WD[6]),
 .F_MC_WD_5(F_MC_WD[5]),
 .F_MC_WD_4(F_MC_WD[4]),
 .F_MC_WD_3(F_MC_WD[3]),
 .F_MC_WD_2(F_MC_WD[2]),
 .F_MC_WD_1(F_MC_WD[1]),
 .F_MC_WD_0(F_MC_WD[0]),
 .F_MC_WDFIFO_WE(F_MC_WDFIFO_WE),
 .F_MC_WI_31(F_MC_WI[31]),
 .F_MC_WI_30(F_MC_WI[30]),
 .F_MC_WI_29(F_MC_WI[29]),
 .F_MC_WI_28(F_MC_WI[28]),
 .F_MC_WI_27(F_MC_WI[27]),
 .F_MC_WI_26(F_MC_WI[26]),
 .F_MC_WI_25(F_MC_WI[25]),
 .F_MC_WI_24(F_MC_WI[24]),
 .F_MC_WI_23(F_MC_WI[23]),
 .F_MC_WI_22(F_MC_WI[22]),
 .F_MC_WI_21(F_MC_WI[21]),
 .F_MC_WI_20(F_MC_WI[20]),
 .F_MC_WI_19(F_MC_WI[19]),
 .F_MC_WI_18(F_MC_WI[18]),
 .F_MC_WI_17(F_MC_WI[17]),
 .F_MC_WI_16(F_MC_WI[16]),
 .F_MC_WI_15(F_MC_WI[15]),
 .F_MC_WI_14(F_MC_WI[14]),
 .F_MC_WI_13(F_MC_WI[13]),
 .F_MC_WI_12(F_MC_WI[12]),
 .F_MC_WI_11(F_MC_WI[11]),
 .F_MC_WI_10(F_MC_WI[10]),
 .F_MC_WI_9(F_MC_WI[9]),
 .F_MC_WI_8(F_MC_WI[8]),
 .F_MC_WI_7(F_MC_WI[7]),
 .F_MC_WI_6(F_MC_WI[6]),
 .F_MC_WI_5(F_MC_WI[5]),
 .F_MC_WI_4(F_MC_WI[4]),
 .F_MC_WI_3(F_MC_WI[3]),
 .F_MC_WI_2(F_MC_WI[2]),
 .F_MC_WI_1(F_MC_WI[1]),
 .F_MC_WI_0(F_MC_WI[0]),
 .F_MC_WIFIFO_WE(F_MC_WIFIFO_WE),
 .F_MC_RIFIFO_WE(F_MC_RIFIFO_WE),
 .GSRN_DISABLE(fpsc_vhi),
 .GSRN_TOA(GSRN_TOA),
 .HADDR_17(HADDR[17]),
 .HADDR_16(HADDR[16]),
 .HADDR_15(HADDR[15]),
 .HADDR_14(HADDR[14]),
 .HADDR_13(HADDR[13]),
 .HADDR_12(HADDR[12]),
 .HADDR_11(HADDR[11]),
 .HADDR_10(HADDR[10]),
 .HADDR_9(HADDR[9]),
 .HADDR_8(HADDR[8]),
 .HADDR_7(HADDR[7]),
 .HADDR_6(HADDR[6]),
 .HADDR_5(HADDR[5]),
 .HADDR_4(HADDR[4]),
 .HADDR_3(HADDR[3]),
 .HADDR_2(HADDR[2]),
 .HADDR_1(HADDR[1]),
 .HADDR_0(HADDR[0]),
 .HBURST(HBURST),
 .HCLK(HCLK),
 .HDINN_A(HDINN_A),
 .HDINN_B(HDINN_B),
 .HDINN_C(HDINN_C),
 .HDINN_D(HDINN_D),
 .HDINP_A(HDINP_A),
 .HDINP_B(HDINP_B),
 .HDINP_C(HDINP_C),
 .HDINP_D(HDINP_D),
 .HREADY_IN(HREADY_IN),
 .HRESET_N(HRESET_N),
 .HSEL(HSEL),
 .HSIZE_1(HSIZE[1]),
 .HSIZE_0(HSIZE[0]),
 .HTRANS_1(HTRANS[1]),
 .HTRANS_0(HTRANS[0]),
 .HWDATA_7(HWDATA[7]),
 .HWDATA_6(HWDATA[6]),
 .HWDATA_5(HWDATA[5]),
 .HWDATA_4(HWDATA[4]),
 .HWDATA_3(HWDATA[3]),
 .HWDATA_2(HWDATA[2]),
 .HWDATA_1(HWDATA[1]),
 .HWDATA_0(HWDATA[0]),
 .HWRITE(HWRITE),
 .PARITY_ODD(fpsc_vhi),
 .PDN(PDN),
 .PWRUPRES(PWRUPRES),
 .REF10(REF10),
 .REF14(REF14),
 .REFCLKN(REFCLKN),
 .REFCLKP(REFCLKP),
 .RESETN(RESETN),
 .RESHI(RESHI),
 .RESLO(RESLO),
 .SI_FRFPGA(fpsc_vlo),
 .SPI_SATM_A(SPI_SATM_A),
 .SPI_DATM_A(SPI_DATM_A),
 .SPI_DLYTAP_A_2(SPI_DLYTAP_A[2]),
 .SPI_DLYTAP_A_1(SPI_DLYTAP_A[1]),
 .SPI_DLYTAP_A_0(SPI_DLYTAP_A[0]),
 .FPGA_RESET_S4A(FPGA_RESET_S4A),
 .BRLSCLK_F(BRLSCLK_F),
 .BTREFCLK_F(BTREFCLK_F),
 .SPI_SATM_B(SPI_SATM_B),
 .SPI_DATM_B(SPI_DATM_B),
 .SPI_DLYTAP_B_2(SPI_DLYTAP_B[2]),
 .SPI_DLYTAP_B_1(SPI_DLYTAP_B[1]),
 .SPI_DLYTAP_B_0(SPI_DLYTAP_B[0]),
 .FPGA_RESET_S4B(FPGA_RESET_S4B),
 .BSTOP_ON_EOP0(BSTOP_ON_EOP0),
 .BSTOP_ON_EOP1(BSTOP_ON_EOP1),
 .BSTOP_ON_EOP2(BSTOP_ON_EOP2),
 .BSTOP_ON_EOP3(BSTOP_ON_EOP3),
 .TCKI(fpsc_vlo),
 .TESTCLK(TESTCLK),
 .TESTMD0N(TESTMDN[0]),
 .TESTMD1N(TESTMDN[1]),
 .TRISTN(TRISTN),
 .TRI_IO(TRI_IO),
 .TSCLKA(TSCLKA),
 .TSTAT0A(TSTATA[0]),
 .TSTAT1A(TSTATA[1]),
 .ATSCLKN(ATSCLKN),
 .ATSCLKP(ATSCLKP),
 .ATSTAT0N(ATSTATN[0]),
 .ATSTAT0P(ATSTATP[0]),
 .ATSTAT1N(ATSTATN[1]),
 .ATSTAT1P(ATSTATP[1]),
 .TSCLKB(TSCLKB),
 .TSTAT0B(TSTATB[0]),
 .TSTAT1B(TSTATB[1]),
 .BTSCLKN(BTSCLKN),
 .BTSCLKP(BTSCLKP),
 .BTSTAT0N(BTSTATN[0]),
 .BTSTAT0P(BTSTATP[0]),
 .BTSTAT1N(BTSTATN[1]),
 .BTSTAT1P(BTSTATP[1]),
 .TS_ALL(fpsc_vlo),
 .WAIT_1(fpsc_vlo),
 .WAIT_0(fpsc_vlo),
 .ABURST_VAL_3(SPIA_TX32_BURST_VAL[3]),
 .ABURST_VAL_2(SPIA_TX32_BURST_VAL[2]),
 .ABURST_VAL_1(SPIA_TX32_BURST_VAL[1]),
 .ABURST_VAL_0(SPIA_TX32_BURST_VAL[0]),
 .ARLSCLK_F(ARLSCLK_F),
 .RSCLKA(RSCLKA),
 .RSTAT0A(RSTATA[0]),
 .RSTAT1A(RSTATA[1]),
 .ARSCLKN(ARSCLKN),
 .ARSCLKP(ARSCLKP),
 .ARSTAT0N(ARSTATN[0]),
 .ARSTAT0P(ARSTATP[0]),
 .ARSTAT1N(ARSTATN[1]),
 .ARSTAT1P(ARSTATP[1]),
 .ARX_D0_39(SPIA_RX32_CTL_0),
 .ARX_D0_38(SPIA_RX32_ERR_0),
 .ARX_D0_37(SPIA_RX32_BE_0[3]),
 .ARX_D0_36(SPIA_RX32_BE_0[2]),
 .ARX_D0_35(SPIA_RX32_BE_0[1]),
 .ARX_D0_34(SPIA_RX32_BE_0[0]),
 .ARX_D0_33(SPIA_RX32_EOP_0),
 .ARX_D0_32(SPIA_RX32_SOP_0),
 .ARX_D0_31(SPIA_RX32_DATA_0[31]),
 .ARX_D0_30(SPIA_RX32_DATA_0[30]),
 .ARX_D0_29(SPIA_RX32_DATA_0[29]),
 .ARX_D0_28(SPIA_RX32_DATA_0[28]),
 .ARX_D0_27(SPIA_RX32_DATA_0[27]),
 .ARX_D0_26(SPIA_RX32_DATA_0[26]),
 .ARX_D0_25(SPIA_RX32_DATA_0[25]),
 .ARX_D0_24(SPIA_RX32_DATA_0[24]),
 .ARX_D0_23(SPIA_RX32_DATA_0[23]),
 .ARX_D0_22(SPIA_RX32_DATA_0[22]),
 .ARX_D0_21(SPIA_RX32_DATA_0[21]),
 .ARX_D0_20(SPIA_RX32_DATA_0[20]),
 .ARX_D0_19(SPIA_RX32_DATA_0[19]),
 .ARX_D0_18(SPIA_RX32_DATA_0[18]),
 .ARX_D0_17(SPIA_RX32_DATA_0[17]),
 .ARX_D0_16(SPIA_RX32_DATA_0[16]),
 .ARX_D0_15(SPIA_RX32_DATA_0[15]),
 .ARX_D0_14(SPIA_RX32_DATA_0[14]),
 .ARX_D0_13(SPIA_RX32_DATA_0[13]),
 .ARX_D0_12(SPIA_RX32_DATA_0[12]),
 .ARX_D0_11(SPIA_RX32_DATA_0[11]),
 .ARX_D0_10(SPIA_RX32_DATA_0[10]),
 .ARX_D0_9(SPIA_RX32_DATA_0[9]),
 .ARX_D0_8(SPIA_RX32_DATA_0[8]),
 .ARX_D0_7(SPIA_RX32_DATA_0[7]),
 .ARX_D0_6(SPIA_RX32_DATA_0[6]),
 .ARX_D0_5(SPIA_RX32_DATA_0[5]),
 .ARX_D0_4(SPIA_RX32_DATA_0[4]),
 .ARX_D0_3(SPIA_RX32_DATA_0[3]),
 .ARX_D0_2(SPIA_RX32_DATA_0[2]),
 .ARX_D0_1(SPIA_RX32_DATA_0[1]),
 .ARX_D0_0(SPIA_RX32_DATA_0[0]),
 .ARX_D1_39(SPIA_RX32_CTL_1),
 .ARX_D1_38(SPIA_RX32_ERR_1),
 .ARX_D1_37(SPIA_RX32_BE_1[3]),
 .ARX_D1_36(SPIA_RX32_BE_1[2]),
 .ARX_D1_35(SPIA_RX32_BE_1[1]),
 .ARX_D1_34(SPIA_RX32_BE_1[0]),
 .ARX_D1_33(SPIA_RX32_EOP_1),
 .ARX_D1_32(SPIA_RX32_SOP_1),
 .ARX_D1_31(SPIA_RX32_DATA_1[31]),
 .ARX_D1_30(SPIA_RX32_DATA_1[30]),
 .ARX_D1_29(SPIA_RX32_DATA_1[29]),
 .ARX_D1_28(SPIA_RX32_DATA_1[28]),
 .ARX_D1_27(SPIA_RX32_DATA_1[27]),
 .ARX_D1_26(SPIA_RX32_DATA_1[26]),
 .ARX_D1_25(SPIA_RX32_DATA_1[25]),
 .ARX_D1_24(SPIA_RX32_DATA_1[24]),
 .ARX_D1_23(SPIA_RX32_DATA_1[23]),
 .ARX_D1_22(SPIA_RX32_DATA_1[22]),
 .ARX_D1_21(SPIA_RX32_DATA_1[21]),
 .ARX_D1_20(SPIA_RX32_DATA_1[20]),
 .ARX_D1_19(SPIA_RX32_DATA_1[19]),
 .ARX_D1_18(SPIA_RX32_DATA_1[18]),
 .ARX_D1_17(SPIA_RX32_DATA_1[17]),
 .ARX_D1_16(SPIA_RX32_DATA_1[16]),
 .ARX_D1_15(SPIA_RX32_DATA_1[15]),
 .ARX_D1_14(SPIA_RX32_DATA_1[14]),
 .ARX_D1_13(SPIA_RX32_DATA_1[13]),
 .ARX_D1_12(SPIA_RX32_DATA_1[12]),
 .ARX_D1_11(SPIA_RX32_DATA_1[11]),
 .ARX_D1_10(SPIA_RX32_DATA_1[10]),
 .ARX_D1_9(SPIA_RX32_DATA_1[9]),
 .ARX_D1_8(SPIA_RX32_DATA_1[8]),
 .ARX_D1_7(SPIA_RX32_DATA_1[7]),
 .ARX_D1_6(SPIA_RX32_DATA_1[6]),
 .ARX_D1_5(SPIA_RX32_DATA_1[5]),
 .ARX_D1_4(SPIA_RX32_DATA_1[4]),
 .ARX_D1_3(SPIA_RX32_DATA_1[3]),
 .ARX_D1_2(SPIA_RX32_DATA_1[2]),
 .ARX_D1_1(SPIA_RX32_DATA_1[1]),
 .ARX_D1_0(SPIA_RX32_DATA_1[0]),
 .ARX_D2_39(SPIA_RX32_CTL_2),
 .ARX_D2_38(SPIA_RX32_ERR_2),
 .ARX_D2_37(SPIA_RX32_BE_2[3]),
 .ARX_D2_36(SPIA_RX32_BE_2[2]),
 .ARX_D2_35(SPIA_RX32_BE_2[1]),
 .ARX_D2_34(SPIA_RX32_BE_2[0]),
 .ARX_D2_33(SPIA_RX32_EOP_2),
 .ARX_D2_32(SPIA_RX32_SOP_2),
 .ARX_D2_31(SPIA_RX32_DATA_2[31]),
 .ARX_D2_30(SPIA_RX32_DATA_2[30]),
 .ARX_D2_29(SPIA_RX32_DATA_2[29]),
 .ARX_D2_28(SPIA_RX32_DATA_2[28]),
 .ARX_D2_27(SPIA_RX32_DATA_2[27]),
 .ARX_D2_26(SPIA_RX32_DATA_2[26]),
 .ARX_D2_25(SPIA_RX32_DATA_2[25]),
 .ARX_D2_24(SPIA_RX32_DATA_2[24]),
 .ARX_D2_23(SPIA_RX32_DATA_2[23]),
 .ARX_D2_22(SPIA_RX32_DATA_2[22]),
 .ARX_D2_21(SPIA_RX32_DATA_2[21]),
 .ARX_D2_20(SPIA_RX32_DATA_2[20]),
 .ARX_D2_19(SPIA_RX32_DATA_2[19]),
 .ARX_D2_18(SPIA_RX32_DATA_2[18]),
 .ARX_D2_17(SPIA_RX32_DATA_2[17]),
 .ARX_D2_16(SPIA_RX32_DATA_2[16]),
 .ARX_D2_15(SPIA_RX32_DATA_2[15]),
 .ARX_D2_14(SPIA_RX32_DATA_2[14]),
 .ARX_D2_13(SPIA_RX32_DATA_2[13]),
 .ARX_D2_12(SPIA_RX32_DATA_2[12]),
 .ARX_D2_11(SPIA_RX32_DATA_2[11]),
 .ARX_D2_10(SPIA_RX32_DATA_2[10]),
 .ARX_D2_9(SPIA_RX32_DATA_2[9]),
 .ARX_D2_8(SPIA_RX32_DATA_2[8]),
 .ARX_D2_7(SPIA_RX32_DATA_2[7]),
 .ARX_D2_6(SPIA_RX32_DATA_2[6]),
 .ARX_D2_5(SPIA_RX32_DATA_2[5]),
 .ARX_D2_4(SPIA_RX32_DATA_2[4]),
 .ARX_D2_3(SPIA_RX32_DATA_2[3]),
 .ARX_D2_2(SPIA_RX32_DATA_2[2]),
 .ARX_D2_1(SPIA_RX32_DATA_2[1]),
 .ARX_D2_0(SPIA_RX32_DATA_2[0]),
 .ARX_D3_39(SPIA_RX32_CTL_3),
 .ARX_D3_38(SPIA_RX32_ERR_3),
 .ARX_D3_37(SPIA_RX32_BE_3[3]),
 .ARX_D3_36(SPIA_RX32_BE_3[2]),
 .ARX_D3_35(SPIA_RX32_BE_3[1]),
 .ARX_D3_34(SPIA_RX32_BE_3[0]),
 .ARX_D3_33(SPIA_RX32_EOP_3),
 .ARX_D3_32(SPIA_RX32_SOP_3),
 .ARX_D3_31(SPIA_RX32_DATA_3[31]),
 .ARX_D3_30(SPIA_RX32_DATA_3[30]),
 .ARX_D3_29(SPIA_RX32_DATA_3[29]),
 .ARX_D3_28(SPIA_RX32_DATA_3[28]),
 .ARX_D3_27(SPIA_RX32_DATA_3[27]),
 .ARX_D3_26(SPIA_RX32_DATA_3[26]),
 .ARX_D3_25(SPIA_RX32_DATA_3[25]),
 .ARX_D3_24(SPIA_RX32_DATA_3[24]),
 .ARX_D3_23(SPIA_RX32_DATA_3[23]),
 .ARX_D3_22(SPIA_RX32_DATA_3[22]),
 .ARX_D3_21(SPIA_RX32_DATA_3[21]),
 .ARX_D3_20(SPIA_RX32_DATA_3[20]),
 .ARX_D3_19(SPIA_RX32_DATA_3[19]),
 .ARX_D3_18(SPIA_RX32_DATA_3[18]),
 .ARX_D3_17(SPIA_RX32_DATA_3[17]),
 .ARX_D3_16(SPIA_RX32_DATA_3[16]),
 .ARX_D3_15(SPIA_RX32_DATA_3[15]),
 .ARX_D3_14(SPIA_RX32_DATA_3[14]),
 .ARX_D3_13(SPIA_RX32_DATA_3[13]),
 .ARX_D3_12(SPIA_RX32_DATA_3[12]),
 .ARX_D3_11(SPIA_RX32_DATA_3[11]),
 .ARX_D3_10(SPIA_RX32_DATA_3[10]),
 .ARX_D3_9(SPIA_RX32_DATA_3[9]),
 .ARX_D3_8(SPIA_RX32_DATA_3[8]),
 .ARX_D3_7(SPIA_RX32_DATA_3[7]),
 .ARX_D3_6(SPIA_RX32_DATA_3[6]),
 .ARX_D3_5(SPIA_RX32_DATA_3[5]),
 .ARX_D3_4(SPIA_RX32_DATA_3[4]),
 .ARX_D3_3(SPIA_RX32_DATA_3[3]),
 .ARX_D3_2(SPIA_RX32_DATA_3[2]),
 .ARX_D3_1(SPIA_RX32_DATA_3[1]),
 .ARX_D3_0(SPIA_RX32_DATA_3[0]),
 .ARX_FIFO_EMPTY0(SPIA_RX32_FIFO_EMPTY_0),
 .ARX_FIFO_EMPTY1(SPIA_RX32_FIFO_EMPTY_1),
 .ARX_FIFO_EMPTY2(SPIA_RX32_FIFO_EMPTY_2),
 .ARX_FIFO_EMPTY3(SPIA_RX32_FIFO_EMPTY_3),
 .ASB_EN_SLI(ASB_EN_SLI),
 .ASB_IRQ_SLI(ASB_IRQ_SLI),
 .ATCTLN(ATCTLN),
 .ATCTLP(ATCTLP),
 .ATDAT0N(ATDATN[0]),
 .ATDAT0P(ATDATP[0]),
 .ATDAT10N(ATDATN[10]),
 .ATDAT10P(ATDATP[10]),
 .ATDAT11N(ATDATN[11]),
 .ATDAT11P(ATDATP[11]),
 .ATDAT12N(ATDATN[12]),
 .ATDAT12P(ATDATP[12]),
 .ATDAT13N(ATDATN[13]),
 .ATDAT13P(ATDATP[13]),
 .ATDAT14N(ATDATN[14]),
 .ATDAT14P(ATDATP[14]),
 .ATDAT15N(ATDATN[15]),
 .ATDAT15P(ATDATP[15]),
 .ATDAT1N(ATDATN[1]),
 .ATDAT1P(ATDATP[1]),
 .ATDAT2N(ATDATN[2]),
 .ATDAT2P(ATDATP[2]),
 .ATDAT3N(ATDATN[3]),
 .ATDAT3P(ATDATP[3]),
 .ATDAT4N(ATDATN[4]),
 .ATDAT4P(ATDATP[4]),
 .ATDAT5N(ATDATN[5]),
 .ATDAT5P(ATDATP[5]),
 .ATDAT6N(ATDATN[6]),
 .ATDAT6P(ATDATP[6]),
 .ATDAT7N(ATDATN[7]),
 .ATDAT7P(ATDATP[7]),
 .ATDAT8N(ATDATN[8]),
 .ATDAT8P(ATDATP[8]),
 .ATDAT9N(ATDATN[9]),
 .ATDAT9P(ATDATP[9]),
 .ATDCLKN(ATDCLKN),
 .ATDCLKP(ATDCLKP),
 .ATREFCLK_F(ATREFCLK_F),
 .ATX_FIFO_FULL0(SPIA_TX32_FIFO_FULL_0),
 .ATX_FIFO_FULL1(SPIA_TX32_FIFO_FULL_1),
 .ATX_FIFO_FULL2(SPIA_TX32_FIFO_FULL_2),
 .ATX_FIFO_FULL3(SPIA_TX32_FIFO_FULL_3),
 .ATX_PORTID_7(SPIA_TX32_PORT_ID[7]),
 .ATX_PORTID_6(SPIA_TX32_PORT_ID[6]),
 .ATX_PORTID_5(SPIA_TX32_PORT_ID[5]),
 .ATX_PORTID_4(SPIA_TX32_PORT_ID[4]),
 .ATX_PORTID_3(SPIA_TX32_PORT_ID[3]),
 .ATX_PORTID_2(SPIA_TX32_PORT_ID[2]),
 .ATX_PORTID_1(SPIA_TX32_PORT_ID[1]),
 .ATX_PORTID_0(SPIA_TX32_PORT_ID[0]),
 .ATX_STAT_1(SPIA_TX32_STAT[1]),
 .ATX_STAT_0(SPIA_TX32_STAT[0]),

 .BBURST_VAL_3(SPIB_TX32_BURST_VAL[3]),
 .BBURST_VAL_2(SPIB_TX32_BURST_VAL[2]),
 .BBURST_VAL_1(SPIB_TX32_BURST_VAL[1]),
 .BBURST_VAL_0(SPIB_TX32_BURST_VAL[0]),
 .RSCLKB(RSCLKB),
 .RSTAT0B(RSTATB[0]),
 .RSTAT1B(RSTATB[1]),
 .BRSCLKN(BRSCLKN),
 .BRSCLKP(BRSCLKP),
 .BRSTAT0N(BRSTATN[0]),
 .BRSTAT0P(BRSTATP[0]),
 .BRSTAT1N(BRSTATN[1]),
 .BRSTAT1P(BRSTATP[1]),

 .BRX_FIFO_EMPTY0(SPIB_RX32_FIFO_EMPTY_0),
 .BRX_FIFO_EMPTY1(SPIB_RX32_FIFO_EMPTY_1),
 .BRX_FIFO_EMPTY2(SPIB_RX32_FIFO_EMPTY_2),
 .BRX_FIFO_EMPTY3(SPIB_RX32_FIFO_EMPTY_3),
 .BRX_D0_MRWDA_39(SPIB_RX32_CTL_0),
 .BRX_D0_MRWDA_38(SPIB_RX32_ERR_0),
 .BRX_D0_MRWDA_37(SPIB_RX32_BE_0[3]),
 .BRX_D0_MRWDA_36(SPIB_RX32_BE_0[2]),
 .BRX_D0_MRWDA_35(SPIB_RX32_BE_0[1]),
 .BRX_D0_MRWDA_34(SPIB_RX32_BE_0[0]),
 .BRX_D0_MRWDA_33(SPIB_RX32_EOP_0),
 .BRX_D0_MRWDA_32(SPIB_RX32_SOP_0),
 .BRX_D0_MRWDA_31(SPIB_RX32_DATA_0[31]),
 .BRX_D0_MRWDA_30(SPIB_RX32_DATA_0[30]),
 .BRX_D0_MRWDA_29(SPIB_RX32_DATA_0[29]),
 .BRX_D0_MRWDA_28(SPIB_RX32_DATA_0[28]),
 .BRX_D0_MRWDA_27(SPIB_RX32_DATA_0[27]),
 .BRX_D0_MRWDA_26(SPIB_RX32_DATA_0[26]),
 .BRX_D0_MRWDA_25(SPIB_RX32_DATA_0[25]),
 .BRX_D0_MRWDA_24(SPIB_RX32_DATA_0[24]),
 .BRX_D0_MRWDA_23(SPIB_RX32_DATA_0[23]),
 .BRX_D0_MRWDA_22(SPIB_RX32_DATA_0[22]),
 .BRX_D0_MRWDA_21(SPIB_RX32_DATA_0[21]),
 .BRX_D0_MRWDA_20(SPIB_RX32_DATA_0[20]),
 .BRX_D0_MRWDA_19(SPIB_RX32_DATA_0[19]),
 .BRX_D0_MRWDA_18(SPIB_RX32_DATA_0[18]),
 .BRX_D0_MRWDA_17(SPIB_RX32_DATA_0[17]),
 .BRX_D0_MRWDA_16(SPIB_RX32_DATA_0[16]),
 .BRX_D0_MRWDA_15(SPIB_RX32_DATA_0[15]),
 .BRX_D0_MRWDA_14(SPIB_RX32_DATA_0[14]),
 .BRX_D0_MRWDA_13(SPIB_RX32_DATA_0[13]),
 .BRX_D0_MRWDA_12(SPIB_RX32_DATA_0[12]),
 .BRX_D0_MRWDA_11(SPIB_RX32_DATA_0[11]),
 .BRX_D0_MRWDA_10(SPIB_RX32_DATA_0[10]),
 .BRX_D0_MRWDA_9(SPIB_RX32_DATA_0[9]),
 .BRX_D0_MRWDA_8(SPIB_RX32_DATA_0[8]),
 .BRX_D0_MRWDA_7(SPIB_RX32_DATA_0[7]),
 .BRX_D0_MRWDA_6(SPIB_RX32_DATA_0[6]),
 .BRX_D0_MRWDA_5(SPIB_RX32_DATA_0[5]),
 .BRX_D0_MRWDA_4(SPIB_RX32_DATA_0[4]),
 .BRX_D0_MRWDA_3(SPIB_RX32_DATA_0[3]),
 .BRX_D0_MRWDA_2(SPIB_RX32_DATA_0[2]),
 .BRX_D0_MRWDA_1(SPIB_RX32_DATA_0[1]),
 .BRX_D0_MRWDA_0(SPIB_RX32_DATA_0[0]),
 .BRX_D1_MRWDB_39(SPIB_RX32_CTL_1),
 .BRX_D1_MRWDB_38(SPIB_RX32_ERR_1),
 .BRX_D1_MRWDB_37(SPIB_RX32_BE_1[3]),
 .BRX_D1_MRWDB_36(SPIB_RX32_BE_1[2]),
 .BRX_D1_MRWDB_35(SPIB_RX32_BE_1[1]),
 .BRX_D1_MRWDB_34(SPIB_RX32_BE_1[0]),
 .BRX_D1_MRWDB_33(SPIB_RX32_EOP_1),
 .BRX_D1_MRWDB_32(SPIB_RX32_SOP_1),
 .BRX_D1_MRWDB_31(SPIB_RX32_DATA_1[31]),
 .BRX_D1_MRWDB_30(SPIB_RX32_DATA_1[30]),
 .BRX_D1_MRWDB_29(SPIB_RX32_DATA_1[29]),
 .BRX_D1_MRWDB_28(SPIB_RX32_DATA_1[28]),
 .BRX_D1_MRWDB_27(SPIB_RX32_DATA_1[27]),
 .BRX_D1_MRWDB_26(SPIB_RX32_DATA_1[26]),
 .BRX_D1_MRWDB_25(SPIB_RX32_DATA_1[25]),
 .BRX_D1_MRWDB_24(SPIB_RX32_DATA_1[24]),
 .BRX_D1_MRWDB_23(SPIB_RX32_DATA_1[23]),
 .BRX_D1_MRWDB_22(SPIB_RX32_DATA_1[22]),
 .BRX_D1_MRWDB_21(SPIB_RX32_DATA_1[21]),
 .BRX_D1_MRWDB_20(SPIB_RX32_DATA_1[20]),
 .BRX_D1_MRWDB_19(SPIB_RX32_DATA_1[19]),
 .BRX_D1_MRWDB_18(SPIB_RX32_DATA_1[18]),
 .BRX_D1_MRWDB_17(SPIB_RX32_DATA_1[17]),
 .BRX_D1_MRWDB_16(SPIB_RX32_DATA_1[16]),
 .BRX_D1_MRWDB_15(SPIB_RX32_DATA_1[15]),
 .BRX_D1_MRWDB_14(SPIB_RX32_DATA_1[14]),
 .BRX_D1_MRWDB_13(SPIB_RX32_DATA_1[13]),
 .BRX_D1_MRWDB_12(SPIB_RX32_DATA_1[12]),
 .BRX_D1_MRWDB_11(SPIB_RX32_DATA_1[11]),
 .BRX_D1_MRWDB_10(SPIB_RX32_DATA_1[10]),
 .BRX_D1_MRWDB_9(SPIB_RX32_DATA_1[9]),
 .BRX_D1_MRWDB_8(SPIB_RX32_DATA_1[8]),
 .BRX_D1_MRWDB_7(SPIB_RX32_DATA_1[7]),
 .BRX_D1_MRWDB_6(SPIB_RX32_DATA_1[6]),
 .BRX_D1_MRWDB_5(SPIB_RX32_DATA_1[5]),
 .BRX_D1_MRWDB_4(SPIB_RX32_DATA_1[4]),
 .BRX_D1_MRWDB_3(SPIB_RX32_DATA_1[3]),
 .BRX_D1_MRWDB_2(SPIB_RX32_DATA_1[2]),
 .BRX_D1_MRWDB_1(SPIB_RX32_DATA_1[1]),
 .BRX_D1_MRWDB_0(SPIB_RX32_DATA_1[0]),
 .BRX_D2_MRWDC_39(SPIB_RX32_CTL_2),
 .BRX_D2_MRWDC_38(SPIB_RX32_ERR_2),
 .BRX_D2_MRWDC_37(SPIB_RX32_BE_2[3]),
 .BRX_D2_MRWDC_36(SPIB_RX32_BE_2[2]),
 .BRX_D2_MRWDC_35(SPIB_RX32_BE_2[1]),
 .BRX_D2_MRWDC_34(SPIB_RX32_BE_2[0]),
 .BRX_D2_MRWDC_33(SPIB_RX32_EOP_2),
 .BRX_D2_MRWDC_32(SPIB_RX32_SOP_2),
 .BRX_D2_MRWDC_31(SPIB_RX32_DATA_2[31]),
 .BRX_D2_MRWDC_30(SPIB_RX32_DATA_2[30]),
 .BRX_D2_MRWDC_29(SPIB_RX32_DATA_2[29]),
 .BRX_D2_MRWDC_28(SPIB_RX32_DATA_2[28]),
 .BRX_D2_MRWDC_27(SPIB_RX32_DATA_2[27]),
 .BRX_D2_MRWDC_26(SPIB_RX32_DATA_2[26]),
 .BRX_D2_MRWDC_25(SPIB_RX32_DATA_2[25]),
 .BRX_D2_MRWDC_24(SPIB_RX32_DATA_2[24]),
 .BRX_D2_MRWDC_23(SPIB_RX32_DATA_2[23]),
 .BRX_D2_MRWDC_22(SPIB_RX32_DATA_2[22]),
 .BRX_D2_MRWDC_21(SPIB_RX32_DATA_2[21]),
 .BRX_D2_MRWDC_20(SPIB_RX32_DATA_2[20]),
 .BRX_D2_MRWDC_19(SPIB_RX32_DATA_2[19]),
 .BRX_D2_MRWDC_18(SPIB_RX32_DATA_2[18]),
 .BRX_D2_MRWDC_17(SPIB_RX32_DATA_2[17]),
 .BRX_D2_MRWDC_16(SPIB_RX32_DATA_2[16]),
 .BRX_D2_MRWDC_15(SPIB_RX32_DATA_2[15]),
 .BRX_D2_MRWDC_14(SPIB_RX32_DATA_2[14]),
 .BRX_D2_MRWDC_13(SPIB_RX32_DATA_2[13]),
 .BRX_D2_MRWDC_12(SPIB_RX32_DATA_2[12]),
 .BRX_D2_MRWDC_11(SPIB_RX32_DATA_2[11]),
 .BRX_D2_MRWDC_10(SPIB_RX32_DATA_2[10]),
 .BRX_D2_MRWDC_9(SPIB_RX32_DATA_2[9]),
 .BRX_D2_MRWDC_8(SPIB_RX32_DATA_2[8]),
 .BRX_D2_MRWDC_7(SPIB_RX32_DATA_2[7]),
 .BRX_D2_MRWDC_6(SPIB_RX32_DATA_2[6]),
 .BRX_D2_MRWDC_5(SPIB_RX32_DATA_2[5]),
 .BRX_D2_MRWDC_4(SPIB_RX32_DATA_2[4]),
 .BRX_D2_MRWDC_3(SPIB_RX32_DATA_2[3]),
 .BRX_D2_MRWDC_2(SPIB_RX32_DATA_2[2]),
 .BRX_D2_MRWDC_1(SPIB_RX32_DATA_2[1]),
 .BRX_D2_MRWDC_0(SPIB_RX32_DATA_2[0]),
 .BRX_D3_MRWDD_39(SPIB_RX32_CTL_3),
 .BRX_D3_MRWDD_38(SPIB_RX32_ERR_3),
 .BRX_D3_MRWDD_37(SPIB_RX32_BE_3[3]),
 .BRX_D3_MRWDD_36(SPIB_RX32_BE_3[2]),
 .BRX_D3_MRWDD_35(SPIB_RX32_BE_3[1]),
 .BRX_D3_MRWDD_34(SPIB_RX32_BE_3[0]),
 .BRX_D3_MRWDD_33(SPIB_RX32_EOP_3),
 .BRX_D3_MRWDD_32(SPIB_RX32_SOP_3),
 .BRX_D3_MRWDD_31(SPIB_RX32_DATA_3[31]),
 .BRX_D3_MRWDD_30(SPIB_RX32_DATA_3[30]),
 .BRX_D3_MRWDD_29(SPIB_RX32_DATA_3[29]),
 .BRX_D3_MRWDD_28(SPIB_RX32_DATA_3[28]),
 .BRX_D3_MRWDD_27(SPIB_RX32_DATA_3[27]),
 .BRX_D3_MRWDD_26(SPIB_RX32_DATA_3[26]),
 .BRX_D3_MRWDD_25(SPIB_RX32_DATA_3[25]),
 .BRX_D3_MRWDD_24(SPIB_RX32_DATA_3[24]),
 .BRX_D3_MRWDD_23(SPIB_RX32_DATA_3[23]),
 .BRX_D3_MRWDD_22(SPIB_RX32_DATA_3[22]),
 .BRX_D3_MRWDD_21(SPIB_RX32_DATA_3[21]),
 .BRX_D3_MRWDD_20(SPIB_RX32_DATA_3[20]),
 .BRX_D3_MRWDD_19(SPIB_RX32_DATA_3[19]),
 .BRX_D3_MRWDD_18(SPIB_RX32_DATA_3[18]),
 .BRX_D3_MRWDD_17(SPIB_RX32_DATA_3[17]),
 .BRX_D3_MRWDD_16(SPIB_RX32_DATA_3[16]),
 .BRX_D3_MRWDD_15(SPIB_RX32_DATA_3[15]),
 .BRX_D3_MRWDD_14(SPIB_RX32_DATA_3[14]),
 .BRX_D3_MRWDD_13(SPIB_RX32_DATA_3[13]),
 .BRX_D3_MRWDD_12(SPIB_RX32_DATA_3[12]),
 .BRX_D3_MRWDD_11(SPIB_RX32_DATA_3[11]),
 .BRX_D3_MRWDD_10(SPIB_RX32_DATA_3[10]),
 .BRX_D3_MRWDD_9(SPIB_RX32_DATA_3[9]),
 .BRX_D3_MRWDD_8(SPIB_RX32_DATA_3[8]),
 .BRX_D3_MRWDD_7(SPIB_RX32_DATA_3[7]),
 .BRX_D3_MRWDD_6(SPIB_RX32_DATA_3[6]),
 .BRX_D3_MRWDD_5(SPIB_RX32_DATA_3[5]),
 .BRX_D3_MRWDD_4(SPIB_RX32_DATA_3[4]),
 .BRX_D3_MRWDD_3(SPIB_RX32_DATA_3[3]),
 .BRX_D3_MRWDD_2(SPIB_RX32_DATA_3[2]),
 .BRX_D3_MRWDD_1(SPIB_RX32_DATA_3[1]),
 .BRX_D3_MRWDD_0(SPIB_RX32_DATA_3[0]),
 .FPGA_RESET_FC(fpsc_vlo),
 .CV_SELA(fpsc_vlo),
 .CV_SELB(fpsc_vlo),
 .CV_SELC(fpsc_vlo),
 .CV_SELD(fpsc_vlo),
 .RSYS_CLK_AB(fpsc_vlo),
 .RSYS_CLK_CD(fpsc_vlo),
 .TBIT9A_3(fpsc_vlo),
 .TBIT9A_2(fpsc_vlo),
 .TBIT9A_1(fpsc_vlo),
 .TBIT9A_0(fpsc_vlo),
 .TBIT9B_3(fpsc_vlo),
 .TBIT9B_2(fpsc_vlo),
 .TBIT9B_1(fpsc_vlo),
 .TBIT9B_0(fpsc_vlo),
 .TBIT9C_3(fpsc_vlo),
 .TBIT9C_2(fpsc_vlo),
 .TBIT9C_1(fpsc_vlo),
 .TBIT9C_0(fpsc_vlo),
 .TBIT9D_3(fpsc_vlo),
 .TBIT9D_2(fpsc_vlo),
 .TBIT9D_1(fpsc_vlo),
 .TBIT9D_0(fpsc_vlo),
 .TCOMMAA_3(fpsc_vlo),
 .TCOMMAA_2(fpsc_vlo),
 .TCOMMAA_1(fpsc_vlo),
 .TCOMMAA_0(fpsc_vlo),
 .TCOMMAB_3(fpsc_vlo),
 .TCOMMAB_2(fpsc_vlo),
 .TCOMMAB_1(fpsc_vlo),
 .TCOMMAB_0(fpsc_vlo),
 .TCOMMAC_3(fpsc_vlo),
 .TCOMMAC_2(fpsc_vlo),
 .TCOMMAC_1(fpsc_vlo),
 .TCOMMAC_0(fpsc_vlo),
 .TCOMMAD_3(fpsc_vlo),
 .TCOMMAD_2(fpsc_vlo),
 .TCOMMAD_1(fpsc_vlo),
 .TCOMMAD_0(fpsc_vlo),
 .TSYS_CLK_A(fpsc_vlo),
 .TSYS_CLK_B(fpsc_vlo),
 .TSYS_CLK_C(fpsc_vlo),
 .TSYS_CLK_D(fpsc_vlo),
 .TWDA_31(fpsc_vlo),
 .TWDA_30(fpsc_vlo),
 .TWDA_29(fpsc_vlo),
 .TWDA_28(fpsc_vlo),
 .TWDA_27(fpsc_vlo),
 .TWDA_26(fpsc_vlo),
 .TWDA_25(fpsc_vlo),
 .TWDA_24(fpsc_vlo),
 .TWDA_23(fpsc_vlo),
 .TWDA_22(fpsc_vlo),
 .TWDA_21(fpsc_vlo),
 .TWDA_20(fpsc_vlo),
 .TWDA_19(fpsc_vlo),
 .TWDA_18(fpsc_vlo),
 .TWDA_17(fpsc_vlo),
 .TWDA_16(fpsc_vlo),
 .TWDA_15(fpsc_vlo),
 .TWDA_14(fpsc_vlo),
 .TWDA_13(fpsc_vlo),
 .TWDA_12(fpsc_vlo),
 .TWDA_11(fpsc_vlo),
 .TWDA_10(fpsc_vlo),
 .TWDA_9(fpsc_vlo),
 .TWDA_8(fpsc_vlo),
 .TWDA_7(fpsc_vlo),
 .TWDA_6(fpsc_vlo),
 .TWDA_5(fpsc_vlo),
 .TWDA_4(fpsc_vlo),
 .TWDA_3(fpsc_vlo),
 .TWDA_2(fpsc_vlo),
 .TWDA_1(fpsc_vlo),
 .TWDA_0(fpsc_vlo),
 .TWDB_31(fpsc_vlo),
 .TWDB_30(fpsc_vlo),
 .TWDB_29(fpsc_vlo),
 .TWDB_28(fpsc_vlo),
 .TWDB_27(fpsc_vlo),
 .TWDB_26(fpsc_vlo),
 .TWDB_25(fpsc_vlo),
 .TWDB_24(fpsc_vlo),
 .TWDB_23(fpsc_vlo),
 .TWDB_22(fpsc_vlo),
 .TWDB_21(fpsc_vlo),
 .TWDB_20(fpsc_vlo),
 .TWDB_19(fpsc_vlo),
 .TWDB_18(fpsc_vlo),
 .TWDB_17(fpsc_vlo),
 .TWDB_16(fpsc_vlo),
 .TWDB_15(fpsc_vlo),
 .TWDB_14(fpsc_vlo),
 .TWDB_13(fpsc_vlo),
 .TWDB_12(fpsc_vlo),
 .TWDB_11(fpsc_vlo),
 .TWDB_10(fpsc_vlo),
 .TWDB_9(fpsc_vlo),
 .TWDB_8(fpsc_vlo),
 .TWDB_7(fpsc_vlo),
 .TWDB_6(fpsc_vlo),
 .TWDB_5(fpsc_vlo),
 .TWDB_4(fpsc_vlo),
 .TWDB_3(fpsc_vlo),
 .TWDB_2(fpsc_vlo),
 .TWDB_1(fpsc_vlo),
 .TWDB_0(fpsc_vlo),
 .TWDC_31(fpsc_vlo),
 .TWDC_30(fpsc_vlo),
 .TWDC_29(fpsc_vlo),
 .TWDC_28(fpsc_vlo),
 .TWDC_27(fpsc_vlo),
 .TWDC_26(fpsc_vlo),
 .TWDC_25(fpsc_vlo),
 .TWDC_24(fpsc_vlo),
 .TWDC_23(fpsc_vlo),
 .TWDC_22(fpsc_vlo),
 .TWDC_21(fpsc_vlo),
 .TWDC_20(fpsc_vlo),
 .TWDC_19(fpsc_vlo),
 .TWDC_18(fpsc_vlo),
 .TWDC_17(fpsc_vlo),
 .TWDC_16(fpsc_vlo),
 .TWDC_15(fpsc_vlo),
 .TWDC_14(fpsc_vlo),
 .TWDC_13(fpsc_vlo),
 .TWDC_12(fpsc_vlo),
 .TWDC_11(fpsc_vlo),
 .TWDC_10(fpsc_vlo),
 .TWDC_9(fpsc_vlo),
 .TWDC_8(fpsc_vlo),
 .TWDC_7(fpsc_vlo),
 .TWDC_6(fpsc_vlo),
 .TWDC_5(fpsc_vlo),
 .TWDC_4(fpsc_vlo),
 .TWDC_3(fpsc_vlo),
 .TWDC_2(fpsc_vlo),
 .TWDC_1(fpsc_vlo),
 .TWDC_0(fpsc_vlo),
 .TWDD_31(fpsc_vlo),
 .TWDD_30(fpsc_vlo),
 .TWDD_29(fpsc_vlo),
 .TWDD_28(fpsc_vlo),
 .TWDD_27(fpsc_vlo),
 .TWDD_26(fpsc_vlo),
 .TWDD_25(fpsc_vlo),
 .TWDD_24(fpsc_vlo),
 .TWDD_23(fpsc_vlo),
 .TWDD_22(fpsc_vlo),
 .TWDD_21(fpsc_vlo),
 .TWDD_20(fpsc_vlo),
 .TWDD_19(fpsc_vlo),
 .TWDD_18(fpsc_vlo),
 .TWDD_17(fpsc_vlo),
 .TWDD_16(fpsc_vlo),
 .TWDD_15(fpsc_vlo),
 .TWDD_14(fpsc_vlo),
 .TWDD_13(fpsc_vlo),
 .TWDD_12(fpsc_vlo),
 .TWDD_11(fpsc_vlo),
 .TWDD_10(fpsc_vlo),
 .TWDD_9(fpsc_vlo),
 .TWDD_8(fpsc_vlo),
 .TWDD_7(fpsc_vlo),
 .TWDD_6(fpsc_vlo),
 .TWDD_5(fpsc_vlo),
 .TWDD_4(fpsc_vlo),
 .TWDD_3(fpsc_vlo),
 .TWDD_2(fpsc_vlo),
 .TWDD_1(fpsc_vlo),
 .TWDD_0(fpsc_vlo),
 .SERDES_LS_LOOP_MODE(fpsc_vlo),
 .RCK78(),
 .RWCKA(),
 .RWCKB(),
 .RWCKC(),
 .RWCKD(),
 .TCK78(),
 .BS_CPTBSR_OUT(),
 .BS_MD_OUT(),
 .BS_SHBSRN_OUT(),
 .BS_TRESET_OUT(),
 .BS_UPDTBSR_OUT(),
 .BTCTLN(BTCTLN),
 .BTCTLP(BTCTLP),
 .BTDAT0N(BTDATN[0]),
 .BTDAT0P(BTDATP[0]),
 .BTDAT10N(BTDATN[10]),
 .BTDAT10P(BTDATP[10]),
 .BTDAT11N(BTDATN[11]),
 .BTDAT11P(BTDATP[11]),
 .BTDAT12N(BTDATN[12]),
 .BTDAT12P(BTDATP[12]),
 .BTDAT13N(BTDATN[13]),
 .BTDAT13P(BTDATP[13]),
 .BTDAT14N(BTDATN[14]),
 .BTDAT14P(BTDATP[14]),
 .BTDAT15N(BTDATN[15]),
 .BTDAT15P(BTDATP[15]),
 .BTDAT1N(BTDATN[1]),
 .BTDAT1P(BTDATP[1]),
 .BTDAT2N(BTDATN[2]),
 .BTDAT2P(BTDATP[2]),
 .BTDAT3N(BTDATN[3]),
 .BTDAT3P(BTDATP[3]),
 .BTDAT4N(BTDATN[4]),
 .BTDAT4P(BTDATP[4]),
 .BTDAT5N(BTDATN[5]),
 .BTDAT5P(BTDATP[5]),
 .BTDAT6N(BTDATN[6]),
 .BTDAT6P(BTDATP[6]),
 .BTDAT7N(BTDATN[7]),
 .BTDAT7P(BTDATP[7]),
 .BTDAT8N(BTDATN[8]),
 .BTDAT8P(BTDATP[8]),
 .BTDAT9N(BTDATN[9]),
 .BTDAT9P(BTDATP[9]),
 .BTDCLKN(BTDCLKN),
 .BTDCLKP(BTDCLKP),
 .BTX_FIFO_FULL0(SPIB_TX32_FIFO_FULL_0),
 .BTX_FIFO_FULL1(SPIB_TX32_FIFO_FULL_1),
 .BTX_FIFO_FULL2(SPIB_TX32_FIFO_FULL_2),
 .BTX_FIFO_FULL3(SPIB_TX32_FIFO_FULL_3),
 .BTX_PORTID_7(SPIB_TX32_PORT_ID[7]),
 .BTX_PORTID_6(SPIB_TX32_PORT_ID[6]),
 .BTX_PORTID_5(SPIB_TX32_PORT_ID[5]),
 .BTX_PORTID_4(SPIB_TX32_PORT_ID[4]),
 .BTX_PORTID_3(SPIB_TX32_PORT_ID[3]),
 .BTX_PORTID_2(SPIB_TX32_PORT_ID[2]),
 .BTX_PORTID_1(SPIB_TX32_PORT_ID[1]),
 .BTX_PORTID_0(SPIB_TX32_PORT_ID[0]),
 .BTX_STAT_1(SPIB_TX32_STAT[1]),
 .BTX_STAT_0(SPIB_TX32_STAT[0]),
 .HDOUTN_A(HDOUTN_A),
 .HDOUTN_B(HDOUTN_B),
 .HDOUTN_C(HDOUTN_C),
 .HDOUTN_D(HDOUTN_D),
 .HDOUTP_A(HDOUTP_A),
 .HDOUTP_B(HDOUTP_B),
 .HDOUTP_C(HDOUTP_C),
 .HDOUTP_D(HDOUTP_D),
 .HRDATA_35(HRDATA[35]), 
 .HRDATA_34(HRDATA[34]), 
 .HRDATA_33(HRDATA[33]), 
 .HRDATA_32(HRDATA[32]), 
 .HRDATA_31(HRDATA[31]), 
 .HRDATA_30(HRDATA[30]), 
 .HRDATA_29(HRDATA[29]), 
 .HRDATA_28(HRDATA[28]),
 .HRDATA_27(HRDATA[27]), 
 .HRDATA_26(HRDATA[26]), 
 .HRDATA_25(HRDATA[25]), 
 .HRDATA_24(HRDATA[24]), 
 .HRDATA_23(HRDATA[23]), 
 .HRDATA_22(HRDATA[22]), 
 .HRDATA_21(HRDATA[21]), 
 .HRDATA_20(HRDATA[20]), 
 .HRDATA_19(HRDATA[19]),
 .HRDATA_18(HRDATA[18]), 
 .HRDATA_17(HRDATA[17]), 
 .HRDATA_16(HRDATA[16]), 
 .HRDATA_15(HRDATA[15]), 
 .HRDATA_14(HRDATA[14]), 
 .HRDATA_13(HRDATA[13]), 
 .HRDATA_12(HRDATA[12]), 
 .HRDATA_11(HRDATA[11]), 
 .HRDATA_10(HRDATA[10]),
 .HRDATA_9(HRDATA[9]), 
 .HRDATA_8(HRDATA[8]), 
 .HRDATA_7(HRDATA[7]), 
 .HRDATA_6(HRDATA[6]), 
 .HRDATA_5(HRDATA[5]), 
 .HRDATA_4(HRDATA[4]), 
 .HRDATA_3(HRDATA[3]), 
 .HRDATA_2(HRDATA[2]), 
 .HRDATA_1(HRDATA[1]), 
 .HRDATA_0(HRDATA[0]),
 .HREADY_OUT(HREADY_OUT),
 .HRESP_1(HRESP[1]), 
 .HRESP_0(HRESP[0]),
 .MC_RD_71(MC_RD[71]),
 .MC_RD_70(MC_RD[70]),
 .MC_RD_69(MC_RD[69]),
 .MC_RD_68(MC_RD[68]),
 .MC_RD_67(MC_RD[67]),
 .MC_RD_66(MC_RD[66]),
 .MC_RD_65(MC_RD[65]),
 .MC_RD_64(MC_RD[64]),
 .MC_RD_63(MC_RD[63]),
 .MC_RD_62(MC_RD[62]),
 .MC_RD_61(MC_RD[61]),
 .MC_RD_60(MC_RD[60]),
 .MC_RD_59(MC_RD[59]),
 .MC_RD_58(MC_RD[58]),
 .MC_RD_57(MC_RD[57]),
 .MC_RD_56(MC_RD[56]),
 .MC_RD_55(MC_RD[55]),
 .MC_RD_54(MC_RD[54]),
 .MC_RD_53(MC_RD[53]),
 .MC_RD_52(MC_RD[52]),
 .MC_RD_51(MC_RD[51]),
 .MC_RD_50(MC_RD[50]),
 .MC_RD_49(MC_RD[49]),
 .MC_RD_48(MC_RD[48]),
 .MC_RD_47(MC_RD[47]),
 .MC_RD_46(MC_RD[46]),
 .MC_RD_45(MC_RD[45]),
 .MC_RD_44(MC_RD[44]),
 .MC_RD_43(MC_RD[43]),
 .MC_RD_42(MC_RD[42]),
 .MC_RD_41(MC_RD[41]),
 .MC_RD_40(MC_RD[40]),
 .MC_RD_39(MC_RD[39]),
 .MC_RD_38(MC_RD[38]),
 .MC_RD_37(MC_RD[37]),
 .MC_RD_36(MC_RD[36]),
 .MC_RD_35(MC_RD[35]),
 .MC_RD_34(MC_RD[34]),
 .MC_RD_33(MC_RD[33]),
 .MC_RD_32(MC_RD[32]),
 .MC_RD_31(MC_RD[31]),
 .MC_RD_30(MC_RD[30]),
 .MC_RD_29(MC_RD[29]),
 .MC_RD_28(MC_RD[28]),
 .MC_RD_27(MC_RD[27]),
 .MC_RD_26(MC_RD[26]),
 .MC_RD_25(MC_RD[25]),
 .MC_RD_24(MC_RD[24]),
 .MC_RD_23(MC_RD[23]),
 .MC_RD_22(MC_RD[22]),
 .MC_RD_21(MC_RD[21]),
 .MC_RD_20(MC_RD[20]),
 .MC_RD_19(MC_RD[19]),
 .MC_RD_18(MC_RD[18]),
 .MC_RD_17(MC_RD[17]),
 .MC_RD_16(MC_RD[16]),
 .MC_RD_15(MC_RD[15]),
 .MC_RD_14(MC_RD[14]),
 .MC_RD_13(MC_RD[13]),
 .MC_RD_12(MC_RD[12]),
 .MC_RD_11(MC_RD[11]),
 .MC_RD_10(MC_RD[10]),
 .MC_RD_9(MC_RD[9]),
 .MC_RD_8(MC_RD[8]),
 .MC_RD_7(MC_RD[7]),
 .MC_RD_6(MC_RD[6]),
 .MC_RD_5(MC_RD[5]),
 .MC_RD_4(MC_RD[4]),
 .MC_RD_3(MC_RD[3]),
 .MC_RD_2(MC_RD[2]),
 .MC_RD_1(MC_RD[1]),
 .MC_RD_0(MC_RD[0]),
 .MC_RDFIFO_EMPTY(MC_RDFIFO_EMPTY),
 .MC_RIFIFO_FULL(MC_RIFIFO_FULL),
 .MC_SYSCLK(MC_SYSCLK),
 .MC_WDFIFO_FULL(MC_WDFIFO_FULL),
 .MC_WIFIFO_FULL(MC_WIFIFO_FULL),
 .REXT(REXT),
 .REXTN(REXTN),
 .SO_TOFPGA(),
 .TCKI_OUT(),
 .TIE_HI(),
 .TIE_LO(),
 .MCREFCLK(MCREFCLK),
 .PMIA0(PMIA[0]),
 .PMIA1(PMIA[1]),
 .PMIA10(PMIA[10]),
 .PMIA11(PMIA[11]),
 .PMIA12(PMIA[12]),
 .PMIA13(PMIA[13]),
 .PMIA14(PMIA[14]),
 .PMIA15(PMIA[15]),
 .PMIA16(PMIA[16]),
 .PMIA17(PMIA[17]),
 .PMIA2(PMIA[2]),
 .PMIA3(PMIA[3]),
 .PMIA4(PMIA[4]),
 .PMIA5(PMIA[5]),
 .PMIA6(PMIA[6]),
 .PMIA7(PMIA[7]),
 .PMIA8(PMIA[8]),
 .PMIA9(PMIA[9]),
 .PMIC(PMIC),
 .PMICN(PMICN),
 .PMID0(PMID[0]),
 .PMID1(PMID[1]),
 .PMID10(PMID[10]),
 .PMID11(PMID[11]),
 .PMID12(PMID[12]),
 .PMID13(PMID[13]),
 .PMID14(PMID[14]),
 .PMID15(PMID[15]),
 .PMID16(PMID[16]),
 .PMID17(PMID[17]),
 .PMID18(PMID[18]),
 .PMID19(PMID[19]),
 .PMID2(PMID[2]),
 .PMID20(PMID[20]),
 .PMID21(PMID[21]),
 .PMID22(PMID[22]),
 .PMID23(PMID[23]),
 .PMID24(PMID[24]),
 .PMID25(PMID[25]),
 .PMID26(PMID[26]),
 .PMID27(PMID[27]),
 .PMID28(PMID[28]),
 .PMID29(PMID[29]),
 .PMID3(PMID[3]),
 .PMID30(PMID[30]),
 .PMID31(PMID[31]),
 .PMID32(PMID[32]),
 .PMID33(PMID[33]),
 .PMID34(PMID[34]),
 .PMID35(PMID[35]),
 .PMID4(PMID[4]),
 .PMID5(PMID[5]),
 .PMID6(PMID[6]),
 .PMID7(PMID[7]),
 .PMID8(PMID[8]),
 .PMID9(PMID[9]),
 .PMIK(PMIK),
 .PMIKN(PMIKN),
 .PMIQ0(PMIQ[0]),
 .PMIQ1(PMIQ[1]),
 .PMIQ10(PMIQ[10]),
 .PMIQ11(PMIQ[11]),
 .PMIQ12(PMIQ[12]),
 .PMIQ13(PMIQ[13]),
 .PMIQ14(PMIQ[14]),
 .PMIQ15(PMIQ[15]),
 .PMIQ16(PMIQ[16]),
 .PMIQ17(PMIQ[17]),
 .PMIQ18(PMIQ[18]),
 .PMIQ19(PMIQ[19]),
 .PMIQ2(PMIQ[2]),
 .PMIQ20(PMIQ[20]),
 .PMIQ21(PMIQ[21]),
 .PMIQ22(PMIQ[22]),
 .PMIQ23(PMIQ[23]),
 .PMIQ24(PMIQ[24]),
 .PMIQ25(PMIQ[25]),
 .PMIQ26(PMIQ[26]),
 .PMIQ27(PMIQ[27]),
 .PMIQ28(PMIQ[28]),
 .PMIQ29(PMIQ[29]),
 .PMIQ3(PMIQ[3]),
 .PMIQ30(PMIQ[30]),
 .PMIQ31(PMIQ[31]),
 .PMIQ32(PMIQ[32]),
 .PMIQ33(PMIQ[33]),
 .PMIQ34(PMIQ[34]),
 .PMIQ35(PMIQ[35]),
 .PMIQ4(PMIQ[4]),
 .PMIQ5(PMIQ[5]),
 .PMIQ6(PMIQ[6]),
 .PMIQ7(PMIQ[7]),
 .PMIQ8(PMIQ[8]),
 .PMIQ9(PMIQ[9]),
 .PMIRN(PMIRN),
 .PMIWN(PMIWN),
 .SYS_RST_N(SYS_RST_N)
);
// exemplar attribute orspi_core_inst IS_ASB $FPSC/orspii/data/orspi.acd          
// exemplar attribute orspi_core_inst CORE_ID FULLSPI       
 
endmodule 

//Inputs
// Not for Simulation Module


module orspi_core (ALVCTAP1, ALVCTAP2, ALVCTAP3, ALVCTAP4, ALVCTAP5,
  ARCTLN, ARCTLP, ARDAT0N, ARDAT0P, ARDAT10N, ARDAT10P, ARDAT11N,
  ARDAT11P, ARDAT12N, ARDAT12P, ARDAT13N, ARDAT13P, ARDAT14N, ARDAT14P,
  ARDAT15N, ARDAT15P, ARDAT1N, ARDAT1P, ARDAT2N, ARDAT2P, ARDAT3N,
  ARDAT3P, ARDAT4N, ARDAT4P, ARDAT5N, ARDAT5P, ARDAT6N, ARDAT6P, ARDAT7N,
  ARDAT7P, ARDAT8N, ARDAT8P, ARDAT9N, ARDAT9P, ARDCLKN, ARDCLKP, ARX_A0_2,
  ARX_A0_1, ARX_A0_0, ARX_A1_2, ARX_A1_1, ARX_A1_0, ARX_A2_2, ARX_A2_1,
  ARX_A2_0, ARX_A3_2, ARX_A3_1, ARX_A3_0, ARX_CLK0, ARX_CLK1, ARX_CLK2,
  ARX_CLK3, ARX_EXT_STATUS_ENABLE, ARX_FPGA_PORT_ID_7, ARX_FPGA_PORT_ID_6,
  ARX_FPGA_PORT_ID_5, ARX_FPGA_PORT_ID_4, ARX_FPGA_PORT_ID_3,
  ARX_FPGA_PORT_ID_2, ARX_FPGA_PORT_ID_1, ARX_FPGA_PORT_ID_0,
  ARX_PORT_STATUS_1, ARX_PORT_STATUS_0, ARX_PSS_CLK, ARX_PSS_WE, ARX_RE0,
  ARX_RE1, ARX_RE2, ARX_RE3, ASTOP_ON_EOP0, ASTOP_ON_EOP1, ASTOP_ON_EOP2,
  ASTOP_ON_EOP3, ATREFCLK, ATSCLKN, ATSCLKP, ATSTAT0N, ATSTAT0P, ATSTAT1N,
  ATSTAT1P, ATX_A0_2, ATX_A0_1, ATX_A0_0, ATX_A1_2, ATX_A1_1, ATX_A1_0,
  ATX_A2_2, ATX_A2_1, ATX_A2_0, ATX_A3_2, ATX_A3_1, ATX_A3_0, ATX_CLK0,
  ATX_CLK1, ATX_CLK2, ATX_CLK3, ATX_D0_39, ATX_D0_38, ATX_D0_37,
  ATX_D0_36, ATX_D0_35, ATX_D0_34, ATX_D0_33, ATX_D0_32, ATX_D0_31,
  ATX_D0_30, ATX_D0_29, ATX_D0_28, ATX_D0_27, ATX_D0_26, ATX_D0_25,
  ATX_D0_24, ATX_D0_23, ATX_D0_22, ATX_D0_21, ATX_D0_20, ATX_D0_19,
  ATX_D0_18, ATX_D0_17, ATX_D0_16, ATX_D0_15, ATX_D0_14, ATX_D0_13,
  ATX_D0_12, ATX_D0_11, ATX_D0_10, ATX_D0_9, ATX_D0_8, ATX_D0_7, ATX_D0_6,
  ATX_D0_5, ATX_D0_4, ATX_D0_3, ATX_D0_2, ATX_D0_1, ATX_D0_0, ATX_D1_39,
  ATX_D1_38, ATX_D1_37, ATX_D1_36, ATX_D1_35, ATX_D1_34, ATX_D1_33,
  ATX_D1_32, ATX_D1_31, ATX_D1_30, ATX_D1_29, ATX_D1_28, ATX_D1_27,
  ATX_D1_26, ATX_D1_25, ATX_D1_24, ATX_D1_23, ATX_D1_22, ATX_D1_21,
  ATX_D1_20, ATX_D1_19, ATX_D1_18, ATX_D1_17, ATX_D1_16, ATX_D1_15,
  ATX_D1_14, ATX_D1_13, ATX_D1_12, ATX_D1_11, ATX_D1_10, ATX_D1_9,
  ATX_D1_8, ATX_D1_7, ATX_D1_6, ATX_D1_5, ATX_D1_4, ATX_D1_3, ATX_D1_2,
  ATX_D1_1, ATX_D1_0, ATX_D2_39, ATX_D2_38, ATX_D2_37, ATX_D2_36,
  ATX_D2_35, ATX_D2_34, ATX_D2_33, ATX_D2_32, ATX_D2_31, ATX_D2_30,
  ATX_D2_29, ATX_D2_28, ATX_D2_27, ATX_D2_26, ATX_D2_25, ATX_D2_24,
  ATX_D2_23, ATX_D2_22, ATX_D2_21, ATX_D2_20, ATX_D2_19, ATX_D2_18,
  ATX_D2_17, ATX_D2_16, ATX_D2_15, ATX_D2_14, ATX_D2_13, ATX_D2_12,
  ATX_D2_11, ATX_D2_10, ATX_D2_9, ATX_D2_8, ATX_D2_7, ATX_D2_6, ATX_D2_5,
  ATX_D2_4, ATX_D2_3, ATX_D2_2, ATX_D2_1, ATX_D2_0, ATX_D3_39, ATX_D3_38,
  ATX_D3_37, ATX_D3_36, ATX_D3_35, ATX_D3_34, ATX_D3_33, ATX_D3_32,
  ATX_D3_31, ATX_D3_30, ATX_D3_29, ATX_D3_28, ATX_D3_27, ATX_D3_26,
  ATX_D3_25, ATX_D3_24, ATX_D3_23, ATX_D3_22, ATX_D3_21, ATX_D3_20,
  ATX_D3_19, ATX_D3_18, ATX_D3_17, ATX_D3_16, ATX_D3_15, ATX_D3_14,
  ATX_D3_13, ATX_D3_12, ATX_D3_11, ATX_D3_10, ATX_D3_9, ATX_D3_8,
  ATX_D3_7, ATX_D3_6, ATX_D3_5, ATX_D3_4, ATX_D3_3, ATX_D3_2, ATX_D3_1,
  ATX_D3_0, ATX_LINK_DIS0, ATX_LINK_DIS1, ATX_LINK_DIS2, ATX_LINK_DIS3,
  ATX_PORT0_7, ATX_PORT0_6, ATX_PORT0_5, ATX_PORT0_4, ATX_PORT0_3,
  ATX_PORT0_2, ATX_PORT0_1, ATX_PORT0_0, ATX_PORT1_7, ATX_PORT1_6,
  ATX_PORT1_5, ATX_PORT1_4, ATX_PORT1_3, ATX_PORT1_2, ATX_PORT1_1,
  ATX_PORT1_0, ATX_PORT2_7, ATX_PORT2_6, ATX_PORT2_5, ATX_PORT2_4,
  ATX_PORT2_3, ATX_PORT2_2, ATX_PORT2_1, ATX_PORT2_0, ATX_PORT3_7,
  ATX_PORT3_6, ATX_PORT3_5, ATX_PORT3_4, ATX_PORT3_3, ATX_PORT3_2,
  ATX_PORT3_1, ATX_PORT3_0, ATX_WE0, ATX_WE1, ATX_WE2, ATX_WE3,
  AWD_CNT_RST0, AWD_CNT_RST1, AWD_CNT_RST2, AWD_CNT_RST3, BLVCTAP1,
  BLVCTAP2, BLVCTAP3, BLVCTAP4, BLVCTAP5, BRCTLN, BRCTLP, BRDAT0N,
  BRDAT0P, BRDAT10N, BRDAT10P, BRDAT11N, BRDAT11P, BRDAT12N, BRDAT12P,
  BRDAT13N, BRDAT13P, BRDAT14N, BRDAT14P, BRDAT15N, BRDAT15P, BRDAT1N,
  BRDAT1P, BRDAT2N, BRDAT2P, BRDAT3N, BRDAT3P, BRDAT4N, BRDAT4P, BRDAT5N,
  BRDAT5P, BRDAT6N, BRDAT6P, BRDAT7N, BRDAT7P, BRDAT8N, BRDAT8P, BRDAT9N,
  BRDAT9P, BRDCLKN, BRDCLKP, BRX_A0_2, BRX_A0_1, BRX_A0_0, BRX_A1_2,
  BRX_A1_1, BRX_A1_0, BRX_A2_2, BRX_A2_1, BRX_A2_0, BRX_A3_2, BRX_A3_1,
  BRX_A3_0, BRX_CLK0, BRX_CLK1, BRX_CLK2, BRX_CLK3, BRX_EXT_STATUS_ENABLE,
  BRX_FPGA_PORT_ID_7, BRX_FPGA_PORT_ID_6, BRX_FPGA_PORT_ID_5,
  BRX_FPGA_PORT_ID_4, BRX_FPGA_PORT_ID_3, BRX_FPGA_PORT_ID_2,
  BRX_FPGA_PORT_ID_1, BRX_FPGA_PORT_ID_0, BRX_PORT_STATUS_1,
  BRX_PORT_STATUS_0, BRX_PSS_CLK, BRX_PSS_WE, BRX_RE0, BRX_RE1, BRX_RE2,
  BRX_RE3, BSTOP_ON_EOP0, BSTOP_ON_EOP1, BSTOP_ON_EOP2, BSTOP_ON_EOP3,
  BS_CPTBSR, BS_MD, BS_SHBSRN, BS_TRESET, BS_UPDTBSR, BTREFCLK, BTSCLKN,
  BTSCLKP, BTSTAT0N, BTSTAT0P, BTSTAT1N, BTSTAT1P, BTX_A0_2, BTX_A0_1,
  BTX_A0_0, BTX_A1_2, BTX_A1_1, BTX_A1_0, BTX_A2_2, BTX_A2_1, BTX_A2_0,
  BTX_A3_2, BTX_A3_1, BTX_A3_0, BTX_CLK0, BTX_CLK1, BTX_CLK2, BTX_CLK3,
  BTX_D0_39, BTX_D0_38, BTX_D0_37, BTX_D0_36, BTX_D0_35, BTX_D0_34,
  BTX_D0_33, BTX_D0_32, BTX_D0_31, BTX_D0_30, BTX_D0_29, BTX_D0_28,
  BTX_D0_27, BTX_D0_26, BTX_D0_25, BTX_D0_24, BTX_D0_23, BTX_D0_22,
  BTX_D0_21, BTX_D0_20, BTX_D0_19, BTX_D0_18, BTX_D0_17, BTX_D0_16,
  BTX_D0_15, BTX_D0_14, BTX_D0_13, BTX_D0_12, BTX_D0_11, BTX_D0_10,
  BTX_D0_9, BTX_D0_8, BTX_D0_7, BTX_D0_6, BTX_D0_5, BTX_D0_4, BTX_D0_3,
  BTX_D0_2, BTX_D0_1, BTX_D0_0, BTX_D1_39, BTX_D1_38, BTX_D1_37,
  BTX_D1_36, BTX_D1_35, BTX_D1_34, BTX_D1_33, BTX_D1_32, BTX_D1_31,
  BTX_D1_30, BTX_D1_29, BTX_D1_28, BTX_D1_27, BTX_D1_26, BTX_D1_25,
  BTX_D1_24, BTX_D1_23, BTX_D1_22, BTX_D1_21, BTX_D1_20, BTX_D1_19,
  BTX_D1_18, BTX_D1_17, BTX_D1_16, BTX_D1_15, BTX_D1_14, BTX_D1_13,
  BTX_D1_12, BTX_D1_11, BTX_D1_10, BTX_D1_9, BTX_D1_8, BTX_D1_7, BTX_D1_6,
  BTX_D1_5, BTX_D1_4, BTX_D1_3, BTX_D1_2, BTX_D1_1, BTX_D1_0, BTX_D2_39,
  BTX_D2_38, BTX_D2_37, BTX_D2_36, BTX_D2_35, BTX_D2_34, BTX_D2_33,
  BTX_D2_32, BTX_D2_31, BTX_D2_30, BTX_D2_29, BTX_D2_28, BTX_D2_27,
  BTX_D2_26, BTX_D2_25, BTX_D2_24, BTX_D2_23, BTX_D2_22, BTX_D2_21,
  BTX_D2_20, BTX_D2_19, BTX_D2_18, BTX_D2_17, BTX_D2_16, BTX_D2_15,
  BTX_D2_14, BTX_D2_13, BTX_D2_12, BTX_D2_11, BTX_D2_10, BTX_D2_9,
  BTX_D2_8, BTX_D2_7, BTX_D2_6, BTX_D2_5, BTX_D2_4, BTX_D2_3, BTX_D2_2,
  BTX_D2_1, BTX_D2_0, BTX_D3_39, BTX_D3_38, BTX_D3_37, BTX_D3_36,
  BTX_D3_35, BTX_D3_34, BTX_D3_33, BTX_D3_32, BTX_D3_31, BTX_D3_30,
  BTX_D3_29, BTX_D3_28, BTX_D3_27, BTX_D3_26, BTX_D3_25, BTX_D3_24,
  BTX_D3_23, BTX_D3_22, BTX_D3_21, BTX_D3_20, BTX_D3_19, BTX_D3_18,
  BTX_D3_17, BTX_D3_16, BTX_D3_15, BTX_D3_14, BTX_D3_13, BTX_D3_12,
  BTX_D3_11, BTX_D3_10, BTX_D3_9, BTX_D3_8, BTX_D3_7, BTX_D3_6, BTX_D3_5,
  BTX_D3_4, BTX_D3_3, BTX_D3_2, BTX_D3_1, BTX_D3_0, BTX_LINK_DIS0,
  BTX_LINK_DIS1, BTX_LINK_DIS2, BTX_LINK_DIS3, BTX_PORT0_7, BTX_PORT0_6,
  BTX_PORT0_5, BTX_PORT0_4, BTX_PORT0_3, BTX_PORT0_2, BTX_PORT0_1,
  BTX_PORT0_0, BTX_PORT1_7, BTX_PORT1_6, BTX_PORT1_5, BTX_PORT1_4,
  BTX_PORT1_3, BTX_PORT1_2, BTX_PORT1_1, BTX_PORT1_0, BTX_PORT2_7,
  BTX_PORT2_6, BTX_PORT2_5, BTX_PORT2_4, BTX_PORT2_3, BTX_PORT2_2,
  BTX_PORT2_1, BTX_PORT2_0, BTX_PORT3_7, BTX_PORT3_6, BTX_PORT3_5,
  BTX_PORT3_4, BTX_PORT3_3, BTX_PORT3_2, BTX_PORT3_1, BTX_PORT3_0,
  BTX_WE0, BTX_WE1, BTX_WE2, BTX_WE3, BWD_CNT_RST0, BWD_CNT_RST1,
  BWD_CNT_RST2, BWD_CNT_RST3, CV_SELA, CV_SELB, CV_SELC, CV_SELD,
  DIVIDE_1, DIVIDE_0, DONE, ENABLE_SPI4_B, EXT_1K, FPGA_RESET_FC,
  FPGA_RESET_MC, FPGA_RESET_S4A, FPGA_RESET_S4B, F_MC_RCLK,
  F_MC_RDFIFO_RE, F_MC_REFCLK, F_MC_RI_31, F_MC_RI_30, F_MC_RI_29,
  F_MC_RI_28, F_MC_RI_27, F_MC_RI_26, F_MC_RI_25, F_MC_RI_24, F_MC_RI_23,
  F_MC_RI_22, F_MC_RI_21, F_MC_RI_20, F_MC_RI_19, F_MC_RI_18, F_MC_RI_17,
  F_MC_RI_16, F_MC_RI_15, F_MC_RI_14, F_MC_RI_13, F_MC_RI_12, F_MC_RI_11,
  F_MC_RI_10, F_MC_RI_9, F_MC_RI_8, F_MC_RI_7, F_MC_RI_6, F_MC_RI_5,
  F_MC_RI_4, F_MC_RI_3, F_MC_RI_2, F_MC_RI_1, F_MC_RI_0, F_MC_RIFIFO_WE,
  F_MC_WCLK, F_MC_WD_73, F_MC_WD_72, F_MC_WD_71, F_MC_WD_70, F_MC_WD_69,
  F_MC_WD_68, F_MC_WD_67, F_MC_WD_66, F_MC_WD_65, F_MC_WD_64, F_MC_WD_63,
  F_MC_WD_62, F_MC_WD_61, F_MC_WD_60, F_MC_WD_59, F_MC_WD_58, F_MC_WD_57,
  F_MC_WD_56, F_MC_WD_55, F_MC_WD_54, F_MC_WD_53, F_MC_WD_52, F_MC_WD_51,
  F_MC_WD_50, F_MC_WD_49, F_MC_WD_48, F_MC_WD_47, F_MC_WD_46, F_MC_WD_45,
  F_MC_WD_44, F_MC_WD_43, F_MC_WD_42, F_MC_WD_41, F_MC_WD_40, F_MC_WD_39,
  F_MC_WD_38, F_MC_WD_37, F_MC_WD_36, F_MC_WD_35, F_MC_WD_34, F_MC_WD_33,
  F_MC_WD_32, F_MC_WD_31, F_MC_WD_30, F_MC_WD_29, F_MC_WD_28, F_MC_WD_27,
  F_MC_WD_26, F_MC_WD_25, F_MC_WD_24, F_MC_WD_23, F_MC_WD_22, F_MC_WD_21,
  F_MC_WD_20, F_MC_WD_19, F_MC_WD_18, F_MC_WD_17, F_MC_WD_16, F_MC_WD_15,
  F_MC_WD_14, F_MC_WD_13, F_MC_WD_12, F_MC_WD_11, F_MC_WD_10, F_MC_WD_9,
  F_MC_WD_8, F_MC_WD_7, F_MC_WD_6, F_MC_WD_5, F_MC_WD_4, F_MC_WD_3,
  F_MC_WD_2, F_MC_WD_1, F_MC_WD_0, F_MC_WDFIFO_WE, F_MC_WI_31, F_MC_WI_30,
  F_MC_WI_29, F_MC_WI_28, F_MC_WI_27, F_MC_WI_26, F_MC_WI_25, F_MC_WI_24,
  F_MC_WI_23, F_MC_WI_22, F_MC_WI_21, F_MC_WI_20, F_MC_WI_19, F_MC_WI_18,
  F_MC_WI_17, F_MC_WI_16, F_MC_WI_15, F_MC_WI_14, F_MC_WI_13, F_MC_WI_12,
  F_MC_WI_11, F_MC_WI_10, F_MC_WI_9, F_MC_WI_8, F_MC_WI_7, F_MC_WI_6,
  F_MC_WI_5, F_MC_WI_4, F_MC_WI_3, F_MC_WI_2, F_MC_WI_1, F_MC_WI_0,
  F_MC_WIFIFO_WE, GSRN_DISABLE, GSRN_TOA, HADDR_17, HADDR_16, HADDR_15,
  HADDR_14, HADDR_13, HADDR_12, HADDR_11, HADDR_10, HADDR_9, HADDR_8,
  HADDR_7, HADDR_6, HADDR_5, HADDR_4, HADDR_3, HADDR_2, HADDR_1, HADDR_0,
  HBURST, HCLK, HDINN_A, HDINN_B, HDINN_C, HDINN_D, HDINP_A, HDINP_B,
  HDINP_C, HDINP_D, HREADY_IN, HRESET_N, HSEL, HSIZE_1, HSIZE_0, HTRANS_1,
  HTRANS_0, HWDATA_7, HWDATA_6, HWDATA_5, HWDATA_4, HWDATA_3, HWDATA_2,
  HWDATA_1, HWDATA_0, HWRITE, PARITY_ODD, PDN, PWRUPRES, REF10, REF14,
  REFCLKN, REFCLKP, RESETN, RESHI, RESLO, RSYS_CLK_AB, RSYS_CLK_CD,
  SERDES_LS_LOOP_MODE, SI_FRFPGA, SPIA_TREFCLK_X8, SPIB_TREFCLK_X8, 
  SPI_SATM_A, SPI_SATM_B,
  SPI_DATM_A, SPI_DATM_B, SPI_DLYTAP_A_2, SPI_DLYTAP_A_1, SPI_DLYTAP_A_0,
  SPI_DLYTAP_B_2, SPI_DLYTAP_B_1, SPI_DLYTAP_B_0,
  SYS_RST_N, TBIT9A_3, TBIT9A_2, TBIT9A_1, TBIT9A_0, TBIT9B_3, TBIT9B_2,
  TBIT9B_1, TBIT9B_0, TBIT9C_3, TBIT9C_2, TBIT9C_1, TBIT9C_0, TBIT9D_3,
  TBIT9D_2, TBIT9D_1, TBIT9D_0, TCKI, TCOMMAA_3, TCOMMAA_2, TCOMMAA_1,
  TCOMMAA_0, TCOMMAB_3, TCOMMAB_2, TCOMMAB_1, TCOMMAB_0, TCOMMAC_3,
  TCOMMAC_2, TCOMMAC_1, TCOMMAC_0, TCOMMAD_3, TCOMMAD_2, TCOMMAD_1,
  TCOMMAD_0, TESTCLK, TESTMD0N, TESTMD1N, TRISTN, TRI_IO, TSCLKA, TSCLKB,
  TSTAT0A, TSTAT0B, TSTAT1A, TSTAT1B, TSYS_CLK_A, TSYS_CLK_B, TSYS_CLK_C,
  TSYS_CLK_D, TS_ALL, TWDA_31, TWDA_30, TWDA_29, TWDA_28, TWDA_27,
  TWDA_26, TWDA_25, TWDA_24, TWDA_23, TWDA_22, TWDA_21, TWDA_20, TWDA_19,
  TWDA_18, TWDA_17, TWDA_16, TWDA_15, TWDA_14, TWDA_13, TWDA_12, TWDA_11,
  TWDA_10, TWDA_9, TWDA_8, TWDA_7, TWDA_6, TWDA_5, TWDA_4, TWDA_3, TWDA_2,
  TWDA_1, TWDA_0, TWDB_31, TWDB_30, TWDB_29, TWDB_28, TWDB_27, TWDB_26,
  TWDB_25, TWDB_24, TWDB_23, TWDB_22, TWDB_21, TWDB_20, TWDB_19, TWDB_18,
  TWDB_17, TWDB_16, TWDB_15, TWDB_14, TWDB_13, TWDB_12, TWDB_11, TWDB_10,
  TWDB_9, TWDB_8, TWDB_7, TWDB_6, TWDB_5, TWDB_4, TWDB_3, TWDB_2, TWDB_1,
  TWDB_0, TWDC_31, TWDC_30, TWDC_29, TWDC_28, TWDC_27, TWDC_26, TWDC_25,
  TWDC_24, TWDC_23, TWDC_22, TWDC_21, TWDC_20, TWDC_19, TWDC_18, TWDC_17,
  TWDC_16, TWDC_15, TWDC_14, TWDC_13, TWDC_12, TWDC_11, TWDC_10, TWDC_9,
  TWDC_8, TWDC_7, TWDC_6, TWDC_5, TWDC_4, TWDC_3, TWDC_2, TWDC_1, TWDC_0,
  TWDD_31, TWDD_30, TWDD_29, TWDD_28, TWDD_27, TWDD_26, TWDD_25, TWDD_24,
  TWDD_23, TWDD_22, TWDD_21, TWDD_20, TWDD_19, TWDD_18, TWDD_17, TWDD_16,
  TWDD_15, TWDD_14, TWDD_13, TWDD_12, TWDD_11, TWDD_10, TWDD_9, TWDD_8,
  TWDD_7, TWDD_6, TWDD_5, TWDD_4, TWDD_3, TWDD_2, TWDD_1, TWDD_0, WAIT_1,
  WAIT_0, ABURST_VAL_3, ABURST_VAL_2, ABURST_VAL_1, ABURST_VAL_0,
  ARLSCLK_F, ARSCLKN, ARSCLKP, ARSTAT0N, ARSTAT0P, ARSTAT1N, ARSTAT1P,
  ARX_D0_39, ARX_D0_38, ARX_D0_37, ARX_D0_36, ARX_D0_35, ARX_D0_34,
  ARX_D0_33, ARX_D0_32, ARX_D0_31, ARX_D0_30, ARX_D0_29, ARX_D0_28,
  ARX_D0_27, ARX_D0_26, ARX_D0_25, ARX_D0_24, ARX_D0_23, ARX_D0_22,
  ARX_D0_21, ARX_D0_20, ARX_D0_19, ARX_D0_18, ARX_D0_17, ARX_D0_16,
  ARX_D0_15, ARX_D0_14, ARX_D0_13, ARX_D0_12, ARX_D0_11, ARX_D0_10,
  ARX_D0_9, ARX_D0_8, ARX_D0_7, ARX_D0_6, ARX_D0_5, ARX_D0_4, ARX_D0_3,
  ARX_D0_2, ARX_D0_1, ARX_D0_0, ARX_D1_39, ARX_D1_38, ARX_D1_37,
  ARX_D1_36, ARX_D1_35, ARX_D1_34, ARX_D1_33, ARX_D1_32, ARX_D1_31,
  ARX_D1_30, ARX_D1_29, ARX_D1_28, ARX_D1_27, ARX_D1_26, ARX_D1_25,
  ARX_D1_24, ARX_D1_23, ARX_D1_22, ARX_D1_21, ARX_D1_20, ARX_D1_19,
  ARX_D1_18, ARX_D1_17, ARX_D1_16, ARX_D1_15, ARX_D1_14, ARX_D1_13,
  ARX_D1_12, ARX_D1_11, ARX_D1_10, ARX_D1_9, ARX_D1_8, ARX_D1_7, ARX_D1_6,
  ARX_D1_5, ARX_D1_4, ARX_D1_3, ARX_D1_2, ARX_D1_1, ARX_D1_0, ARX_D2_39,
  ARX_D2_38, ARX_D2_37, ARX_D2_36, ARX_D2_35, ARX_D2_34, ARX_D2_33,
  ARX_D2_32, ARX_D2_31, ARX_D2_30, ARX_D2_29, ARX_D2_28, ARX_D2_27,
  ARX_D2_26, ARX_D2_25, ARX_D2_24, ARX_D2_23, ARX_D2_22, ARX_D2_21,
  ARX_D2_20, ARX_D2_19, ARX_D2_18, ARX_D2_17, ARX_D2_16, ARX_D2_15,
  ARX_D2_14, ARX_D2_13, ARX_D2_12, ARX_D2_11, ARX_D2_10, ARX_D2_9,
  ARX_D2_8, ARX_D2_7, ARX_D2_6, ARX_D2_5, ARX_D2_4, ARX_D2_3, ARX_D2_2,
  ARX_D2_1, ARX_D2_0, ARX_D3_39, ARX_D3_38, ARX_D3_37, ARX_D3_36,
  ARX_D3_35, ARX_D3_34, ARX_D3_33, ARX_D3_32, ARX_D3_31, ARX_D3_30,
  ARX_D3_29, ARX_D3_28, ARX_D3_27, ARX_D3_26, ARX_D3_25, ARX_D3_24,
  ARX_D3_23, ARX_D3_22, ARX_D3_21, ARX_D3_20, ARX_D3_19, ARX_D3_18,
  ARX_D3_17, ARX_D3_16, ARX_D3_15, ARX_D3_14, ARX_D3_13, ARX_D3_12,
  ARX_D3_11, ARX_D3_10, ARX_D3_9, ARX_D3_8, ARX_D3_7, ARX_D3_6, ARX_D3_5,
  ARX_D3_4, ARX_D3_3, ARX_D3_2, ARX_D3_1, ARX_D3_0, ARX_FIFO_EMPTY0,
  ARX_FIFO_EMPTY1, ARX_FIFO_EMPTY2, ARX_FIFO_EMPTY3, ASB_EN_SLI,
  ASB_IRQ_SLI, ATCTLN, ATCTLP, ATDAT0N, ATDAT0P, ATDAT10N, ATDAT10P,
  ATDAT11N, ATDAT11P, ATDAT12N, ATDAT12P, ATDAT13N, ATDAT13P, ATDAT14N,
  ATDAT14P, ATDAT15N, ATDAT15P, ATDAT1N, ATDAT1P, ATDAT2N, ATDAT2P,
  ATDAT3N, ATDAT3P, ATDAT4N, ATDAT4P, ATDAT5N, ATDAT5P, ATDAT6N, ATDAT6P,
  ATDAT7N, ATDAT7P, ATDAT8N, ATDAT8P, ATDAT9N, ATDAT9P, ATDCLKN, ATDCLKP,
  ATREFCLK_F, ATX_FIFO_FULL0, ATX_FIFO_FULL1, ATX_FIFO_FULL2,
  ATX_FIFO_FULL3, ATX_PORTID_7, ATX_PORTID_6, ATX_PORTID_5, ATX_PORTID_4,
  ATX_PORTID_3, ATX_PORTID_2, ATX_PORTID_1, ATX_PORTID_0, ATX_STAT_1,
  ATX_STAT_0, BBURST_VAL_3, BBURST_VAL_2, BBURST_VAL_1, BBURST_VAL_0,
  BRLSCLK_F, BRSCLKN, BRSCLKP, BRSTAT0N, BRSTAT0P, BRSTAT1N, BRSTAT1P,
  BRX_D0_MRWDA_39, BRX_D0_MRWDA_38, BRX_D0_MRWDA_37, BRX_D0_MRWDA_36,
  BRX_D0_MRWDA_35, BRX_D0_MRWDA_34, BRX_D0_MRWDA_33, BRX_D0_MRWDA_32,
  BRX_D0_MRWDA_31, BRX_D0_MRWDA_30, BRX_D0_MRWDA_29, BRX_D0_MRWDA_28,
  BRX_D0_MRWDA_27, BRX_D0_MRWDA_26, BRX_D0_MRWDA_25, BRX_D0_MRWDA_24,
  BRX_D0_MRWDA_23, BRX_D0_MRWDA_22, BRX_D0_MRWDA_21, BRX_D0_MRWDA_20,
  BRX_D0_MRWDA_19, BRX_D0_MRWDA_18, BRX_D0_MRWDA_17, BRX_D0_MRWDA_16,
  BRX_D0_MRWDA_15, BRX_D0_MRWDA_14, BRX_D0_MRWDA_13, BRX_D0_MRWDA_12,
  BRX_D0_MRWDA_11, BRX_D0_MRWDA_10, BRX_D0_MRWDA_9, BRX_D0_MRWDA_8,
  BRX_D0_MRWDA_7, BRX_D0_MRWDA_6, BRX_D0_MRWDA_5, BRX_D0_MRWDA_4,
  BRX_D0_MRWDA_3, BRX_D0_MRWDA_2, BRX_D0_MRWDA_1, BRX_D0_MRWDA_0,
  BRX_D1_MRWDB_39, BRX_D1_MRWDB_38, BRX_D1_MRWDB_37, BRX_D1_MRWDB_36,
  BRX_D1_MRWDB_35, BRX_D1_MRWDB_34, BRX_D1_MRWDB_33, BRX_D1_MRWDB_32,
  BRX_D1_MRWDB_31, BRX_D1_MRWDB_30, BRX_D1_MRWDB_29, BRX_D1_MRWDB_28,
  BRX_D1_MRWDB_27, BRX_D1_MRWDB_26, BRX_D1_MRWDB_25, BRX_D1_MRWDB_24,
  BRX_D1_MRWDB_23, BRX_D1_MRWDB_22, BRX_D1_MRWDB_21, BRX_D1_MRWDB_20,
  BRX_D1_MRWDB_19, BRX_D1_MRWDB_18, BRX_D1_MRWDB_17, BRX_D1_MRWDB_16,
  BRX_D1_MRWDB_15, BRX_D1_MRWDB_14, BRX_D1_MRWDB_13, BRX_D1_MRWDB_12,
  BRX_D1_MRWDB_11, BRX_D1_MRWDB_10, BRX_D1_MRWDB_9, BRX_D1_MRWDB_8,
  BRX_D1_MRWDB_7, BRX_D1_MRWDB_6, BRX_D1_MRWDB_5, BRX_D1_MRWDB_4,
  BRX_D1_MRWDB_3, BRX_D1_MRWDB_2, BRX_D1_MRWDB_1, BRX_D1_MRWDB_0,
  BRX_D2_MRWDC_39, BRX_D2_MRWDC_38, BRX_D2_MRWDC_37, BRX_D2_MRWDC_36,
  BRX_D2_MRWDC_35, BRX_D2_MRWDC_34, BRX_D2_MRWDC_33, BRX_D2_MRWDC_32,
  BRX_D2_MRWDC_31, BRX_D2_MRWDC_30, BRX_D2_MRWDC_29, BRX_D2_MRWDC_28,
  BRX_D2_MRWDC_27, BRX_D2_MRWDC_26, BRX_D2_MRWDC_25, BRX_D2_MRWDC_24,
  BRX_D2_MRWDC_23, BRX_D2_MRWDC_22, BRX_D2_MRWDC_21, BRX_D2_MRWDC_20,
  BRX_D2_MRWDC_19, BRX_D2_MRWDC_18, BRX_D2_MRWDC_17, BRX_D2_MRWDC_16,
  BRX_D2_MRWDC_15, BRX_D2_MRWDC_14, BRX_D2_MRWDC_13, BRX_D2_MRWDC_12,
  BRX_D2_MRWDC_11, BRX_D2_MRWDC_10, BRX_D2_MRWDC_9, BRX_D2_MRWDC_8,
  BRX_D2_MRWDC_7, BRX_D2_MRWDC_6, BRX_D2_MRWDC_5, BRX_D2_MRWDC_4,
  BRX_D2_MRWDC_3, BRX_D2_MRWDC_2, BRX_D2_MRWDC_1, BRX_D2_MRWDC_0,
  BRX_D3_MRWDD_39, BRX_D3_MRWDD_38, BRX_D3_MRWDD_37, BRX_D3_MRWDD_36,
  BRX_D3_MRWDD_35, BRX_D3_MRWDD_34, BRX_D3_MRWDD_33, BRX_D3_MRWDD_32,
  BRX_D3_MRWDD_31, BRX_D3_MRWDD_30, BRX_D3_MRWDD_29, BRX_D3_MRWDD_28,
  BRX_D3_MRWDD_27, BRX_D3_MRWDD_26, BRX_D3_MRWDD_25, BRX_D3_MRWDD_24,
  BRX_D3_MRWDD_23, BRX_D3_MRWDD_22, BRX_D3_MRWDD_21, BRX_D3_MRWDD_20,
  BRX_D3_MRWDD_19, BRX_D3_MRWDD_18, BRX_D3_MRWDD_17, BRX_D3_MRWDD_16,
  BRX_D3_MRWDD_15, BRX_D3_MRWDD_14, BRX_D3_MRWDD_13, BRX_D3_MRWDD_12,
  BRX_D3_MRWDD_11, BRX_D3_MRWDD_10, BRX_D3_MRWDD_9, BRX_D3_MRWDD_8,
  BRX_D3_MRWDD_7, BRX_D3_MRWDD_6, BRX_D3_MRWDD_5, BRX_D3_MRWDD_4,
  BRX_D3_MRWDD_3, BRX_D3_MRWDD_2, BRX_D3_MRWDD_1, BRX_D3_MRWDD_0,
  BRX_FIFO_EMPTY0, BRX_FIFO_EMPTY1, BRX_FIFO_EMPTY2, BRX_FIFO_EMPTY3,
  BS_CPTBSR_OUT, BS_MD_OUT, BS_SHBSRN_OUT, BS_TRESET_OUT, BS_UPDTBSR_OUT,
  BTCTLN, BTCTLP, BTDAT0N, BTDAT0P, BTDAT10N, BTDAT10P, BTDAT11N,
  BTDAT11P, BTDAT12N, BTDAT12P, BTDAT13N, BTDAT13P, BTDAT14N, BTDAT14P,
  BTDAT15N, BTDAT15P, BTDAT1N, BTDAT1P, BTDAT2N, BTDAT2P, BTDAT3N,
  BTDAT3P, BTDAT4N, BTDAT4P, BTDAT5N, BTDAT5P, BTDAT6N, BTDAT6P, BTDAT7N,
  BTDAT7P, BTDAT8N, BTDAT8P, BTDAT9N, BTDAT9P, BTDCLKN, BTDCLKP,
  BTREFCLK_F, BTX_FIFO_FULL0, BTX_FIFO_FULL1, BTX_FIFO_FULL2,
  BTX_FIFO_FULL3, BTX_PORTID_7, BTX_PORTID_6, BTX_PORTID_5, BTX_PORTID_4,
  BTX_PORTID_3, BTX_PORTID_2, BTX_PORTID_1, BTX_PORTID_0, BTX_STAT_1,
  BTX_STAT_0, HDOUTN_A, HDOUTN_B, HDOUTN_C, HDOUTN_D, HDOUTP_A, HDOUTP_B,
  HDOUTP_C, HDOUTP_D, HRDATA_35, HRDATA_34, HRDATA_33, HRDATA_32,
  HRDATA_31, HRDATA_30, HRDATA_29, HRDATA_28, HRDATA_27, HRDATA_26,
  HRDATA_25, HRDATA_24, HRDATA_23, HRDATA_22, HRDATA_21, HRDATA_20,
  HRDATA_19, HRDATA_18, HRDATA_17, HRDATA_16, HRDATA_15, HRDATA_14,
  HRDATA_13, HRDATA_12, HRDATA_11, HRDATA_10, HRDATA_9, HRDATA_8,
  HRDATA_7, HRDATA_6, HRDATA_5, HRDATA_4, HRDATA_3, HRDATA_2, HRDATA_1,
  HRDATA_0, HREADY_OUT, HRESP_1, HRESP_0, MC_RD_71, MC_RD_70, MC_RD_69,
  MC_RD_68, MC_RD_67, MC_RD_66, MC_RD_65, MC_RD_64, MC_RD_63, MC_RD_62,
  MC_RD_61, MC_RD_60, MC_RD_59, MC_RD_58, MC_RD_57, MC_RD_56, MC_RD_55,
  MC_RD_54, MC_RD_53, MC_RD_52, MC_RD_51, MC_RD_50, MC_RD_49, MC_RD_48,
  MC_RD_47, MC_RD_46, MC_RD_45, MC_RD_44, MC_RD_43, MC_RD_42, MC_RD_41,
  MC_RD_40, MC_RD_39, MC_RD_38, MC_RD_37, MC_RD_36, MC_RD_35, MC_RD_34,
  MC_RD_33, MC_RD_32, MC_RD_31, MC_RD_30, MC_RD_29, MC_RD_28, MC_RD_27,
  MC_RD_26, MC_RD_25, MC_RD_24, MC_RD_23, MC_RD_22, MC_RD_21, MC_RD_20,
  MC_RD_19, MC_RD_18, MC_RD_17, MC_RD_16, MC_RD_15, MC_RD_14, MC_RD_13,
  MC_RD_12, MC_RD_11, MC_RD_10, MC_RD_9, MC_RD_8, MC_RD_7, MC_RD_6,
  MC_RD_5, MC_RD_4, MC_RD_3, MC_RD_2, MC_RD_1, MC_RD_0, MC_RDFIFO_EMPTY,
  MC_RIFIFO_FULL, MC_SYSCLK, MC_WDFIFO_FULL, MC_WIFIFO_FULL, RCK78, REXT,
  REXTN, RSCLKA, RSCLKB, RSTAT0A, RSTAT0B, RSTAT1A, RSTAT1B, RWCKA, RWCKB,
  RWCKC, RWCKD, SO_TOFPGA, TCK78, TCKI_OUT, TIE_HI, TIE_LO, MCREFCLK,
  PMIA0, PMIA1, PMIA10, PMIA11, PMIA12, PMIA13, PMIA14, PMIA15, PMIA16,
  PMIA17, PMIA2, PMIA3, PMIA4, PMIA5, PMIA6, PMIA7, PMIA8, PMIA9, PMIC,
  PMICN, PMID0, PMID1, PMID10, PMID11, PMID12, PMID13, PMID14, PMID15,
  PMID16, PMID17, PMID18, PMID19, PMID2, PMID20, PMID21, PMID22, PMID23,
  PMID24, PMID25, PMID26, PMID27, PMID28, PMID29, PMID3, PMID30, PMID31,
  PMID32, PMID33, PMID34, PMID35, PMID4, PMID5, PMID6, PMID7, PMID8,
  PMID9, PMIK, PMIKN, PMIQ0, PMIQ1, PMIQ10, PMIQ11, PMIQ12, PMIQ13,
  PMIQ14, PMIQ15, PMIQ16, PMIQ17, PMIQ18, PMIQ19, PMIQ2, PMIQ20, PMIQ21,
  PMIQ22, PMIQ23, PMIQ24, PMIQ25, PMIQ26, PMIQ27, PMIQ28, PMIQ29, PMIQ3,
  PMIQ30, PMIQ31, PMIQ32, PMIQ33, PMIQ34, PMIQ35, PMIQ4, PMIQ5, PMIQ6,
  PMIQ7, PMIQ8, PMIQ9, PMIRN, PMIWN
);

// Ports

  input  ALVCTAP1;
  input  ALVCTAP2;
  input  ALVCTAP3;
  input  ALVCTAP4;
  input  ALVCTAP5;
  input  ARCTLN;
  input  ARCTLP;
  input  ARDAT0N;
  input  ARDAT0P;
  input  ARDAT10N;
  input  ARDAT10P;
  input  ARDAT11N;
  input  ARDAT11P;
  input  ARDAT12N;
  input  ARDAT12P;
  input  ARDAT13N;
  input  ARDAT13P;
  input  ARDAT14N;
  input  ARDAT14P;
  input  ARDAT15N;
  input  ARDAT15P;
  input  ARDAT1N;
  input  ARDAT1P;
  input  ARDAT2N;
  input  ARDAT2P;
  input  ARDAT3N;
  input  ARDAT3P;
  input  ARDAT4N;
  input  ARDAT4P;
  input  ARDAT5N;
  input  ARDAT5P;
  input  ARDAT6N;
  input  ARDAT6P;
  input  ARDAT7N;
  input  ARDAT7P;
  input  ARDAT8N;
  input  ARDAT8P;
  input  ARDAT9N;
  input  ARDAT9P;
  input  ARDCLKN;
  input  ARDCLKP;
  input  ARX_A0_2;
  input  ARX_A0_1;
  input  ARX_A0_0;
  input  ARX_A1_2;
  input  ARX_A1_1;
  input  ARX_A1_0;
  input  ARX_A2_2;
  input  ARX_A2_1;
  input  ARX_A2_0;
  input  ARX_A3_2;
  input  ARX_A3_1;
  input  ARX_A3_0;
  input  ARX_CLK0;
  input  ARX_CLK1;
  input  ARX_CLK2;
  input  ARX_CLK3;
  input  ARX_EXT_STATUS_ENABLE;
  input  ARX_FPGA_PORT_ID_7;
  input  ARX_FPGA_PORT_ID_6;
  input  ARX_FPGA_PORT_ID_5;
  input  ARX_FPGA_PORT_ID_4;
  input  ARX_FPGA_PORT_ID_3;
  input  ARX_FPGA_PORT_ID_2;
  input  ARX_FPGA_PORT_ID_1;
  input  ARX_FPGA_PORT_ID_0;
  input  ARX_PORT_STATUS_1;
  input  ARX_PORT_STATUS_0;
  input  ARX_PSS_CLK;
  input  ARX_PSS_WE;
  input  ARX_RE0;
  input  ARX_RE1;
  input  ARX_RE2;
  input  ARX_RE3;
  input  ASTOP_ON_EOP0;
  input  ASTOP_ON_EOP1;
  input  ASTOP_ON_EOP2;
  input  ASTOP_ON_EOP3;
  input  ATREFCLK;
  input  ATSCLKN;
  input  ATSCLKP;
  input  ATSTAT0N;
  input  ATSTAT0P;
  input  ATSTAT1N;
  input  ATSTAT1P;
  input  ATX_A0_2;
  input  ATX_A0_1;
  input  ATX_A0_0;
  input  ATX_A1_2;
  input  ATX_A1_1;
  input  ATX_A1_0;
  input  ATX_A2_2;
  input  ATX_A2_1;
  input  ATX_A2_0;
  input  ATX_A3_2;
  input  ATX_A3_1;
  input  ATX_A3_0;
  input  ATX_CLK0;
  input  ATX_CLK1;
  input  ATX_CLK2;
  input  ATX_CLK3;
  input  ATX_D0_39;
  input  ATX_D0_38;
  input  ATX_D0_37;
  input  ATX_D0_36;
  input  ATX_D0_35;
  input  ATX_D0_34;
  input  ATX_D0_33;
  input  ATX_D0_32;
  input  ATX_D0_31;
  input  ATX_D0_30;
  input  ATX_D0_29;
  input  ATX_D0_28;
  input  ATX_D0_27;
  input  ATX_D0_26;
  input  ATX_D0_25;
  input  ATX_D0_24;
  input  ATX_D0_23;
  input  ATX_D0_22;
  input  ATX_D0_21;
  input  ATX_D0_20;
  input  ATX_D0_19;
  input  ATX_D0_18;
  input  ATX_D0_17;
  input  ATX_D0_16;
  input  ATX_D0_15;
  input  ATX_D0_14;
  input  ATX_D0_13;
  input  ATX_D0_12;
  input  ATX_D0_11;
  input  ATX_D0_10;
  input  ATX_D0_9;
  input  ATX_D0_8;
  input  ATX_D0_7;
  input  ATX_D0_6;
  input  ATX_D0_5;
  input  ATX_D0_4;
  input  ATX_D0_3;
  input  ATX_D0_2;
  input  ATX_D0_1;
  input  ATX_D0_0;
  input  ATX_D1_39;
  input  ATX_D1_38;
  input  ATX_D1_37;
  input  ATX_D1_36;
  input  ATX_D1_35;
  input  ATX_D1_34;
  input  ATX_D1_33;
  input  ATX_D1_32;
  input  ATX_D1_31;
  input  ATX_D1_30;
  input  ATX_D1_29;
  input  ATX_D1_28;
  input  ATX_D1_27;
  input  ATX_D1_26;
  input  ATX_D1_25;
  input  ATX_D1_24;
  input  ATX_D1_23;
  input  ATX_D1_22;
  input  ATX_D1_21;
  input  ATX_D1_20;
  input  ATX_D1_19;
  input  ATX_D1_18;
  input  ATX_D1_17;
  input  ATX_D1_16;
  input  ATX_D1_15;
  input  ATX_D1_14;
  input  ATX_D1_13;
  input  ATX_D1_12;
  input  ATX_D1_11;
  input  ATX_D1_10;
  input  ATX_D1_9;
  input  ATX_D1_8;
  input  ATX_D1_7;
  input  ATX_D1_6;
  input  ATX_D1_5;
  input  ATX_D1_4;
  input  ATX_D1_3;
  input  ATX_D1_2;
  input  ATX_D1_1;
  input  ATX_D1_0;
  input  ATX_D2_39;
  input  ATX_D2_38;
  input  ATX_D2_37;
  input  ATX_D2_36;
  input  ATX_D2_35;
  input  ATX_D2_34;
  input  ATX_D2_33;
  input  ATX_D2_32;
  input  ATX_D2_31;
  input  ATX_D2_30;
  input  ATX_D2_29;
  input  ATX_D2_28;
  input  ATX_D2_27;
  input  ATX_D2_26;
  input  ATX_D2_25;
  input  ATX_D2_24;
  input  ATX_D2_23;
  input  ATX_D2_22;
  input  ATX_D2_21;
  input  ATX_D2_20;
  input  ATX_D2_19;
  input  ATX_D2_18;
  input  ATX_D2_17;
  input  ATX_D2_16;
  input  ATX_D2_15;
  input  ATX_D2_14;
  input  ATX_D2_13;
  input  ATX_D2_12;
  input  ATX_D2_11;
  input  ATX_D2_10;
  input  ATX_D2_9;
  input  ATX_D2_8;
  input  ATX_D2_7;
  input  ATX_D2_6;
  input  ATX_D2_5;
  input  ATX_D2_4;
  input  ATX_D2_3;
  input  ATX_D2_2;
  input  ATX_D2_1;
  input  ATX_D2_0;
  input  ATX_D3_39;
  input  ATX_D3_38;
  input  ATX_D3_37;
  input  ATX_D3_36;
  input  ATX_D3_35;
  input  ATX_D3_34;
  input  ATX_D3_33;
  input  ATX_D3_32;
  input  ATX_D3_31;
  input  ATX_D3_30;
  input  ATX_D3_29;
  input  ATX_D3_28;
  input  ATX_D3_27;
  input  ATX_D3_26;
  input  ATX_D3_25;
  input  ATX_D3_24;
  input  ATX_D3_23;
  input  ATX_D3_22;
  input  ATX_D3_21;
  input  ATX_D3_20;
  input  ATX_D3_19;
  input  ATX_D3_18;
  input  ATX_D3_17;
  input  ATX_D3_16;
  input  ATX_D3_15;
  input  ATX_D3_14;
  input  ATX_D3_13;
  input  ATX_D3_12;
  input  ATX_D3_11;
  input  ATX_D3_10;
  input  ATX_D3_9;
  input  ATX_D3_8;
  input  ATX_D3_7;
  input  ATX_D3_6;
  input  ATX_D3_5;
  input  ATX_D3_4;
  input  ATX_D3_3;
  input  ATX_D3_2;
  input  ATX_D3_1;
  input  ATX_D3_0;
  input  ATX_LINK_DIS0;
  input  ATX_LINK_DIS1;
  input  ATX_LINK_DIS2;
  input  ATX_LINK_DIS3;
  input  ATX_PORT0_7;
  input  ATX_PORT0_6;
  input  ATX_PORT0_5;
  input  ATX_PORT0_4;
  input  ATX_PORT0_3;
  input  ATX_PORT0_2;
  input  ATX_PORT0_1;
  input  ATX_PORT0_0;
  input  ATX_PORT1_7;
  input  ATX_PORT1_6;
  input  ATX_PORT1_5;
  input  ATX_PORT1_4;
  input  ATX_PORT1_3;
  input  ATX_PORT1_2;
  input  ATX_PORT1_1;
  input  ATX_PORT1_0;
  input  ATX_PORT2_7;
  input  ATX_PORT2_6;
  input  ATX_PORT2_5;
  input  ATX_PORT2_4;
  input  ATX_PORT2_3;
  input  ATX_PORT2_2;
  input  ATX_PORT2_1;
  input  ATX_PORT2_0;
  input  ATX_PORT3_7;
  input  ATX_PORT3_6;
  input  ATX_PORT3_5;
  input  ATX_PORT3_4;
  input  ATX_PORT3_3;
  input  ATX_PORT3_2;
  input  ATX_PORT3_1;
  input  ATX_PORT3_0;
  input  ATX_WE0;
  input  ATX_WE1;
  input  ATX_WE2;
  input  ATX_WE3;
  input  AWD_CNT_RST0;
  input  AWD_CNT_RST1;
  input  AWD_CNT_RST2;
  input  AWD_CNT_RST3;
  input  BLVCTAP1;
  input  BLVCTAP2;
  input  BLVCTAP3;
  input  BLVCTAP4;
  input  BLVCTAP5;
  input  BRCTLN;
  input  BRCTLP;
  input  BRDAT0N;
  input  BRDAT0P;
  input  BRDAT10N;
  input  BRDAT10P;
  input  BRDAT11N;
  input  BRDAT11P;
  input  BRDAT12N;
  input  BRDAT12P;
  input  BRDAT13N;
  input  BRDAT13P;
  input  BRDAT14N;
  input  BRDAT14P;
  input  BRDAT15N;
  input  BRDAT15P;
  input  BRDAT1N;
  input  BRDAT1P;
  input  BRDAT2N;
  input  BRDAT2P;
  input  BRDAT3N;
  input  BRDAT3P;
  input  BRDAT4N;
  input  BRDAT4P;
  input  BRDAT5N;
  input  BRDAT5P;
  input  BRDAT6N;
  input  BRDAT6P;
  input  BRDAT7N;
  input  BRDAT7P;
  input  BRDAT8N;
  input  BRDAT8P;
  input  BRDAT9N;
  input  BRDAT9P;
  input  BRDCLKN;
  input  BRDCLKP;
  input  BRX_A0_2;
  input  BRX_A0_1;
  input  BRX_A0_0;
  input  BRX_A1_2;
  input  BRX_A1_1;
  input  BRX_A1_0;
  input  BRX_A2_2;
  input  BRX_A2_1;
  input  BRX_A2_0;
  input  BRX_A3_2;
  input  BRX_A3_1;
  input  BRX_A3_0;
  input  BRX_CLK0;
  input  BRX_CLK1;
  input  BRX_CLK2;
  input  BRX_CLK3;
  input  BRX_EXT_STATUS_ENABLE;
  input  BRX_FPGA_PORT_ID_7;
  input  BRX_FPGA_PORT_ID_6;
  input  BRX_FPGA_PORT_ID_5;
  input  BRX_FPGA_PORT_ID_4;
  input  BRX_FPGA_PORT_ID_3;
  input  BRX_FPGA_PORT_ID_2;
  input  BRX_FPGA_PORT_ID_1;
  input  BRX_FPGA_PORT_ID_0;
  input  BRX_PORT_STATUS_1;
  input  BRX_PORT_STATUS_0;
  input  BRX_PSS_CLK;
  input  BRX_PSS_WE;
  input  BRX_RE0;
  input  BRX_RE1;
  input  BRX_RE2;
  input  BRX_RE3;
  input  BSTOP_ON_EOP0;
  input  BSTOP_ON_EOP1;
  input  BSTOP_ON_EOP2;
  input  BSTOP_ON_EOP3;
  input  BS_CPTBSR;
  input  BS_MD;
  input  BS_SHBSRN;
  input  BS_TRESET;
  input  BS_UPDTBSR;
  input  BTREFCLK;
  input  BTSCLKN;
  input  BTSCLKP;
  input  BTSTAT0N;
  input  BTSTAT0P;
  input  BTSTAT1N;
  input  BTSTAT1P;
  input  BTX_A0_2;
  input  BTX_A0_1;
  input  BTX_A0_0;
  input  BTX_A1_2;
  input  BTX_A1_1;
  input  BTX_A1_0;
  input  BTX_A2_2;
  input  BTX_A2_1;
  input  BTX_A2_0;
  input  BTX_A3_2;
  input  BTX_A3_1;
  input  BTX_A3_0;
  input  BTX_CLK0;
  input  BTX_CLK1;
  input  BTX_CLK2;
  input  BTX_CLK3;
  input  BTX_D0_39;
  input  BTX_D0_38;
  input  BTX_D0_37;
  input  BTX_D0_36;
  input  BTX_D0_35;
  input  BTX_D0_34;
  input  BTX_D0_33;
  input  BTX_D0_32;
  input  BTX_D0_31;
  input  BTX_D0_30;
  input  BTX_D0_29;
  input  BTX_D0_28;
  input  BTX_D0_27;
  input  BTX_D0_26;
  input  BTX_D0_25;
  input  BTX_D0_24;
  input  BTX_D0_23;
  input  BTX_D0_22;
  input  BTX_D0_21;
  input  BTX_D0_20;
  input  BTX_D0_19;
  input  BTX_D0_18;
  input  BTX_D0_17;
  input  BTX_D0_16;
  input  BTX_D0_15;
  input  BTX_D0_14;
  input  BTX_D0_13;
  input  BTX_D0_12;
  input  BTX_D0_11;
  input  BTX_D0_10;
  input  BTX_D0_9;
  input  BTX_D0_8;
  input  BTX_D0_7;
  input  BTX_D0_6;
  input  BTX_D0_5;
  input  BTX_D0_4;
  input  BTX_D0_3;
  input  BTX_D0_2;
  input  BTX_D0_1;
  input  BTX_D0_0;
  input  BTX_D1_39;
  input  BTX_D1_38;
  input  BTX_D1_37;
  input  BTX_D1_36;
  input  BTX_D1_35;
  input  BTX_D1_34;
  input  BTX_D1_33;
  input  BTX_D1_32;
  input  BTX_D1_31;
  input  BTX_D1_30;
  input  BTX_D1_29;
  input  BTX_D1_28;
  input  BTX_D1_27;
  input  BTX_D1_26;
  input  BTX_D1_25;
  input  BTX_D1_24;
  input  BTX_D1_23;
  input  BTX_D1_22;
  input  BTX_D1_21;
  input  BTX_D1_20;
  input  BTX_D1_19;
  input  BTX_D1_18;
  input  BTX_D1_17;
  input  BTX_D1_16;
  input  BTX_D1_15;
  input  BTX_D1_14;
  input  BTX_D1_13;
  input  BTX_D1_12;
  input  BTX_D1_11;
  input  BTX_D1_10;
  input  BTX_D1_9;
  input  BTX_D1_8;
  input  BTX_D1_7;
  input  BTX_D1_6;
  input  BTX_D1_5;
  input  BTX_D1_4;
  input  BTX_D1_3;
  input  BTX_D1_2;
  input  BTX_D1_1;
  input  BTX_D1_0;
  input  BTX_D2_39;
  input  BTX_D2_38;
  input  BTX_D2_37;
  input  BTX_D2_36;
  input  BTX_D2_35;
  input  BTX_D2_34;
  input  BTX_D2_33;
  input  BTX_D2_32;
  input  BTX_D2_31;
  input  BTX_D2_30;
  input  BTX_D2_29;
  input  BTX_D2_28;
  input  BTX_D2_27;
  input  BTX_D2_26;
  input  BTX_D2_25;
  input  BTX_D2_24;
  input  BTX_D2_23;
  input  BTX_D2_22;
  input  BTX_D2_21;
  input  BTX_D2_20;
  input  BTX_D2_19;
  input  BTX_D2_18;
  input  BTX_D2_17;
  input  BTX_D2_16;
  input  BTX_D2_15;
  input  BTX_D2_14;
  input  BTX_D2_13;
  input  BTX_D2_12;
  input  BTX_D2_11;
  input  BTX_D2_10;
  input  BTX_D2_9;
  input  BTX_D2_8;
  input  BTX_D2_7;
  input  BTX_D2_6;
  input  BTX_D2_5;
  input  BTX_D2_4;
  input  BTX_D2_3;
  input  BTX_D2_2;
  input  BTX_D2_1;
  input  BTX_D2_0;
  input  BTX_D3_39;
  input  BTX_D3_38;
  input  BTX_D3_37;
  input  BTX_D3_36;
  input  BTX_D3_35;
  input  BTX_D3_34;
  input  BTX_D3_33;
  input  BTX_D3_32;
  input  BTX_D3_31;
  input  BTX_D3_30;
  input  BTX_D3_29;
  input  BTX_D3_28;
  input  BTX_D3_27;
  input  BTX_D3_26;
  input  BTX_D3_25;
  input  BTX_D3_24;
  input  BTX_D3_23;
  input  BTX_D3_22;
  input  BTX_D3_21;
  input  BTX_D3_20;
  input  BTX_D3_19;
  input  BTX_D3_18;
  input  BTX_D3_17;
  input  BTX_D3_16;
  input  BTX_D3_15;
  input  BTX_D3_14;
  input  BTX_D3_13;
  input  BTX_D3_12;
  input  BTX_D3_11;
  input  BTX_D3_10;
  input  BTX_D3_9;
  input  BTX_D3_8;
  input  BTX_D3_7;
  input  BTX_D3_6;
  input  BTX_D3_5;
  input  BTX_D3_4;
  input  BTX_D3_3;
  input  BTX_D3_2;
  input  BTX_D3_1;
  input  BTX_D3_0;
  input  BTX_LINK_DIS0;
  input  BTX_LINK_DIS1;
  input  BTX_LINK_DIS2;
  input  BTX_LINK_DIS3;
  input  BTX_PORT0_7;
  input  BTX_PORT0_6;
  input  BTX_PORT0_5;
  input  BTX_PORT0_4;
  input  BTX_PORT0_3;
  input  BTX_PORT0_2;
  input  BTX_PORT0_1;
  input  BTX_PORT0_0;
  input  BTX_PORT1_7;
  input  BTX_PORT1_6;
  input  BTX_PORT1_5;
  input  BTX_PORT1_4;
  input  BTX_PORT1_3;
  input  BTX_PORT1_2;
  input  BTX_PORT1_1;
  input  BTX_PORT1_0;
  input  BTX_PORT2_7;
  input  BTX_PORT2_6;
  input  BTX_PORT2_5;
  input  BTX_PORT2_4;
  input  BTX_PORT2_3;
  input  BTX_PORT2_2;
  input  BTX_PORT2_1;
  input  BTX_PORT2_0;
  input  BTX_PORT3_7;
  input  BTX_PORT3_6;
  input  BTX_PORT3_5;
  input  BTX_PORT3_4;
  input  BTX_PORT3_3;
  input  BTX_PORT3_2;
  input  BTX_PORT3_1;
  input  BTX_PORT3_0;
  input  BTX_WE0;
  input  BTX_WE1;
  input  BTX_WE2;
  input  BTX_WE3;
  input  BWD_CNT_RST0;
  input  BWD_CNT_RST1;
  input  BWD_CNT_RST2;
  input  BWD_CNT_RST3;
  input  CV_SELA;
  input  CV_SELB;
  input  CV_SELC;
  input  CV_SELD;
  input  DIVIDE_1;
  input  DIVIDE_0;
  input  DONE;
  input  ENABLE_SPI4_B;
  input  EXT_1K;
  input  FPGA_RESET_FC;
  input  FPGA_RESET_MC;
  input  FPGA_RESET_S4A;
  input  FPGA_RESET_S4B;
  input  F_MC_RCLK;
  input  F_MC_RDFIFO_RE;
  input  F_MC_REFCLK;
  input  F_MC_RI_31;
  input  F_MC_RI_30;
  input  F_MC_RI_29;
  input  F_MC_RI_28;
  input  F_MC_RI_27;
  input  F_MC_RI_26;
  input  F_MC_RI_25;
  input  F_MC_RI_24;
  input  F_MC_RI_23;
  input  F_MC_RI_22;
  input  F_MC_RI_21;
  input  F_MC_RI_20;
  input  F_MC_RI_19;
  input  F_MC_RI_18;
  input  F_MC_RI_17;
  input  F_MC_RI_16;
  input  F_MC_RI_15;
  input  F_MC_RI_14;
  input  F_MC_RI_13;
  input  F_MC_RI_12;
  input  F_MC_RI_11;
  input  F_MC_RI_10;
  input  F_MC_RI_9;
  input  F_MC_RI_8;
  input  F_MC_RI_7;
  input  F_MC_RI_6;
  input  F_MC_RI_5;
  input  F_MC_RI_4;
  input  F_MC_RI_3;
  input  F_MC_RI_2;
  input  F_MC_RI_1;
  input  F_MC_RI_0;
  input  F_MC_RIFIFO_WE;
  input  F_MC_WCLK;
  input  F_MC_WD_73;
  input  F_MC_WD_72;
  input  F_MC_WD_71;
  input  F_MC_WD_70;
  input  F_MC_WD_69;
  input  F_MC_WD_68;
  input  F_MC_WD_67;
  input  F_MC_WD_66;
  input  F_MC_WD_65;
  input  F_MC_WD_64;
  input  F_MC_WD_63;
  input  F_MC_WD_62;
  input  F_MC_WD_61;
  input  F_MC_WD_60;
  input  F_MC_WD_59;
  input  F_MC_WD_58;
  input  F_MC_WD_57;
  input  F_MC_WD_56;
  input  F_MC_WD_55;
  input  F_MC_WD_54;
  input  F_MC_WD_53;
  input  F_MC_WD_52;
  input  F_MC_WD_51;
  input  F_MC_WD_50;
  input  F_MC_WD_49;
  input  F_MC_WD_48;
  input  F_MC_WD_47;
  input  F_MC_WD_46;
  input  F_MC_WD_45;
  input  F_MC_WD_44;
  input  F_MC_WD_43;
  input  F_MC_WD_42;
  input  F_MC_WD_41;
  input  F_MC_WD_40;
  input  F_MC_WD_39;
  input  F_MC_WD_38;
  input  F_MC_WD_37;
  input  F_MC_WD_36;
  input  F_MC_WD_35;
  input  F_MC_WD_34;
  input  F_MC_WD_33;
  input  F_MC_WD_32;
  input  F_MC_WD_31;
  input  F_MC_WD_30;
  input  F_MC_WD_29;
  input  F_MC_WD_28;
  input  F_MC_WD_27;
  input  F_MC_WD_26;
  input  F_MC_WD_25;
  input  F_MC_WD_24;
  input  F_MC_WD_23;
  input  F_MC_WD_22;
  input  F_MC_WD_21;
  input  F_MC_WD_20;
  input  F_MC_WD_19;
  input  F_MC_WD_18;
  input  F_MC_WD_17;
  input  F_MC_WD_16;
  input  F_MC_WD_15;
  input  F_MC_WD_14;
  input  F_MC_WD_13;
  input  F_MC_WD_12;
  input  F_MC_WD_11;
  input  F_MC_WD_10;
  input  F_MC_WD_9;
  input  F_MC_WD_8;
  input  F_MC_WD_7;
  input  F_MC_WD_6;
  input  F_MC_WD_5;
  input  F_MC_WD_4;
  input  F_MC_WD_3;
  input  F_MC_WD_2;
  input  F_MC_WD_1;
  input  F_MC_WD_0;
  input  F_MC_WDFIFO_WE;
  input  F_MC_WI_31;
  input  F_MC_WI_30;
  input  F_MC_WI_29;
  input  F_MC_WI_28;
  input  F_MC_WI_27;
  input  F_MC_WI_26;
  input  F_MC_WI_25;
  input  F_MC_WI_24;
  input  F_MC_WI_23;
  input  F_MC_WI_22;
  input  F_MC_WI_21;
  input  F_MC_WI_20;
  input  F_MC_WI_19;
  input  F_MC_WI_18;
  input  F_MC_WI_17;
  input  F_MC_WI_16;
  input  F_MC_WI_15;
  input  F_MC_WI_14;
  input  F_MC_WI_13;
  input  F_MC_WI_12;
  input  F_MC_WI_11;
  input  F_MC_WI_10;
  input  F_MC_WI_9;
  input  F_MC_WI_8;
  input  F_MC_WI_7;
  input  F_MC_WI_6;
  input  F_MC_WI_5;
  input  F_MC_WI_4;
  input  F_MC_WI_3;
  input  F_MC_WI_2;
  input  F_MC_WI_1;
  input  F_MC_WI_0;
  input  F_MC_WIFIFO_WE;
  input  GSRN_DISABLE;
  input  GSRN_TOA;
  input  HADDR_17;
  input  HADDR_16;
  input  HADDR_15;
  input  HADDR_14;
  input  HADDR_13;
  input  HADDR_12;
  input  HADDR_11;
  input  HADDR_10;
  input  HADDR_9;
  input  HADDR_8;
  input  HADDR_7;
  input  HADDR_6;
  input  HADDR_5;
  input  HADDR_4;
  input  HADDR_3;
  input  HADDR_2;
  input  HADDR_1;
  input  HADDR_0;
  input  HBURST;
  input  HCLK;
  input  HDINN_A;
  input  HDINN_B;
  input  HDINN_C;
  input  HDINN_D;
  input  HDINP_A;
  input  HDINP_B;
  input  HDINP_C;
  input  HDINP_D;
  input  HREADY_IN;
  input  HRESET_N;
  input  HSEL;
  input  HSIZE_1;
  input  HSIZE_0;
  input  HTRANS_1;
  input  HTRANS_0;
  input  HWDATA_7;
  input  HWDATA_6;
  input  HWDATA_5;
  input  HWDATA_4;
  input  HWDATA_3;
  input  HWDATA_2;
  input  HWDATA_1;
  input  HWDATA_0;
  input  HWRITE;
  input  PARITY_ODD;
  input  PDN;
  input  PWRUPRES;
  input  REF10;
  input  REF14;
  input  REFCLKN;
  input  REFCLKP;
  input  RESETN;
  input  RESHI;
  input  RESLO;
  input  RSYS_CLK_AB;
  input  RSYS_CLK_CD;
  input  SERDES_LS_LOOP_MODE;
  input  SI_FRFPGA;
  input  SPIA_TREFCLK_X8;
  input  SPIB_TREFCLK_X8;
  input  SPI_SATM_A;
  input  SPI_SATM_B;
  input  SPI_DATM_A;
  input  SPI_DATM_B;
  input  SPI_DLYTAP_A_2;
  input  SPI_DLYTAP_A_1;
  input  SPI_DLYTAP_A_0;
  input  SPI_DLYTAP_B_2;
  input  SPI_DLYTAP_B_1;
  input  SPI_DLYTAP_B_0; 
  input  SYS_RST_N;
  input  TBIT9A_3;
  input  TBIT9A_2;
  input  TBIT9A_1;
  input  TBIT9A_0;
  input  TBIT9B_3;
  input  TBIT9B_2;
  input  TBIT9B_1;
  input  TBIT9B_0;
  input  TBIT9C_3;
  input  TBIT9C_2;
  input  TBIT9C_1;
  input  TBIT9C_0;
  input  TBIT9D_3;
  input  TBIT9D_2;
  input  TBIT9D_1;
  input  TBIT9D_0;
  input  TCKI;
  input  TCOMMAA_3;
  input  TCOMMAA_2;
  input  TCOMMAA_1;
  input  TCOMMAA_0;
  input  TCOMMAB_3;
  input  TCOMMAB_2;
  input  TCOMMAB_1;
  input  TCOMMAB_0;
  input  TCOMMAC_3;
  input  TCOMMAC_2;
  input  TCOMMAC_1;
  input  TCOMMAC_0;
  input  TCOMMAD_3;
  input  TCOMMAD_2;
  input  TCOMMAD_1;
  input  TCOMMAD_0;
  input  TESTCLK;
  input  TESTMD0N;
  input  TESTMD1N;
  input  TRISTN;
  input  TRI_IO;
  input  TSCLKA;
  input  TSCLKB;
  input  TSTAT0A;
  input  TSTAT0B;
  input  TSTAT1A;
  input  TSTAT1B;
  input  TSYS_CLK_A;
  input  TSYS_CLK_B;
  input  TSYS_CLK_C;
  input  TSYS_CLK_D;
  input  TS_ALL;
  input  TWDA_31;
  input  TWDA_30;
  input  TWDA_29;
  input  TWDA_28;
  input  TWDA_27;
  input  TWDA_26;
  input  TWDA_25;
  input  TWDA_24;
  input  TWDA_23;
  input  TWDA_22;
  input  TWDA_21;
  input  TWDA_20;
  input  TWDA_19;
  input  TWDA_18;
  input  TWDA_17;
  input  TWDA_16;
  input  TWDA_15;
  input  TWDA_14;
  input  TWDA_13;
  input  TWDA_12;
  input  TWDA_11;
  input  TWDA_10;
  input  TWDA_9;
  input  TWDA_8;
  input  TWDA_7;
  input  TWDA_6;
  input  TWDA_5;
  input  TWDA_4;
  input  TWDA_3;
  input  TWDA_2;
  input  TWDA_1;
  input  TWDA_0;
  input  TWDB_31;
  input  TWDB_30;
  input  TWDB_29;
  input  TWDB_28;
  input  TWDB_27;
  input  TWDB_26;
  input  TWDB_25;
  input  TWDB_24;
  input  TWDB_23;
  input  TWDB_22;
  input  TWDB_21;
  input  TWDB_20;
  input  TWDB_19;
  input  TWDB_18;
  input  TWDB_17;
  input  TWDB_16;
  input  TWDB_15;
  input  TWDB_14;
  input  TWDB_13;
  input  TWDB_12;
  input  TWDB_11;
  input  TWDB_10;
  input  TWDB_9;
  input  TWDB_8;
  input  TWDB_7;
  input  TWDB_6;
  input  TWDB_5;
  input  TWDB_4;
  input  TWDB_3;
  input  TWDB_2;
  input  TWDB_1;
  input  TWDB_0;
  input  TWDC_31;
  input  TWDC_30;
  input  TWDC_29;
  input  TWDC_28;
  input  TWDC_27;
  input  TWDC_26;
  input  TWDC_25;
  input  TWDC_24;
  input  TWDC_23;
  input  TWDC_22;
  input  TWDC_21;
  input  TWDC_20;
  input  TWDC_19;
  input  TWDC_18;
  input  TWDC_17;
  input  TWDC_16;
  input  TWDC_15;
  input  TWDC_14;
  input  TWDC_13;
  input  TWDC_12;
  input  TWDC_11;
  input  TWDC_10;
  input  TWDC_9;
  input  TWDC_8;
  input  TWDC_7;
  input  TWDC_6;
  input  TWDC_5;
  input  TWDC_4;
  input  TWDC_3;
  input  TWDC_2;
  input  TWDC_1;
  input  TWDC_0;
  input  TWDD_31;
  input  TWDD_30;
  input  TWDD_29;
  input  TWDD_28;
  input  TWDD_27;
  input  TWDD_26;
  input  TWDD_25;
  input  TWDD_24;
  input  TWDD_23;
  input  TWDD_22;
  input  TWDD_21;
  input  TWDD_20;
  input  TWDD_19;
  input  TWDD_18;
  input  TWDD_17;
  input  TWDD_16;
  input  TWDD_15;
  input  TWDD_14;
  input  TWDD_13;
  input  TWDD_12;
  input  TWDD_11;
  input  TWDD_10;
  input  TWDD_9;
  input  TWDD_8;
  input  TWDD_7;
  input  TWDD_6;
  input  TWDD_5;
  input  TWDD_4;
  input  TWDD_3;
  input  TWDD_2;
  input  TWDD_1;
  input  TWDD_0;
  input  WAIT_1;
  input  WAIT_0;
  output ABURST_VAL_3;
  output ABURST_VAL_2;
  output ABURST_VAL_1;
  output ABURST_VAL_0;
  output ARLSCLK_F;
  output ARSCLKN;
  output ARSCLKP;
  output ARSTAT0N;
  output ARSTAT0P;
  output ARSTAT1N;
  output ARSTAT1P;
  output ARX_D0_39;
  output ARX_D0_38;
  output ARX_D0_37;
  output ARX_D0_36;
  output ARX_D0_35;
  output ARX_D0_34;
  output ARX_D0_33;
  output ARX_D0_32;
  output ARX_D0_31;
  output ARX_D0_30;
  output ARX_D0_29;
  output ARX_D0_28;
  output ARX_D0_27;
  output ARX_D0_26;
  output ARX_D0_25;
  output ARX_D0_24;
  output ARX_D0_23;
  output ARX_D0_22;
  output ARX_D0_21;
  output ARX_D0_20;
  output ARX_D0_19;
  output ARX_D0_18;
  output ARX_D0_17;
  output ARX_D0_16;
  output ARX_D0_15;
  output ARX_D0_14;
  output ARX_D0_13;
  output ARX_D0_12;
  output ARX_D0_11;
  output ARX_D0_10;
  output ARX_D0_9;
  output ARX_D0_8;
  output ARX_D0_7;
  output ARX_D0_6;
  output ARX_D0_5;
  output ARX_D0_4;
  output ARX_D0_3;
  output ARX_D0_2;
  output ARX_D0_1;
  output ARX_D0_0;
  output ARX_D1_39;
  output ARX_D1_38;
  output ARX_D1_37;
  output ARX_D1_36;
  output ARX_D1_35;
  output ARX_D1_34;
  output ARX_D1_33;
  output ARX_D1_32;
  output ARX_D1_31;
  output ARX_D1_30;
  output ARX_D1_29;
  output ARX_D1_28;
  output ARX_D1_27;
  output ARX_D1_26;
  output ARX_D1_25;
  output ARX_D1_24;
  output ARX_D1_23;
  output ARX_D1_22;
  output ARX_D1_21;
  output ARX_D1_20;
  output ARX_D1_19;
  output ARX_D1_18;
  output ARX_D1_17;
  output ARX_D1_16;
  output ARX_D1_15;
  output ARX_D1_14;
  output ARX_D1_13;
  output ARX_D1_12;
  output ARX_D1_11;
  output ARX_D1_10;
  output ARX_D1_9;
  output ARX_D1_8;
  output ARX_D1_7;
  output ARX_D1_6;
  output ARX_D1_5;
  output ARX_D1_4;
  output ARX_D1_3;
  output ARX_D1_2;
  output ARX_D1_1;
  output ARX_D1_0;
  output ARX_D2_39;
  output ARX_D2_38;
  output ARX_D2_37;
  output ARX_D2_36;
  output ARX_D2_35;
  output ARX_D2_34;
  output ARX_D2_33;
  output ARX_D2_32;
  output ARX_D2_31;
  output ARX_D2_30;
  output ARX_D2_29;
  output ARX_D2_28;
  output ARX_D2_27;
  output ARX_D2_26;
  output ARX_D2_25;
  output ARX_D2_24;
  output ARX_D2_23;
  output ARX_D2_22;
  output ARX_D2_21;
  output ARX_D2_20;
  output ARX_D2_19;
  output ARX_D2_18;
  output ARX_D2_17;
  output ARX_D2_16;
  output ARX_D2_15;
  output ARX_D2_14;
  output ARX_D2_13;
  output ARX_D2_12;
  output ARX_D2_11;
  output ARX_D2_10;
  output ARX_D2_9;
  output ARX_D2_8;
  output ARX_D2_7;
  output ARX_D2_6;
  output ARX_D2_5;
  output ARX_D2_4;
  output ARX_D2_3;
  output ARX_D2_2;
  output ARX_D2_1;
  output ARX_D2_0;
  output ARX_D3_39;
  output ARX_D3_38;
  output ARX_D3_37;
  output ARX_D3_36;
  output ARX_D3_35;
  output ARX_D3_34;
  output ARX_D3_33;
  output ARX_D3_32;
  output ARX_D3_31;
  output ARX_D3_30;
  output ARX_D3_29;
  output ARX_D3_28;
  output ARX_D3_27;
  output ARX_D3_26;
  output ARX_D3_25;
  output ARX_D3_24;
  output ARX_D3_23;
  output ARX_D3_22;
  output ARX_D3_21;
  output ARX_D3_20;
  output ARX_D3_19;
  output ARX_D3_18;
  output ARX_D3_17;
  output ARX_D3_16;
  output ARX_D3_15;
  output ARX_D3_14;
  output ARX_D3_13;
  output ARX_D3_12;
  output ARX_D3_11;
  output ARX_D3_10;
  output ARX_D3_9;
  output ARX_D3_8;
  output ARX_D3_7;
  output ARX_D3_6;
  output ARX_D3_5;
  output ARX_D3_4;
  output ARX_D3_3;
  output ARX_D3_2;
  output ARX_D3_1;
  output ARX_D3_0;
  output ARX_FIFO_EMPTY0;
  output ARX_FIFO_EMPTY1;
  output ARX_FIFO_EMPTY2;
  output ARX_FIFO_EMPTY3;
  output ASB_EN_SLI;
  output ASB_IRQ_SLI;
  output ATCTLN;
  output ATCTLP;
  output ATDAT0N;
  output ATDAT0P;
  output ATDAT10N;
  output ATDAT10P;
  output ATDAT11N;
  output ATDAT11P;
  output ATDAT12N;
  output ATDAT12P;
  output ATDAT13N;
  output ATDAT13P;
  output ATDAT14N;
  output ATDAT14P;
  output ATDAT15N;
  output ATDAT15P;
  output ATDAT1N;
  output ATDAT1P;
  output ATDAT2N;
  output ATDAT2P;
  output ATDAT3N;
  output ATDAT3P;
  output ATDAT4N;
  output ATDAT4P;
  output ATDAT5N;
  output ATDAT5P;
  output ATDAT6N;
  output ATDAT6P;
  output ATDAT7N;
  output ATDAT7P;
  output ATDAT8N;
  output ATDAT8P;
  output ATDAT9N;
  output ATDAT9P;
  output ATDCLKN;
  output ATDCLKP;
  output ATREFCLK_F;
  output ATX_FIFO_FULL0;
  output ATX_FIFO_FULL1;
  output ATX_FIFO_FULL2;
  output ATX_FIFO_FULL3;
  output ATX_PORTID_7;
  output ATX_PORTID_6;
  output ATX_PORTID_5;
  output ATX_PORTID_4;
  output ATX_PORTID_3;
  output ATX_PORTID_2;
  output ATX_PORTID_1;
  output ATX_PORTID_0;
  output ATX_STAT_1;
  output ATX_STAT_0;
  output BBURST_VAL_3;
  output BBURST_VAL_2;
  output BBURST_VAL_1;
  output BBURST_VAL_0;
  output BRLSCLK_F;
  output BRSCLKN;
  output BRSCLKP;
  output BRSTAT0N;
  output BRSTAT0P;
  output BRSTAT1N;
  output BRSTAT1P;
  output BRX_D0_MRWDA_39;
  output BRX_D0_MRWDA_38;
  output BRX_D0_MRWDA_37;
  output BRX_D0_MRWDA_36;
  output BRX_D0_MRWDA_35;
  output BRX_D0_MRWDA_34;
  output BRX_D0_MRWDA_33;
  output BRX_D0_MRWDA_32;
  output BRX_D0_MRWDA_31;
  output BRX_D0_MRWDA_30;
  output BRX_D0_MRWDA_29;
  output BRX_D0_MRWDA_28;
  output BRX_D0_MRWDA_27;
  output BRX_D0_MRWDA_26;
  output BRX_D0_MRWDA_25;
  output BRX_D0_MRWDA_24;
  output BRX_D0_MRWDA_23;
  output BRX_D0_MRWDA_22;
  output BRX_D0_MRWDA_21;
  output BRX_D0_MRWDA_20;
  output BRX_D0_MRWDA_19;
  output BRX_D0_MRWDA_18;
  output BRX_D0_MRWDA_17;
  output BRX_D0_MRWDA_16;
  output BRX_D0_MRWDA_15;
  output BRX_D0_MRWDA_14;
  output BRX_D0_MRWDA_13;
  output BRX_D0_MRWDA_12;
  output BRX_D0_MRWDA_11;
  output BRX_D0_MRWDA_10;
  output BRX_D0_MRWDA_9;
  output BRX_D0_MRWDA_8;
  output BRX_D0_MRWDA_7;
  output BRX_D0_MRWDA_6;
  output BRX_D0_MRWDA_5;
  output BRX_D0_MRWDA_4;
  output BRX_D0_MRWDA_3;
  output BRX_D0_MRWDA_2;
  output BRX_D0_MRWDA_1;
  output BRX_D0_MRWDA_0;
  output BRX_D1_MRWDB_39;
  output BRX_D1_MRWDB_38;
  output BRX_D1_MRWDB_37;
  output BRX_D1_MRWDB_36;
  output BRX_D1_MRWDB_35;
  output BRX_D1_MRWDB_34;
  output BRX_D1_MRWDB_33;
  output BRX_D1_MRWDB_32;
  output BRX_D1_MRWDB_31;
  output BRX_D1_MRWDB_30;
  output BRX_D1_MRWDB_29;
  output BRX_D1_MRWDB_28;
  output BRX_D1_MRWDB_27;
  output BRX_D1_MRWDB_26;
  output BRX_D1_MRWDB_25;
  output BRX_D1_MRWDB_24;
  output BRX_D1_MRWDB_23;
  output BRX_D1_MRWDB_22;
  output BRX_D1_MRWDB_21;
  output BRX_D1_MRWDB_20;
  output BRX_D1_MRWDB_19;
  output BRX_D1_MRWDB_18;
  output BRX_D1_MRWDB_17;
  output BRX_D1_MRWDB_16;
  output BRX_D1_MRWDB_15;
  output BRX_D1_MRWDB_14;
  output BRX_D1_MRWDB_13;
  output BRX_D1_MRWDB_12;
  output BRX_D1_MRWDB_11;
  output BRX_D1_MRWDB_10;
  output BRX_D1_MRWDB_9;
  output BRX_D1_MRWDB_8;
  output BRX_D1_MRWDB_7;
  output BRX_D1_MRWDB_6;
  output BRX_D1_MRWDB_5;
  output BRX_D1_MRWDB_4;
  output BRX_D1_MRWDB_3;
  output BRX_D1_MRWDB_2;
  output BRX_D1_MRWDB_1;
  output BRX_D1_MRWDB_0;
  output BRX_D2_MRWDC_39;
  output BRX_D2_MRWDC_38;
  output BRX_D2_MRWDC_37;
  output BRX_D2_MRWDC_36;
  output BRX_D2_MRWDC_35;
  output BRX_D2_MRWDC_34;
  output BRX_D2_MRWDC_33;
  output BRX_D2_MRWDC_32;
  output BRX_D2_MRWDC_31;
  output BRX_D2_MRWDC_30;
  output BRX_D2_MRWDC_29;
  output BRX_D2_MRWDC_28;
  output BRX_D2_MRWDC_27;
  output BRX_D2_MRWDC_26;
  output BRX_D2_MRWDC_25;
  output BRX_D2_MRWDC_24;
  output BRX_D2_MRWDC_23;
  output BRX_D2_MRWDC_22;
  output BRX_D2_MRWDC_21;
  output BRX_D2_MRWDC_20;
  output BRX_D2_MRWDC_19;
  output BRX_D2_MRWDC_18;
  output BRX_D2_MRWDC_17;
  output BRX_D2_MRWDC_16;
  output BRX_D2_MRWDC_15;
  output BRX_D2_MRWDC_14;
  output BRX_D2_MRWDC_13;
  output BRX_D2_MRWDC_12;
  output BRX_D2_MRWDC_11;
  output BRX_D2_MRWDC_10;
  output BRX_D2_MRWDC_9;
  output BRX_D2_MRWDC_8;
  output BRX_D2_MRWDC_7;
  output BRX_D2_MRWDC_6;
  output BRX_D2_MRWDC_5;
  output BRX_D2_MRWDC_4;
  output BRX_D2_MRWDC_3;
  output BRX_D2_MRWDC_2;
  output BRX_D2_MRWDC_1;
  output BRX_D2_MRWDC_0;
  output BRX_D3_MRWDD_39;
  output BRX_D3_MRWDD_38;
  output BRX_D3_MRWDD_37;
  output BRX_D3_MRWDD_36;
  output BRX_D3_MRWDD_35;
  output BRX_D3_MRWDD_34;
  output BRX_D3_MRWDD_33;
  output BRX_D3_MRWDD_32;
  output BRX_D3_MRWDD_31;
  output BRX_D3_MRWDD_30;
  output BRX_D3_MRWDD_29;
  output BRX_D3_MRWDD_28;
  output BRX_D3_MRWDD_27;
  output BRX_D3_MRWDD_26;
  output BRX_D3_MRWDD_25;
  output BRX_D3_MRWDD_24;
  output BRX_D3_MRWDD_23;
  output BRX_D3_MRWDD_22;
  output BRX_D3_MRWDD_21;
  output BRX_D3_MRWDD_20;
  output BRX_D3_MRWDD_19;
  output BRX_D3_MRWDD_18;
  output BRX_D3_MRWDD_17;
  output BRX_D3_MRWDD_16;
  output BRX_D3_MRWDD_15;
  output BRX_D3_MRWDD_14;
  output BRX_D3_MRWDD_13;
  output BRX_D3_MRWDD_12;
  output BRX_D3_MRWDD_11;
  output BRX_D3_MRWDD_10;
  output BRX_D3_MRWDD_9;
  output BRX_D3_MRWDD_8;
  output BRX_D3_MRWDD_7;
  output BRX_D3_MRWDD_6;
  output BRX_D3_MRWDD_5;
  output BRX_D3_MRWDD_4;
  output BRX_D3_MRWDD_3;
  output BRX_D3_MRWDD_2;
  output BRX_D3_MRWDD_1;
  output BRX_D3_MRWDD_0;
  output BRX_FIFO_EMPTY0;
  output BRX_FIFO_EMPTY1;
  output BRX_FIFO_EMPTY2;
  output BRX_FIFO_EMPTY3;
  output BS_CPTBSR_OUT;
  output BS_MD_OUT;
  output BS_SHBSRN_OUT;
  output BS_TRESET_OUT;
  output BS_UPDTBSR_OUT;
  output BTCTLN;
  output BTCTLP;
  output BTDAT0N;
  output BTDAT0P;
  output BTDAT10N;
  output BTDAT10P;
  output BTDAT11N;
  output BTDAT11P;
  output BTDAT12N;
  output BTDAT12P;
  output BTDAT13N;
  output BTDAT13P;
  output BTDAT14N;
  output BTDAT14P;
  output BTDAT15N;
  output BTDAT15P;
  output BTDAT1N;
  output BTDAT1P;
  output BTDAT2N;
  output BTDAT2P;
  output BTDAT3N;
  output BTDAT3P;
  output BTDAT4N;
  output BTDAT4P;
  output BTDAT5N;
  output BTDAT5P;
  output BTDAT6N;
  output BTDAT6P;
  output BTDAT7N;
  output BTDAT7P;
  output BTDAT8N;
  output BTDAT8P;
  output BTDAT9N;
  output BTDAT9P;
  output BTDCLKN;
  output BTDCLKP;
  output BTREFCLK_F;
  output BTX_FIFO_FULL0;
  output BTX_FIFO_FULL1;
  output BTX_FIFO_FULL2;
  output BTX_FIFO_FULL3;
  output BTX_PORTID_7;
  output BTX_PORTID_6;
  output BTX_PORTID_5;
  output BTX_PORTID_4;
  output BTX_PORTID_3;
  output BTX_PORTID_2;
  output BTX_PORTID_1;
  output BTX_PORTID_0;
  output BTX_STAT_1;
  output BTX_STAT_0;
  output HDOUTN_A;
  output HDOUTN_B;
  output HDOUTN_C;
  output HDOUTN_D;
  output HDOUTP_A;
  output HDOUTP_B;
  output HDOUTP_C;
  output HDOUTP_D;
  output HRDATA_35;
  output HRDATA_34;
  output HRDATA_33;
  output HRDATA_32;
  output HRDATA_31;
  output HRDATA_30;
  output HRDATA_29;
  output HRDATA_28;
  output HRDATA_27;
  output HRDATA_26;
  output HRDATA_25;
  output HRDATA_24;
  output HRDATA_23;
  output HRDATA_22;
  output HRDATA_21;
  output HRDATA_20;
  output HRDATA_19;
  output HRDATA_18;
  output HRDATA_17;
  output HRDATA_16;
  output HRDATA_15;
  output HRDATA_14;
  output HRDATA_13;
  output HRDATA_12;
  output HRDATA_11;
  output HRDATA_10;
  output HRDATA_9;
  output HRDATA_8;
  output HRDATA_7;
  output HRDATA_6;
  output HRDATA_5;
  output HRDATA_4;
  output HRDATA_3;
  output HRDATA_2;
  output HRDATA_1;
  output HRDATA_0;
  output HREADY_OUT;
  output HRESP_1;
  output HRESP_0;
  output MC_RD_71;
  output MC_RD_70;
  output MC_RD_69;
  output MC_RD_68;
  output MC_RD_67;
  output MC_RD_66;
  output MC_RD_65;
  output MC_RD_64;
  output MC_RD_63;
  output MC_RD_62;
  output MC_RD_61;
  output MC_RD_60;
  output MC_RD_59;
  output MC_RD_58;
  output MC_RD_57;
  output MC_RD_56;
  output MC_RD_55;
  output MC_RD_54;
  output MC_RD_53;
  output MC_RD_52;
  output MC_RD_51;
  output MC_RD_50;
  output MC_RD_49;
  output MC_RD_48;
  output MC_RD_47;
  output MC_RD_46;
  output MC_RD_45;
  output MC_RD_44;
  output MC_RD_43;
  output MC_RD_42;
  output MC_RD_41;
  output MC_RD_40;
  output MC_RD_39;
  output MC_RD_38;
  output MC_RD_37;
  output MC_RD_36;
  output MC_RD_35;
  output MC_RD_34;
  output MC_RD_33;
  output MC_RD_32;
  output MC_RD_31;
  output MC_RD_30;
  output MC_RD_29;
  output MC_RD_28;
  output MC_RD_27;
  output MC_RD_26;
  output MC_RD_25;
  output MC_RD_24;
  output MC_RD_23;
  output MC_RD_22;
  output MC_RD_21;
  output MC_RD_20;
  output MC_RD_19;
  output MC_RD_18;
  output MC_RD_17;
  output MC_RD_16;
  output MC_RD_15;
  output MC_RD_14;
  output MC_RD_13;
  output MC_RD_12;
  output MC_RD_11;
  output MC_RD_10;
  output MC_RD_9;
  output MC_RD_8;
  output MC_RD_7;
  output MC_RD_6;
  output MC_RD_5;
  output MC_RD_4;
  output MC_RD_3;
  output MC_RD_2;
  output MC_RD_1;
  output MC_RD_0;
  output MC_RDFIFO_EMPTY;
  output MC_RIFIFO_FULL;
  output MC_SYSCLK;
  output MC_WDFIFO_FULL;
  output MC_WIFIFO_FULL;
  output RCK78;
  output REXT;
  output REXTN;
  output RSCLKA;
  output RSCLKB;
  output RSTAT0A;
  output RSTAT0B;
  output RSTAT1A;
  output RSTAT1B;
  output RWCKA;
  output RWCKB;
  output RWCKC;
  output RWCKD;
  output SO_TOFPGA;
  output TCK78;
  output TCKI_OUT;
  output TIE_HI;
  output TIE_LO;
  inout MCREFCLK;
  inout	PMIA0;
  inout	PMIA1;
  inout PMIA10;
  inout PMIA11;
  inout PMIA12;
  inout PMIA13;
  inout PMIA14;
  inout PMIA15;
  inout PMIA16;
  inout PMIA17;
  inout PMIA2;
  inout PMIA3;
  inout PMIA4;
  inout PMIA5;
  inout PMIA6;
  inout PMIA7;
  inout PMIA8;
  inout PMIA9;
  inout PMIC;
  inout PMICN;
  inout PMID0;
  inout PMID1;
  inout PMID10;
  inout PMID11;
  inout PMID12;
  inout PMID13;
  inout PMID14;
  inout PMID15;
  inout PMID16;
  inout PMID17;
  inout PMID18;
  inout PMID19;
  inout PMID2;
  inout PMID20;
  inout PMID21;
  inout PMID22;
  inout PMID23;
  inout PMID24;
  inout PMID25;
  inout PMID26;
  inout PMID27;
  inout PMID28;
  inout PMID29;
  inout PMID3;
  inout PMID30;
  inout PMID31;
  inout PMID32;
  inout PMID33;
  inout PMID34;
  inout PMID35;
  inout PMID4;
  inout PMID5;
  inout PMID6;
  inout PMID7;
  inout PMID8;
  inout PMID9;
  inout PMIK;
  inout PMIKN;
  inout  PMIQ0;
  inout  PMIQ1;
  inout  PMIQ10;
  inout  PMIQ11;
  inout  PMIQ12;
  inout  PMIQ13;
  inout  PMIQ14;
  inout  PMIQ15;
  inout  PMIQ16;
  inout  PMIQ17;
  inout  PMIQ18;
  inout  PMIQ19;
  inout  PMIQ2;
  inout  PMIQ20;
  inout  PMIQ21;
  inout  PMIQ22;
  inout  PMIQ23;
  inout  PMIQ24;
  inout  PMIQ25;
  inout  PMIQ26;
  inout  PMIQ27;
  inout  PMIQ28;
  inout  PMIQ29;
  inout  PMIQ3;
  inout  PMIQ30;
  inout  PMIQ31;
  inout  PMIQ32;
  inout  PMIQ33;
  inout  PMIQ34;
  inout  PMIQ35;
  inout  PMIQ4;
  inout  PMIQ5;
  inout  PMIQ6;
  inout  PMIQ7;
  inout  PMIQ8;
  inout  PMIQ9;
  inout  PMIRN;
  inout  PMIWN;

endmodule

