set hdl_input_location {../../source/top}
analyze -format verilog -work work ../../source/exemplar/orca4_leonardo.v
analyze -format verilog -work work ../../source/top/qspi3_define.v
analyze -format verilog -work work ../../source/exemplar/rfclk_pll_ph_bo.v
analyze -format verilog -work work ../../source/exemplar/rfclk_hpll_ph_bo.v
analyze -format verilog -work work ../../source/exemplar/sysbus_fpsc.v
analyze -format verilog -work work ../../source/exemplar/mycore.v
analyze -format verilog -work work ../../source/top/spi_324p_o4_1_001.v
analyze -format verilog -work work ../../source/top/orspi.v
