///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor
// Corporation.
// The entire notice above must be reproduced on all authorized
// copies and copies may only be made to the extent permitted
// by a licensing agreement from Lattice Semiconductor Corporation.
//

// ====================================================================
// File Details
// ====================================================================
// Project              :       ORSPII
// Filename             :       reg_desc.v
// Author               :       Rob Proudlock, rproudlo@latticesemi.com
// Created on           :       Wednesday 10th July 2002
// Last Modified By     :       $Author: bkerr $
// Last Modified On     :       $Date: Thu Nov 21 09:20:18 2002 $ 
// Revision             :       $Revision: 1.12 $
// Status               :       Development
// Dependencies         :       None
//=====================================================================

//=====================================================================
// Description          :
//=====================================================================
// This module lists the register declarations for the control registers
//
//
//=====================================================================

//=====================================================================
// Revision History
//=====================================================================
// $Log: reg_desc.v.rca $
// 
//  Revision: 1.12 Thu Nov 21 09:20:18 2002 bkerr
//  Added LOOPBACK_FE register bit introduced in top8 release
// 
//  Revision: 1.11 Thu Oct 31 11:03:06 2002 rproudlo
//  Modified BurstVal to be random
// 
//  Revision: 1.10 Thu Oct 24 11:54:22 2002 rproudlo
//  Added new register bits.
// 
//  Revision: 1.9 Tue Oct  8 08:49:07 2002 rproudlo
//  Added RX_EXT_STAT_EN
// 
//  Revision: 1.8 Tue Oct  1 05:00:45 2002 rproudlo
//  Added MAX_BURST1/2_RX
// 
//  Revision: 1.7 Fri Sep 13 11:52:57 2002 rproudlo
//  Reduced TX_PDM_BVAL to 4 bits from 5
// 
//  Revision: 1.6 Thu Sep 12 10:29:07 2002 rproudlo
//  Reworked for new register map
// 
//  Revision: 1.5 Tue Sep 10 09:20:52 2002 bkerr
//  Re-declared TX_PDM_ACTIVE_PORTS and RX_PDM_ACTIVE_PORTS variables as
//  integers to allow 256 ports to be specified
// 
//  Revision: 1.4 Fri Aug 23 08:15:31 2002 bkerr
//  Uncommented and resized FIFO_THRESHOLD_H_TX as this is required by tx_path
// 
//  Revision: 1.3 Thu Aug 15 09:49:44 2002 rproudlo
//  Updated after initial verification
// 
//  Revision: 1.2 Wed Jul 10 11:34:53 2002 rproudlo
//  Fixed typo
// 
//  Revision: 1.1 Wed Jul 10 11:17:24 2002 rproudlo
//  Initial Creation
// 
// 
//=====================================================================

reg [7:0] CALENDAR_M_RX;
reg [9:0] CALENDAR_LEN_RX;

reg [7:0] CALENDAR_M_RX_SHDW;
reg [9:0] CALENDAR_LEN_RX_SHDW;

reg       CALENDAR_SW_EN_RX;
reg       CALENDAR_SW_SEL_RX;

reg [7:0] CALENDAR_M_TX;
reg [9:0] CALENDAR_LEN_TX;

reg [7:0] CALENDAR_M_TX_SHDW;
reg [9:0] CALENDAR_LEN_TX_SHDW;

reg       CALENDAR_SW_EN_TX;

reg       TX_BURST_TERMINATION;

reg [7:0] FIFO_THRESHOLD_H_RX;
reg [4:0] FIFO_THRESHOLD_H_TX;

reg [9:0] MAX_BURST1; 
reg [9:0] MAX_BURST2; 

reg [9:0] MAX_BURST1_RX;
reg [9:0] MAX_BURST2_RX;

reg       DISABLE_STATUS;
reg       MASK_DIP4;
reg [2:0] LOSS_SYNC;
reg       EN_TRAINING;
reg       EN_BASELINE;

reg [2:0] DIP2_ERR_TH;

reg [31:0] DATA_MAX_T;
reg [15:0] ALPHA;

reg       RDI_PLL_LOL_INT_EN;
reg       RDI_BAS_DONE_INT_EN;
reg       RDI_BAS_ERR_INT_EN;
reg       RDI_DSKW_DONE_INT_EN;
reg       RDI_DSKW_ERR_INT_EN;
reg       RDI_TRN_DET_INT_EN;
reg       ALGN_OFF_INT_EN;
reg       TX_STATUS_LOF_INT_EN;

reg [7:0] RDI_INT_EN;

reg       ILLEGAL_CTL_EN;
reg       RX_SOP_ALIGN_ERR_INT_EN;
reg       TX_SOP_ALIGN_ERR_INT_EN;
reg       DIP4_ERR_INT_EN;
reg       DIP2_ERR_INT_EN;
reg       ASYNC_FIFO_RX_OVRRUN_INT_EN;

reg [5:0] SOP_DIP_ASF_INT_EN;
  

reg       DPRAM_0_RXFIFO_OVERRUN_INT_EN;
reg       DPRAM_1_RXFIFO_OVERRUN_INT_EN;
reg       DPRAM_2_RXFIFO_OVERRUN_INT_EN;
reg       DPRAM_3_RXFIFO_OVERRUN_INT_EN;

//TX FIFO Overrun Interrupt Enables


reg  DPRAM_0_TXFIFO_OVERRUN_INT_EN;
reg  DPRAM_1_TXFIFO_OVERRUN_INT_EN;
reg  DPRAM_2_TXFIFO_OVERRUN_INT_EN;
reg  DPRAM_3_TXFIFO_OVERRUN_INT_EN;

//RX FIFO Underrun Interrupt Enables

reg  DPRAM_0_RXFIFO_URRUN_INT_EN;
reg  DPRAM_1_RXFIFO_URRUN_INT_EN;
reg  DPRAM_2_RXFIFO_URRUN_INT_EN;
reg  DPRAM_3_RXFIFO_URRUN_INT_EN;

//

reg [7:0] DPRAM_RX_FIFO_OVER_UR_RUN_INT_EN;
reg [7:0] DPRAM_TX_FIFO_OVER_UR_RUN_INT_EN;

//TX FIFO Underrun Interrupt Enables

reg  DPRAM_0_TXFIFO_URRUN_INT_EN;
reg  DPRAM_1_TXFIFO_URRUN_INT_EN;
reg  DPRAM_2_TXFIFO_URRUN_INT_EN;
reg  DPRAM_3_TXFIFO_URRUN_INT_EN;

reg [1:0] RX_DPRAM_0_PART_SIZE;
reg [1:0] RX_DPRAM_1_PART_SIZE;
reg [1:0] RX_DPRAM_2_PART_SIZE;
reg [1:0] RX_DPRAM_3_PART_SIZE;

reg [7:0] RX_DPRAM_PART_SIZE;

reg [1:0] RX_DPRAM_0_AGGR_MODE;
reg [1:0] RX_DPRAM_1_AGGR_MODE;
reg [1:0] RX_DPRAM_2_AGGR_MODE;
reg [1:0] RX_DPRAM_3_AGGR_MODE;

reg [7:0] RX_DPRAM_AGGR_MODE;

reg [1:0] TX_DPRAM_0_PART_SIZE;
reg [1:0] TX_DPRAM_1_PART_SIZE;
reg [1:0] TX_DPRAM_2_PART_SIZE;
reg [1:0] TX_DPRAM_3_PART_SIZE;

reg [7:0] TX_DPRAM_PART_SIZE;

reg [1:0] TX_DPRAM_0_AGGR_MODE;
reg [1:0] TX_DPRAM_1_AGGR_MODE;
reg [1:0] TX_DPRAM_2_AGGR_MODE;
reg [1:0] TX_DPRAM_3_AGGR_MODE;

reg [7:0] TX_DPRAM_AGGR_MODE;

reg       TX_DPRAM_0_FULL_TYPE_SEL;
reg       TX_DPRAM_1_FULL_TYPE_SEL;
reg       TX_DPRAM_2_FULL_TYPE_SEL;
reg       TX_DPRAM_3_FULL_TYPE_SEL;

reg       RX_DPRAM_0_EMPTY_TYPE_SEL;
reg       RX_DPRAM_1_EMPTY_TYPE_SEL;
reg       RX_DPRAM_2_EMPTY_TYPE_SEL;
reg       RX_DPRAM_3_EMPTY_TYPE_SEL;

reg [7:0] DPRAM_FULL_EMPTY_SEL;

reg       LOOPBACK_FE;
reg       LOW_SPEED_DATA_SEL;
reg       STATUS_IO_SEL;
reg       LOOPBACK_HS;
reg       LOOPBACK_LS;
reg       FORCE_DIP4_ERR;
reg       FORCE_DIP2_ERR;

reg [6:0] LS_STIO_LB_FERR;
		   
//
//Memory Registers
//

reg [17:0] MEMORY_BASE_ADDR;

reg [7:0] TX_MAIN_CAL_SEQ   [0:1023];
reg [7:0] TX_SHADOW_CAL_SEQ [0:1023];

reg [7:0] RX_MAIN_CAL_SEQ   [0:1023];
reg [7:0] RX_SHADOW_CAL_SEQ [0:1023];

integer   TX_PDM_ACTIVE_PORTS;

reg [7:0] TX_PDM_ACTIVE_PORT_ID [0:255];

reg       TX_PDM_MBEN    [0:255];
reg       TX_PDM_M_BIT   [0:255];
reg [1:0] TX_PDM_BANK_ID [0:255];
reg [2:0] TX_PDM_PA      [0:255];
reg [3:0] TX_PDM_BVAL    [0:255];
reg [7:0] TX_PDM_PORT_ID [0:255];

integer   RX_PDM_ACTIVE_PORTS;

reg [7:0] RX_PDM_ACTIVE_PORT_ID [0:255];

reg [1:0] RX_PDM_BANK_ID [0:255];
reg [2:0] RX_PDM_PA      [0:255];

//
//
//

reg       RX_EXT_STAT_EN;

reg [3:0] PDM_BVAL;
