///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor
// Corporation.
// The entire notice above must be reproduced on all authorized
// copies and copies may only be made to the extent permitted
// by a licensing agreement from Lattice Semiconductor Corporation.
//

// ====================================================================
// File Details
// ====================================================================
// Project              :       ORSPII
// Filename             :       header.v
// Author               :       Ben_Kerr,bkerr@latticesemi.com
// Created on           :       Tuesday July 09 2002 (WW27)
// Last Modified By     :       $Author: bkerr $
// Last Modified On     :       $Date: Fri Jan  3 04:17:44 2003 $
// Revision             :       $Revision: 1.46 $
// Status               :       Development
// Dependencies         :       reg_desc.v, addr_params.v
//=====================================================================

//=====================================================================
// Description          :
//=====================================================================
// Header file used at the top of the automatically created toptest.v
//
// After running the simany_ph1 script, toptest.v is created
// This file is built from the following files:
//
//   +-----------------------------------+
//   | `defines generated by script      |  Time of day, user information & configuration feedback
//   +-----------------------------------+
//   |                                   |  top level module statement, global variables
//   |        header.v (this file)       |  module instantiations, clock & reset generation
//   |                                   |  initial ....
//   +-----------------------------------+
//   |                                   |    DUT register settings (configuration specific)
//   |     SFnn - from command line      |
//   |                                   |
//   +-----------------------------------+
//   |                                   |    DUT memory configurations (configuration specific)
//   |     Mnn - from command line       |
//   |                                   |
//   +-----------------------------------+
//   |                                   |    Task calls to configure DUT
//   |             body.v                |    Task calls to enable checkers
//   |                                   |    Task calls to perform data format tests
//   +-----------------------------------+
//   |                                   |    Report pass/fail
//   |            footer.v               |    `include common tasks
//   |                                   |  endmodule
//   +-----------------------------------+
//
//
//=====================================================================

//=====================================================================
// Revision History
//=====================================================================
// $Log: header.v.rca $
// 
//  Revision: 1.46 Fri Jan  3 04:17:44 2003 bkerr
//  Removed forces on MACLOG AR nets due to new MACLOG models
//  Added ANNOTATE `define to run SDF back-annotation
// 
//  Revision: 1.45 Tue Dec 17 13:22:48 2002 bkerr
//  Altered 2nd reset to only reset SPI4 and not do a full hard-reset
// 
//  Revision: 1.44 Fri Dec 13 11:03:16 2002 bkerr
//  Added pulldowns onto Rx_RE and Rx_A to prevent X's
//  Forced a default RX_DPRAM aggregation mode (32-bit) to prevent X's
// 
//  Revision: 1.43 Thu Dec 12 11:48:36 2002 bkerr
//  Changed TRI_IO input to 1'b1
// 
//  Revision: 1.42 Thu Dec 12 06:26:19 2002 bkerr
//  Added double reset for gate-level simulation
//  Added RAM pre-load for gate-level simulation
// 
//  Revision: 1.41 Thu Nov 21 06:33:58 2002 bkerr
//  Added new SPI_DATM and SPI_DLYTAP inputs introduced in top8 release
// 
//  Revision: 1.40 Mon Nov 11 06:10:57 2002 bkerr
//  Changed heirarchical reference to MEM_TXPDMx_INIT_DONE to
//  maintain compatibility with gate-level netlist
// 
//  Revision: 1.39 Mon Oct 21 05:10:28 2002 bkerr
//  Reduced simulation lockup timebomb to 1 second
// 
//  Revision: 1.38 Thu Oct 17 07:56:50 2002 bkerr
//  Added BS_TRESET_OUT and BS_TRESET that were incorrectly removed
// 
//  Revision: 1.37 Thu Oct 17 04:18:05 2002 bkerr
//  Modified orspii_asb instantiation for top5 I/O changes
// 
//  Revision: 1.36 Tue Oct 15 11:44:01 2002 bkerr
//  Removed force's driving HSIX and used testio_mux to get the HSIX into
//  bypass mode
// 
//  Revision: 1.35 Fri Oct 11 09:50:53 2002 bkerr
//  Disabled testio_mux and used force's to get SPI4HSIX operating in
//  bypass mode
// 
//  Revision: 1.34 Thu Oct 10 04:38:28 2002 bkerr
//  Connected up additional I/O
// 
//  Revision: 1.33 Thu Sep 26 07:09:26 2002 rproudlo
//  Added missing reg declaration
// 
//  Revision: 1.32 Thu Sep 26 06:21:51 2002 rproudlo
//  Added very basic ISR
// 
//  Revision: 1.31 Tue Sep 24 03:38:24 2002 rproudlo
//  Added FIFO_Full flow-control to fpga_bfm_rx
// 
//  Revision: 1.30 Mon Sep 23 06:44:27 2002 bkerr
//  Checked out due to neptune downtime  Added multiplexed testio connections to allow HSIX forces to be
//  removed when the I/O buffers are added to orspii_asb top-level
// 
//  Revision: 1.29 Tue Sep 17 05:33:10 2002 bkerr
//  Added 5 second simulation lock-up abort
// 
//  Revision: 1.28 Mon Sep 16 09:50:52 2002 bkerr
//  Fixed connection to HWDATA to remove warnings with NCVerilog
// 
//  Revision: 1.27 Mon Sep 16 06:54:14 2002 rproudlo
//  fixed wiring mistake on RDAT[12]
// 
//  Revision: 1.26 Mon Sep 16 05:54:49 2002 rproudlo
//  Un-connected LVDS STAT lines
// 
//  Revision: 1.25 Mon Sep 16 05:38:05 2002 rproudlo
//  DebuggingInitial testing
// 
//  Revision: 1.24 Mon Sep 16 05:05:23 2002 bkerr
//  Added force statements to get the HSIX model operating in PLL
//  bypass mode
// 
//  Revision: 1.23 Mon Sep 16 04:59:10 2002 rproudlo
//  Wired-up a number of "inputs" in attempt to progress testing
// 
//  Revision: 1.22 Mon Sep 16 04:25:29 2002 rproudlo
//  Updated orspii_asb instantiation to match new version
// 
//  Revision: 1.21 Fri Sep 13 09:46:07 2002 bkerr
//  Added call to busmaster set_retry_limit
// 
//  Revision: 1.20 Fri Sep 13 05:38:58 2002 bkerr
//  Instantiated orspii_asb and removed s4_top instantiation
//
//  Revision: 1.19 Wed Sep 11 11:23:24 2002 rproudlo
//  Added loopback Rx->Tx
//
//  Revision: 1.18 Tue Sep 10 09:28:41 2002 bkerr
//  Added variables for use in SF17
//  Removed all rldclk references
//
//  Revision: 1.17 Mon Sep  9 10:06:53 2002 bkerr
//  Corrected memory write interface for programming Rx memories
//
//  Revision: 1.16 Mon Sep  9 09:03:49 2002 bkerr
//  Connected a_rsclk to LatSPI4 instead of using rldclk
//
//  Revision: 1.15 Mon Sep  9 08:57:17 2002 bkerr
//  Added force to connect rstat
//
//  Revision: 1.14 Mon Sep  9 07:31:54 2002 bkerr
//  Replaced tx_path and s4_rx_top instantiations with s4_top
//
//  Revision: 1.13 Mon Sep  9 05:13:09 2002 rproudlo
//  Modifications to wiring of s4_rx_top
//
//  Revision: 1.12 Fri Sep  6 10:00:51 2002 rproudlo
//  Removed redundant ports from s4_rx_top
//
//  Revision: 1.11 Fri Sep  6 08:48:15 2002 bkerr
//  Added tlctl and tldat outputs to tx_path port connections
//
//  Revision: 1.10 Fri Sep  6 05:05:51 2002 rproudlo
//  Added Rx Memory interface
//
//  Revision: 1.9 Fri Sep  6 04:48:44 2002 bkerr
//  Updated tx_path port connections to reflect changes
//  Removed references to tclk
//
//  Revision: 1.8 Fri Sep  6 04:02:15 2002 rproudlo
//  Added s4_rx_top and fpga_bfm_rx modules and wired-up
//
//  Revision: 1.7 Wed Sep  4 05:44:25 2002 bkerr
//  Updated tx_path instantiation to reflect port changes
//  Removed tclk as it is now internally generated
//
//  Revision: 1.6 Fri Aug 23 10:25:51 2002 bkerr
//  Fixed BIST & TX_Dn connections to prevent "Port size mismatch"
//  warnings from simulator
//
//  Revision: 1.5 Fri Aug 23 08:04:22 2002 bkerr
//  Removed orspii_asb instantiation and replaced with tx_path
//  Added clock and reset generation
//  Added wait for reset to complete and wait for DUT to complete
//  initialisation
//
//  Revision: 1.4 Tue Aug 20 12:03:12 2002 bkerr
//  Instantiate the orspii_asb top-level module and connect up the
//  SPI4 "A" connections to the LatSPI4 and fpga BFMs
//  Instantiate the AHB bmaster model to drive the AHB bus
//
//  Revision: 1.3 Tue Jul 30 12:11:31 2002 bkerr
//  Added integer i declaration for use in mnn files
//
//  Revision: 1.2 Thu Jul 11 08:38:47 2002 rproudlo
//  Added port maps for fpga_bfm_rx/tx
//
//  Revision: 1.1 Tue Jul  9 11:59:12 2002 bkerr
//  Initial creation
//=====================================================================

`timescale 1ns/1ps

module toptest;

`include "reg_desc.v"
`include "qspi3_define.v"

parameter ports = `PORTS;

// ---------------------------------------------------------------------------
// Variables
// ---------------------------------------------------------------------------
integer     error_count;      // Number of errors recorded during test

// Configuration variables
integer     i;                // loop variable
reg [255:0] port_used;        // Flags to indicate if a port has been used
reg [  7:0] random_port;      // A randomly selected port number


// Clocks
wire        trefclk;          // Tx reference clock
reg         trefclk_2x;       // 2x trefclk (for SPI4HSIX)
reg   [2:0] trefclk_div;      // Counter to divide trefclk_2x by 8
reg         rfclk;
wire        rfclk_out;

// Reset
reg         dut_reset;        // main DUT reset (active high)
wire        dut_reset_n;      // main DUT reset (active low)
reg         spi4_reset;       // SPI4 reset (active high)
reg         reset_done;       // reset_done indication
reg         sys_resetn;       // FPGA reset
reg         sys_rst_n;        // FPSC ASB reset

reg         FPGA_LB;
reg         test_go;

event       preload_ram;      // trigger to preload RAM in gate-level sim


// Signals from ORSPI_ASB SPI-4 interface to LATSPI4 driver/monitor
wire        a_tdclk;
wire [15:0] a_tdat;
wire        a_tctl;
wire        a_tsclk;
wire [ 1:0] a_tstat;

wire        a_rdclk;
wire [15:0] a_rdat;
wire        a_rctl;
wire        a_rsclk;
wire [ 1:0] a_rstat;


// module processor interface (MPI)
// wire [1:0]  mpi_tsz;
// wire mpi_rw;
// wire mpi_burstn;
// wire mpi_bdipn;
// wire mpi_strbn;
// wire mpi_cs0n;
// wire mpi_cs1;
// wire [17:0] mpi_a;
// tri  [31:0] mpi_d;
// tri  [0:7] mpi_d_temp;
// tri  [3:0] mpi_dp;
// wire mpi_ackn;
// wire mpi_tean;
// wire mpi_irqn;
// wire mpi_retryn;

// reg mpi_clk;

// Signals to orspi_qspi3 device under test

// SPI-3 Interface 0

wire		renb0;
wire		rsx0;
wire		rsop0;
wire		reop0;
wire		rprty0;
wire		rval0;
wire		rerr0;
wire [1:0]	rmod0;
wire [31:0]	rdat0;

wire		tenb0;
wire		tsx0;
wire		tsop0;
wire		teop0;
wire		tprty0;
wire		terr0;
wire [1:0]	tmod0;
wire [31:0]	tdat0;
wire [5:0]	tadr0;
wire [ports-1:0]	dtpa0;

// SPI-3 Interface 1

wire		renb1;
wire		rsx1;
wire		rsop1;
wire		reop1;
wire		rprty1;
wire		rval1;
wire		rerr1;
wire [1:0]	rmod1;
wire [31:0]	rdat1;

wire		tenb1;
wire		tsx1;
wire		tsop1;
wire		teop1;
wire		tprty1;
wire		terr1;
wire [1:0]	tmod1;
wire [31:0]	tdat1;
wire [5:0]	tadr1;
wire [ports-1:0]	dtpa1;

// SPI-3 Interface 2

wire		renb2;
wire		rsx2;
wire		rsop2;
wire		reop2;
wire		rprty2;
wire		rval2;
wire		rerr2;
wire [1:0]	rmod2;
wire [31:0]	rdat2;

wire		tenb2;
wire		tsx2;
wire		tsop2;
wire		teop2;
wire		tprty2;
wire		terr2;
wire [1:0]	tmod2;
wire [31:0]	tdat2;
wire [5:0]	tadr2;
wire [ports-1:0]	dtpa2;

// SPI-3 Interface 3

wire		renb3;
wire		rsx3;
wire		rsop3;
wire		reop3;
wire		rprty3;
wire		rval3;
wire		rerr3;
wire [1:0]	rmod3;
wire [31:0]	rdat3;

wire		tenb3;
wire		tsx3;
wire		tsop3;
wire		teop3;
wire		tprty3;
wire		terr3;
wire [1:0]	tmod3;
wire [31:0]	tdat3;
wire [5:0]	tadr3;
wire [ports-1:0]	dtpa3;


// AHB master
wire        HCLK;
wire        HREADY;
wire  [1:0] HRESP;
wire [35:0] HRDATA;
wire        HWRITE;
wire        HBURST;
wire [ 1:0] HTRANS;
wire [17:0] HADDR;
wire  [1:0] HSIZE;
wire [35:0] HWDATA;

// Memory controller/test_io mux
wire [35:0] PMID;
wire [17:0] PMIA;

wire [35:0] mem_D;
wire [17:0] mem_SA;


reg  [ 1:0] TESTMD;

//Interrupt line
wire        ASB_IRQ_SLI;

// MPI interface signals from bmaster driver
wire   		mpi_clk;
wire [1:0]	mpi_tsz;
wire   		mpi_rdwr_n;
wire   		mpi_burst;
wire   		mpi_bdip;
wire   		mpi_strbn;
wire   		cs0n;
wire   		cs1;
wire [17:0]	mpi_addr;
tri [7:0]	mpi_data;
wire   		mpi_ta;
wire   		mpi_tea;
wire   		mpi_irq;
wire   		mpi_retry;

reg [7:0]   read_reg;
reg [7:0]   rx_pe;
reg [7:0]   rx_pf;
reg [7:0]   tx_pf;

initial
   TESTMD = 2'b00;   // Enable SPI4 testio_mux to get the HSIX into bypass mode


// Test mode multiplexor
assign PMIA[17] =                                  mem_SA[17];
assign PMIA[16] = (TESTMD == 2'b00) ? 1'b0 :       mem_SA[16];    // spi4_sel
assign PMIA[15] =                                  mem_SA[15];
assign PMIA[14] =                                  mem_SA[14];
assign PMIA[13] =                                  mem_SA[13];
assign PMIA[12] = (TESTMD == 2'b00) ? 1'b0 :       mem_SA[12];    // spi4_sel
assign PMIA[11] =                                  mem_SA[11];
assign PMIA[10] = (TESTMD == 2'b00) ? 1'b0 :       mem_SA[10];    // TSTLOOPBK
assign PMIA[ 9] =                                  mem_SA[ 9];
assign PMIA[ 8] =                                  mem_SA[ 8];
assign PMIA[ 7] =                                  mem_SA[ 7];
assign PMIA[ 6] =                                  mem_SA[ 6];
assign PMIA[ 5] =                                  mem_SA[ 5];
assign PMIA[ 4] =                                  mem_SA[ 4];
assign PMIA[ 3] = (TESTMD == 2'b00) ? 1'b1 :       mem_SA[ 3];    // BYPASS
assign PMIA[ 2] =                                  mem_SA[ 2];
assign PMIA[ 1] = (TESTMD == 2'b00) ? dut_reset :  mem_SA[ 1];    // RESETIX
assign PMIA[ 0] =                                  mem_SA[ 0];

assign PMID[35] =                                  mem_D [35];
assign PMID[34] =                                  mem_D [34];
assign PMID[33] =                                  mem_D [33];
assign PMID[32] = (TESTMD == 2'b00) ? 1'b0 :       mem_D [32];    // TSTMODE
assign PMID[31] =                                  mem_D [31];
assign PMID[30] = (TESTMD == 2'b00) ? 1'b0 :       mem_D [30];    // TSTSHFTLD
assign PMID[29] =                                  mem_D [29];
assign PMID[28] =                                  mem_D [28];
assign PMID[27] =                                  mem_D [27];
assign PMID[26] = (TESTMD == 2'b00) ? 1'b0 :       mem_D [26];    // ECSEL
assign PMID[25] =                                  mem_D [25];
assign PMID[24] = (TESTMD == 2'b00) ? 1'b0 :       mem_D [24];    // ECTOGGLE
assign PMID[23] =                                  mem_D [23];
assign PMID[22] = (TESTMD == 2'b00) ? 1'b0 :       mem_D [22];    // EXDNUP
assign PMID[21] =                                  mem_D [21];
assign PMID[20] =                                  mem_D [20];
assign PMID[19] =                                  mem_D [19];
assign PMID[18] = (TESTMD == 2'b00) ? dut_reset :  mem_D [18];    // TESTRST
assign PMID[17] =                                  mem_D [17];
assign PMID[16] =                                  mem_D [16];
assign PMID[15] =                                  mem_D [15];
assign PMID[14] =                                  mem_D [14];
assign PMID[13] =                                  mem_D [13];
assign PMID[12] =                                  mem_D [12];
assign PMID[11] =                                  mem_D [11];
assign PMID[10] =                                  mem_D [10];
assign PMID[ 9] =                                  mem_D [ 9];
assign PMID[ 8] =                                  mem_D [ 8];
assign PMID[ 7] =                                  mem_D [ 7];
assign PMID[ 6] =                                  mem_D [ 6];
assign PMID[ 5] =                                  mem_D [ 5];
assign PMID[ 4] =                                  mem_D [ 4];
assign PMID[ 3] =                                  mem_D [ 3];
assign PMID[ 2] =                                  mem_D [ 2];
assign PMID[ 1] =                                  mem_D [ 1];
assign PMID[ 0] =                                  mem_D [ 0];

// -------------------------------------------------------------------------
// Module instantiations
// -------------------------------------------------------------------------

orspi_qspi3 orspi_qspi3 (


// FPGA external interface io

   .sys_resetn    (sys_resetn),         // system reset (active low)
   .sys_rst_n     (sys_rst_n),         

// ------------------------------------
// SPI-3 INTERFACE NUMBER 0 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   .rfclk0        (rfclk),
   .renb0         (renb0),
   .renb_a0       (renb0),
   .renb_b0       (renb0),
        
   .rsx0          (rsx0),
   .rsop0         (rsop0),
   .reop0         (reop0),
   .rprty0        (rprty0),
   .rval0         (rval0),
   .rerr0         (rerr0),
   .rmod0         (rmod0[1:0]),
   .rdat0         (rdat0[31:0]),
   
   // transmit side I/O
   .tenb0         (tenb0),
   .tdat0         (tdat0[31:0]),
   .tmod0         (tmod0[1:0]),
   .tprty0        (tprty0),
   .tsop0         (tsop0),
   .teop0         (teop0),
   .terr0         (terr0),
   .tsx0          (tsx0),
   .dtpa0         (dtpa0[ports-1:0]),
   .stpa0         (stpa0),
   .ptpa0         (ptpa0),
   .tadr0         (tadr0[5:0]),

// ------------------------------------
// SPI-3 INTERFACE NUMBER 1 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   .rfclk1        (rfclk),
   .renb1         (renb1),
   .renb_a1       (renb1),
   .renb_b1       (renb1),
        
   .rsx1          (rsx1),
   .rsop1         (rsop1),
   .reop1         (reop1),
   .rprty1        (rprty1),
   .rval1         (rval1),
   .rerr1         (rerr1),
   .rmod1         (rmod1[1:0]),
   .rdat1         (rdat1[31:0]),
   
   // transmit side I/O
   .tenb1         (tenb1),
   .tdat1         (tdat1[31:0]),
   .tmod1         (tmod1[1:0]),
   .tprty1        (tprty1),
   .tsop1         (tsop1),
   .teop1         (teop1),
   .terr1         (terr1),
   .tsx1          (tsx1),
   .dtpa1         (dtpa1[ports-1:0]),
   .stpa1         (stpa1),
   .ptpa1         (ptpa1),
   .tadr1         (tadr1[5:0]),

// ------------------------------------
// SPI-3 INTERFACE NUMBER 2 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   .rfclk2        (rfclk),
   .renb2         (renb2),
   .renb_a2       (renb2),
   .renb_b2       (renb2),
        
   .rsx2          (rsx2),
   .rsop2         (rsop2),
   .reop2         (reop2),
   .rprty2        (rprty2),
   .rval2         (rval2),
   .rerr2         (rerr2),
   .rmod2         (rmod2[1:0]),
   .rdat2         (rdat2[31:0]),
   
   // transmit side I/O
   .tenb2         (tenb2),
   .tdat2         (tdat2[31:0]),
   .tmod2         (tmod2[1:0]),
   .tprty2        (tprty2),
   .tsop2         (tsop2),
   .teop2         (teop2),
   .terr2         (terr2),
   .tsx2          (tsx2),
   .dtpa2         (dtpa2[ports-1:0]),
   .stpa2         (stpa2),
   .ptpa2         (ptpa2),
   .tadr2         (tadr2[5:0]),

// ------------------------------------
// SPI-3 INTERFACE NUMBER 3 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   .rfclk3        (rfclk),
   .renb3         (renb3),
   .renb_a3       (renb3),
   .renb_b3       (renb3),
        
   .rsx3          (rsx3),
   .rsop3         (rsop3),
   .reop3         (reop3),
   .rprty3        (rprty3),
   .rval3         (rval3),
   .rerr3         (rerr3),
   .rmod3         (rmod3[1:0]),
   .rdat3         (rdat3[31:0]),
   
   // transmit side I/O
   .tenb3         (tenb3),
   .tdat3         (tdat3[31:0]),
   .tmod3         (tmod3[1:0]),
   .tprty3        (tprty3),
   .tsop3         (tsop3),
   .teop3         (teop3),
   .terr3         (terr3),
   .tsx3          (tsx3),
   .dtpa3         (dtpa3[ports-1:0]),
   .stpa3         (stpa3),
   .ptpa3         (ptpa3),
   .tadr3         (tadr3[5:0]),


//ASIC side pins for the orspi.  These pins must exist for the embedded core.

  .ARDATN     (~a_rdat),  	
  .ARDATP     (a_rdat),  	
  .ARCTLN     (~a_rctl),  	
  .ARCTLP     (a_rctl),  	
  .ARDCLKN    (~a_rdclk),  	
  .ARDCLKP    (a_rdclk),  	
  .RSCLKA     (a_rsclk),		
  .RSTATA     (a_rstat),		
  .ARSCLKN    (),	
  .ARSCLKP    (),	
  .ARSTATN    (),	
  .ARSTATP    (),	
  .BRDATN     (),  	
  .BRDATP     (),  	
  .BRCTLN     (),  	
  .BRCTLP     (),  	
  .BRDCLKN    (),  	
  .BRDCLKP    (),  	
  .RSCLKB     (),		
  .RSTATB     (),		
  .BRSCLKN    (),	
  .BRSCLKP    (),	
  .BRSTATN    (),	
  .BRSTATP    (),	
  .TSCLKA     (a_tsclk),		
  .TSTATA     (a_tstat), 	
  .ATSCLKN    (),	
  .ATSCLKP    (),	
  .ATSTATN    (),	
  .ATSTATP    (),	
  .ATDATN     (),		
  .ATDATP     (a_tdat[15:0]),		
  .ATCTLN     (),		
  .ATCTLP     (a_tctl),		
  .ATDCLKN    (),	
  .ATDCLKP    (a_tdclk),	
  .ATREFCLK   (trefclk),	
  .TSCLKB     (),		// unconnected
  .TSTATB     (), 		// unconnected
  .BTSCLKN    (),		// unconnected
  .BTSCLKP    (),		// unconnected
  .BTSTATN    (),		// unconnected
  .BTSTATP    (),		// unconnected
  .BTDATN     (),		// unconnected
  .BTDATP     (),		// unconnected
  .BTCTLN     (),		
  .BTCTLP     (),		
  .BTDCLKN    (),	
  .BTDCLKP    (),	
  .BTREFCLK   (1'b0),	

  .MCREFCLK   (),	
  .PDN        (1'b1),		
  .PMIA       (PMIA[17:0]),		
  .PMIC       (),		
  .PMICN      (), 		
  .PMID       (PMID[35:0]),		
  .PMIK       (),		// unconnected
  .PMIKN      (),		// unconnected
  .PMIQ       (),		// unconnected
  .PMIRN      (),       	// unconnected
  .PMIWN      (),		// unconnected
  
  .REF10      (1'b0),		
  .REF14      (1'b1),		
  .EXT_1K     (1'b0),		

  .RESLO      (1'b0),		
  .RESHI      (1'b1),		

  .ALVCTAP1   (),	
  .ALVCTAP2   (),	
  .ALVCTAP3   (),	
  .ALVCTAP4   (),	
  .ALVCTAP5   (),	
  .BLVCTAP1   (),	
  .BLVCTAP2   (),	
  .BLVCTAP3   (),	
  .BLVCTAP4   (),	
  .BLVCTAP5   (),	

  .REFCLKN    (),	
  .REFCLKP    (),	

  .RESETN     (dut_reset_n),		

  .REXT(),		
  .REXTN(),		

//.TESTCLK    (1'b0),	
  .TESTCLK    (trefclk_2x),

  .TESTMDN    (TESTMD[1:0]), 	
  .TRISTN     (1'b1),		

  .HDINN_A    (),	
  .HDINN_B    (),	
  .HDINN_C    (),	
  .HDINN_D    (),	
  .HDINP_A    (),	
  .HDINP_B    (),	
  .HDINP_C    (),	
  .HDINP_D    (),	

  .HDOUTN_A   (),	
  .HDOUTN_B   (),	
  .HDOUTN_C   (),	
  .HDOUTN_D   (),	
  .HDOUTP_A   (),	
  .HDOUTP_B   (),	
  .HDOUTP_C   (),	
  .HDOUTP_D   (),	


//--MPI pins from the system bus 

//  .MPI_CLK    (mpi_clk),
//  .MPI_RDWR_N (mpi_rw),
//  .MPI_STRBN  (mpi_strbn),
//  .MPI_TSZ    (mpi_tsz), 
//  .MPI_BURST  (mpi_burstn),
//  .MPI_BDIP   (mpi_bdipn),
//  .CS0N       (mpi_cs0n),
//  .CS1        (mpi_cs1),
//  .USR_CLK    (usr_clk),
//  .USR_IRQ_GENERAL(usr_irq_general),
//  .MPI_ADDR   (mpi_a), 
//  .MPI_TA     (mpi_ackn),
//  .MPI_RETRY  (mpi_retryn), 
//  .MPI_TEA    (mpi_tean),
//  .MPI_IRQ    (mpi_irqn),
//  .USR_IRQ    (usr_irq),
//  .MPI_DATA   (mpi_d_temp),
//  .MPI_PARITY (mpi_dp[0])
//
  .MPI_CLK    (mpi_clk),
  .MPI_RDWR_N (mpi_rdwr_n),
  .MPI_STRBN  (mpi_strbn),
  .MPI_TSZ    (mpi_tsz), 
  .MPI_BURST  (mpi_burst),
  .MPI_BDIP   (mpi_bdip),
  .CS0N       (cs0n),
  .CS1        (cs1),
  .USR_CLK    (mpi_clk),
  .USR_IRQ_GENERAL(1'b0),
  .MPI_ADDR   (mpi_addr), 
  .MPI_TA     (mpi_ta),
  .MPI_RETRY  (mpi_retry), 
  .MPI_TEA    (mpi_tea),
  .MPI_IRQ    (mpi_irq),
  .USR_IRQ    (),
  .MPI_DATA   (mpi_data)
//  .MPI_PARITY ()
//  .SPIA_TREFCLK_X8(),
//  .SPIB_TREFCLK_X8()
);

// assign mpi_d_temp = mpi_d[7:0];

//
// SPI-3 LOOPBACK CIRCUITS FOR SIMULATION 
//

rfclk_pll rfclk_pll_o(

    .clk              (rfclk),
    .mclk             (rfclk_out),
    .nclk             (),
    .lock             ()
);

loop loop_0(

	.rfclk		(rfclk_out),
	.sys_resetn	(sys_resetn),	// system reset (active low)

	.renb		(renb0),
	.rsx		(rsx0),
	.rsop		(rsop0),
	.reop		(reop0),
	.rprty		(rprty0),
	.rmod		(rmod0),
        .rdat		(rdat0),
	.rval		(rval0),
	.rerr		(rerr0),

	.tenb		(tenb0),
	.tsx		(tsx0),
	.tsop		(tsop0),
	.teop		(teop0),
	.tprty		(tprty0),
	.tadr		(tadr0),
	.tmod		(tmod0),
        .tdat		(tdat0),
	.terr		(terr0),

	.dtpa		(dtpa0),
	.port_id_int	(4'd0)
);

loop loop_1(

	.rfclk		(rfclk_out),
	.sys_resetn	(sys_resetn),	// system reset (active low)

	.renb		(renb1),
	.rsx		(rsx1),
	.rsop		(rsop1),
	.reop		(reop1),
	.rprty		(rprty1),
	.rmod		(rmod1),
        .rdat		(rdat1),
        .rval		(rval1),
	.rerr		(rerr1),

	.tenb		(tenb1),
	.tsx		(tsx1),
	.tsop		(tsop1),
	.teop		(teop1),
	.tprty		(tprty1),
	.tadr		(tadr1),
	.tmod		(tmod1),
        .tdat		(tdat1),
	.terr		(terr1),

	.dtpa		(dtpa1),
	.port_id_int	(4'd0)
);

loop loop_2(

	.rfclk		(rfclk_out),
	.sys_resetn	(sys_resetn),	// system reset (active low)

	.renb		(renb2),
	.rsx		(rsx2),
	.rsop		(rsop2),
	.reop		(reop2),
	.rprty		(rprty2),
	.rmod		(rmod2),
        .rdat		(rdat2),
	.rval		(rval2),
	.rerr		(rerr2),

	.tenb		(tenb2),
	.tsx		(tsx2),
	.tsop		(tsop2),
	.teop		(teop2),
	.tprty		(tprty2),
	.tadr		(tadr2),
	.tmod		(tmod2),
        .tdat		(tdat2),
	.terr		(terr2),

	.dtpa		(dtpa2),
	.port_id_int	(4'd0)
);

loop loop_3(

	.rfclk		(rfclk_out),
	.sys_resetn	(sys_resetn),	// system reset (active low)

	.renb		(renb3),
	.rsx		(rsx3),
	.rsop		(rsop3),
	.reop		(reop3),
	.rprty		(rprty3),
	.rmod		(rmod3),
        .rdat		(rdat3),
	.rval		(rval3),
	.rerr		(rerr3),

	.tenb		(tenb3),
	.tsx		(tsx3),
	.tsop		(tsop3),
	.teop		(teop3),
	.tprty		(tprty3),
	.tadr		(tadr3),
	.tmod		(tmod3),
        .tdat		(tdat3),
	.terr		(terr3),

	.dtpa		(dtpa3),
	.port_id_int	(4'd0)
);

spi3mon spimon0 (
	
	.rfclk(rfclk_out),
	.renb(renb0),
	.rxdat(rdat0),
	.rmod(rmod0),
	.rprty(rprty0),
	.rval(rval0),
	.rsop(rsop0),
	.reop(reop0),
	.rerr(rerr0),
	.rsx(rsx0),
	.reset(sys_resetn),
	.bankid(2'b00)
);

spi3mon spimon1 (
	
	.rfclk(rfclk_out),
	.renb(renb1),
	.rxdat(rdat1),
	.rmod(rmod1),
	.rprty(rprty1),
	.rval(rval1),
	.rsop(rsop1),
	.reop(reop1),
	.rerr(rerr1),
	.rsx(rsx1),
	.reset(sys_resetn),
	.bankid(2'b00)
);

spi3mon spimon2 (
	
	.rfclk(rfclk_out),
	.renb(renb2),
	.rxdat(rdat2),
	.rmod(rmod2),
	.rprty(rprty2),
	.rval(rval2),
	.rsop(rsop2),
	.reop(reop2),
	.rerr(rerr2),
	.rsx(rsx2),
	.reset(sys_resetn),
	.bankid(2'b00)
);

spi3mon spimon3 (
	
	.rfclk(rfclk_out),
	.renb(renb3),
	.rxdat(rdat3),
	.rmod(rmod3),
	.rprty(rprty3),
	.rval(rval3),
	.rsop(rsop3),
	.reop(reop3),
	.rerr(rerr3),
	.rsx(rsx3),
	.reset(sys_resetn),
	.bankid(2'b00)
);


// AHB clock generation (33MHz)
//tbclk #(30.0) ahb_clk (1'b1, HCLK);
tbclk #(30.0) ahb_clk (1'b1, mpi_clk);


// AHB Master instantiation
//bmaster bmaster (
//      .HCLK       (HCLK),
//      .HRESET_N   (dut_reset_n),
//      .HGRANT     (1'b1),
//      .HREADY     (toptest.orspi_qspi3.mycore_inst.HREADY_OUT),
//      .HRESP      (toptest.orspi_qspi3.mycore_inst.HRESP),
//      .HRDATA     (toptest.orspi_qspi3.mycore_inst.HRDATA),
//      .HBUSREQ    (),
//      .HLOCK      (),
//      .HWRITE     (toptest.orspi_qspi3.mycore_inst.HWRITE),
//      .HBURST     (toptest.orspi_qspi3.mycore_inst.HBURST),
//      .HTRANS     (toptest.orspi_qspi3.mycore_inst.HTRANS),
//      .HADDR      (toptest.orspi_qspi3.mycore_inst.HADDR),
//      .HSIZE      (toptest.orspi_qspi3.mycore_inst.HSIZE),
//      .HWDATA     (toptest.orspi_qspi3.mycore_inst.HWDATA)
//      );

bmaster bmaster(
   .mpi_clk	(mpi_clk),
   .mpi_tsz	(mpi_tsz),
   .mpi_rdwr_n	(mpi_rdwr_n),
   .mpi_burst	(mpi_burst),
   .mpi_bdip	(mpi_bdip),
   .mpi_strbn	(mpi_strbn),
   .cs0n	(cs0n),
   .cs1		(cs1),
   .mpi_addr	(mpi_addr),
   .mpi_data	(mpi_data),
   .mpi_ta	(mpi_ta),
   .mpi_tea	(mpi_tea),
   .mpi_irq	(mpi_irq),
   .mpi_retry   (mpi_retry)
);



//
//LatSPI
//

latspi4 a_latspi4 (
                 .tdclk(a_rdclk),
                 .tdat(a_rdat),
                 .tctl(a_rctl),
                 .tsclk(a_rsclk),
                 .tstat(a_rstat),

                 .rdclk(a_tdclk),
                 .rdat(a_tdat),
                 .rctl(a_tctl),
                 .rsclk(a_tsclk),
                 .rstat(a_tstat)
                 );

// ---------------------------------------------------------------------------
// Clocks
// ---------------------------------------------------------------------------
initial
begin
   trefclk_2x  = 1'b0;
   trefclk_div = 3'b000;
   rfclk = 1'b0;
end

// POS-PHY clocks

// 2x DDR clock for SPI4HSIX model operating in PLL bypass mode
always #(0.625) trefclk_2x = ~trefclk_2x;    // 800MHz
always #(4.808) rfclk = ~rfclk;    		// 104MHz

// Divide trefclk_2x by 8 to get trefclk
always @(posedge trefclk_2x)
   trefclk_div = trefclk_div + 3'b001;

assign trefclk = trefclk_div[2];

// ---------------------------------------------------------------------------
// Reset
// ---------------------------------------------------------------------------
initial
begin
   reset_done = 1'b0;
   
   // First reset
   // Hard-reset & SPI4 reset
   dut_reset  = 1'b0;
   sys_rst_n  = 1'b0;
   spi4_reset = 1'b0;
   sys_resetn = 1'b0;
   FPGA_LB    = 1'b0;
   #(1);
   dut_reset  = 1'b1;
   sys_rst_n  = 1'b1;
   spi4_reset = 1'b1;

   #(100);
   sys_resetn = 1'b1;

				// delay reset to asb
   #(400);			// mph
   dut_reset  = 1'b0;		// mph
   spi4_reset = 1'b0;		// mph
   
   // Second reset
   // SPI4 reset only
   #(500);
   spi4_reset = 1'b1;
   -> preload_ram;
   #(100);
   spi4_reset = 1'b0;
   
   reset_done = 1'b1;
end

assign      dut_reset_n = ~dut_reset;

// ---------------------------------------------------------------------------
// output from spi3mon
// ---------------------------------------------------------------------------
integer log_file;

initial begin

   log_file = $fopen ("sim.log");

   #10000000

   $fclose(log_file);

end



// ---------------------------------------------------------------------------
// SDF annotation  
// ---------------------------------------------------------------------------
`ifdef ANNOTATE
initial
begin
   $sdf_annotate("../primetime/report_sdf/orspii_asb.sdfRC",
                  orspii_asb,
                  ,
                  "sdf_annotate.log",
                  "MAXIMUM"
                 );
end
`endif

// ---------------------------------------------------------------------------
// Gate-level RAM pre-load to prevent X propagation  
// ---------------------------------------------------------------------------
`ifdef GATELEVEL
always @(preload_ram)
begin
   // While in this second reset, initialize control memories to randomly set data (see rand_init.pl)
//   toptest.orspii_asb.s4a.t.tx_ls_inst.tsp_top.port_status_mem.mem_array.U_BIST_BINT0_M.BR.M.load("port_status.init");
//   toptest.orspii_asb.s4a.t.tx_cf_inst.pws_inst.pws_cr_inst.credit_inst.SW_MPSRAM0_M.BR.M.load("credit.init");
//   toptest.orspii_asb.s4a.t.tx_cf_inst.pws_inst.pws_pdm_inst.pdm_inst.SW_MPSRAM0_M.BR.M.load("pdm_main.init");
//   toptest.orspii_asb.s4a.t.tx_cf_inst.pws_inst.pws_stat_inst.status_inst.SW_MPSRAM0_M.BR.M.load("pdm_stat.init");
//   toptest.orspii_asb.s4a.t.tx_cf_inst.pws_inst.pws_spt_inst.spt_inst.SW_MPSRAM0_M.BR.M.load("mpcal.init");

   toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.tx_ls_inst.tsp_top.port_status_mem.mem_array.U_BIST_BINT0_M.BR.M.load("port_status.init");
   toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.tx_cf_inst.pws_inst.pws_cr_inst.credit_inst.SW_MPSRAM0_M.BR.M.load("credit.init");
   toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.tx_cf_inst.pws_inst.pws_pdm_inst.pdm_inst.SW_MPSRAM0_M.BR.M.load("pdm_main.init");
   toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.tx_cf_inst.pws_inst.pws_stat_inst.status_inst.SW_MPSRAM0_M.BR.M.load("pdm_stat.init");
   toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.tx_cf_inst.pws_inst.pws_spt_inst.spt_inst.SW_MPSRAM0_M.BR.M.load("mpcal.init");
end
`endif

// ---------------------------------------------------------------------------
// Simulation lock-up termination
// ---------------------------------------------------------------------------
initial
begin
//  sec  msec   usec   nsec
   #(1 * 1000 * 1000 * 1000);      // 1 second timebomb
   $display("%t: ERROR: Simulation lock-up. Terminating after 1 second...",$time);
   $display("%t: *******************************************************",$time);
   $display("%t: ****               T E S T   F A I L E D",$time);
   $display("%t: *******************************************************",$time);
   $finish(2);
end

// ---------------------------------------------------------------------------
// Main initial block to run test
// ---------------------------------------------------------------------------

initial
begin // end is contained in footer.v

   RX_DPRAM_0_AGGR_MODE = 2'b00;
   RX_DPRAM_1_AGGR_MODE = 2'b00;
   RX_DPRAM_2_AGGR_MODE = 2'b00;
   RX_DPRAM_3_AGGR_MODE = 2'b00;
   
 
 
   test_go = 1'b0;
      
   // HSIX requires 2x clock when operating in bypass mode (set by testio_mux)
   // the TSTCLK connects to the scan clock. Simulation speed will be greatly
   // affected if all the test logic is run @ 800MHz, so this force probes
   // down into the design to force the high-speed clock into the HSIX model 
//   force  orspii_asb.s4a.r.rdi.TSTCLK           = trefclk_2x;  
//   force  orspii_asb.s4a.t.tx_hs_inst.TSTCLK    = trefclk_2x;
/*      
force  { toptest.orspi_qspi3.\\mycore_inst/orspi_core_inst\/\mycore_inst/orspi_core_inst_ORSPI_CORE\.INST10.asb_inst.s4a.r.rdi.TSTCLK }         = trefclk_2x;

force  { toptest.orspi_qspi3.\\mycore_inst/orspi_core_inst_ORSPI_CORE\\.INST10.asb_inst.s4a.t.tx_hs_inst.TSTCLK }  = trefclk_2x;

// force  toptest.orspi_qspi3.\mycore_inst/orspi_core_inst.\mycore_inst/orspi_core_inst_ORSPI_CORE.s4a.r.rdi.TSTCLK           = trefclk_2x;  
//    force  toptest.orspi_qspi3.\mycore_inst/orspi_core_inst.\mycore_inst/orspi_core_inst_ORSPI_CORE.s4a.t.tx_hs_inst.TSTCLK    = trefclk_2x;
*/        
   $timeformat(-9,0," ns",10);

   $display("**************************************************************");
   $display("****                                                          ");
   $display("****              LATTICE SEMICONDUCTOR, INC.                 ");
   $display("****                     O R S P I I                          ");
   $display("****        Top Level Verification - Phase 1 - S4A            ");
   $display("****                                                          ");
   $display("**** =========================================================");
   $display("****");
   $display("****    Build date: %s",`BUILDDATE);
   $display("****    Built by:   %s",`BUILDWHO);
   $display("****");
   $display("****    SF: %s",`SF);
   $display("****     M: %s",`M);
   $display("****");
   $display("**************************************************************");

   error_count = 0;

// Wait for reset to be deasserted before continuing
   wait (reset_done == 1'b1);

   $display("%t: DUT out of reset",$time);
   
// commented out - does not exist in new bmaster - mph
//   bmaster.set_retry_limit(10);

// Wait for DUT to initialise RAMs before continuing
//   wait (orspii_asb.s4a.t.MEM_TXPDMC_INIT_DONE == 1'b1 &&
//         orspii_asb.s4a.t.MEM_TXPDMM_INIT_DONE == 1'b1 &&
//         orspii_asb.s4a.t.MEM_TXPDMU_INIT_DONE == 1'b1 );

// add a delay as a substitute for the following wait
// determined by watching an older simulation (3 usec)
// also added additional delay because circuit was not responding to first MPI read 
 #9000;
 #11000;

//   wait (toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.MEM_TXPDMC_INIT_DONE == 1'b1 &&
//         toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.MEM_TXPDMM_INIT_DONE == 1'b1 &&
//         toptest.orspi_qspi3.mycore_inst.orspi_core_inst.asb_inst.s4a.t.MEM_TXPDMU_INIT_DONE == 1'b1 );

// Short delay to let everything settle down..
   #200;

   test_go = 1'b1;
   
