
// NOTE: This template file has been provided to instantiate the interface
//       netlist.  Since this template contains synthesis attributes that
//       are crucial to the design flow, we recommend that you use this
//       template in your FPGA design.

`timescale 1ns/ 100 ps

`include "qspi3_define.v"

module orspi_qspi3 (

// FPGA design top level I/Os 
sys_resetn, 
sys_rst_n,

rfclk0, renb0, renb_a0, renb_b0,
rsx0, rsop0, reop0, rprty0, rval0, rerr0, rmod0, rdat0, 
tenb0, tdat0, tmod0, tprty0, tsop0, teop0, terr0, 
tsx0, dtpa0, stpa0, ptpa0, tadr0, 

`ifdef NUMINT2
rfclk1, renb1, renb_a1, renb_b1,
rsx1, rsop1, reop1, rprty1, rval1, rerr1, rmod1, rdat1, 
tenb1, tdat1, tmod1, tprty1, tsop1, teop1, terr1, 
tsx1, dtpa1, stpa1, ptpa1, tadr1, 
`endif

`ifdef NUMINT3
rfclk2, renb2, renb_a2, renb_b2,
rsx2, rsop2, reop2, rprty2, rval2, rerr2, rmod2, rdat2, 
tenb2, tdat2, tmod2, tprty2, tsop2, teop2, terr2, 
tsx2, dtpa2, stpa2, ptpa2, tadr2, 
`endif

`ifdef NUMINT4
rfclk3, renb3, renb_a3, renb_b3,
rsx3, rsop3, reop3, rprty3, rval3, rerr3, rmod3, rdat3, 
tenb3, tdat3, tmod3, tprty3, tsop3, teop3, terr3, 
tsx3, dtpa3, stpa3, ptpa3, tadr3, 
`endif


//APIOs

ARCTLN, ARCTLP, ARDATN, ARDATP, ARDCLKN, ARDCLKP, 
RSCLKA, RSTATA, 
ARSTATN, ARSTATP, ARSCLKN, ARSCLKP,
ATCTLN, ATCTLP, ATDATN, ATDATP, ATDCLKN, ATDCLKP, ATREFCLK, 
TSCLKA, TSTATA, 
ATSCLKN, ATSCLKP, ATSTATN, ATSTATP,
BRCTLN, BRCTLP, BRDATN, BRDATP, BRDCLKN, BRDCLKP,
RSCLKB, RSTATB, 
BRSTATN, BRSTATP, BRSCLKN, BRSCLKP,
BTCTLN, BTCTLP, BTDATN, BTDATP, BTDCLKN, BTDCLKP, BTREFCLK, 
TSCLKB, TSTATB, 
BTSCLKN, BTSCLKP, BTSTATN, BTSTATP,
HDINN_A, HDINN_B, HDINN_C, HDINN_D, HDINP_A, HDINP_B, HDINP_C, HDINP_D, 
HDOUTN_A, HDOUTN_B, HDOUTN_C, HDOUTN_D, HDOUTP_A, HDOUTP_B, HDOUTP_C, HDOUTP_D, 
MCREFCLK, PDN, PMIA, PMIC, PMICN, PMID, PMIK, PMIKN, PMIQ, PMIRN, PMIWN, 
REF10, REF14, EXT_1K, REFCLKN, REFCLKP, RESETN,
ALVCTAP1, ALVCTAP2, ALVCTAP3, ALVCTAP4, ALVCTAP5,
BLVCTAP1, BLVCTAP2, BLVCTAP3, BLVCTAP4, BLVCTAP5,
TESTCLK, TESTMDN, TRISTN, RESLO, RESHI, REXT, REXTN,

// System Bus related

MPI_CLK, MPI_RDWR_N, MPI_STRBN, MPI_TSZ, MPI_BURST,
MPI_BDIP, CS0N, CS1, MPI_ADDR, MPI_DATA, 
// MPI_PARITY,
MPI_TA, MPI_RETRY, MPI_TEA, MPI_IRQ, USR_CLK,
USR_IRQ_GENERAL, USR_IRQ);

// parameters to locate EBR RAMS
// parameter ram_placement_ttop01_0 = "RAM1024_0";
// parameter ram_placement_ttop00_1 = "RAM512_1";
// parameter ram_placement_rtop01_0 = "RAM1024_2";
// parameter ram_placement_rtop00_1 = "RAM512_3";
// 
// parameter ram_placement_ttop11_0 = "RAM1024_32";
// parameter ram_placement_ttop10_1 = "RAM512_33";
// parameter ram_placement_rtop11_0 = "RAM1024_34";
// parameter ram_placement_rtop10_1 = "RAM512_35";
// 
// parameter ram_placement_ttop21_0 = "RAM1024_36";
// parameter ram_placement_ttop20_1 = "RAM512_37";
// parameter ram_placement_rtop21_0 = "RAM1024_38";
// parameter ram_placement_rtop20_1 = "RAM512_39";
// 
// parameter ram_placement_ttop31_0 = "RAM1024_4";
// parameter ram_placement_ttop30_1 = "RAM512_5";
// parameter ram_placement_rtop31_0 = "RAM1024_6";
// parameter ram_placement_rtop30_1 = "RAM512_7";
// 

// User defined parameters:

// parameters for transmit side of SPI3 bridge
parameter ports      = `PORTS;

// FPGA external interface io

   input        sys_resetn;    //exemplar attribute sys_resetn NOPAD true
                               // system reset (active low)
			        
   input        sys_rst_n;     

// ------------------------------------
// SPI-3 INTERFACE NUMBER 0 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   input          rfclk0;       //exemplar attribute rfclk0 NOPAD true
   input          renb0;        //exemplar attribute renb0 NOPAD true
   input          renb_a0;      //exemplar attribute renb_a0 NOPAD true
   input          renb_b0;      //exemplar attribute renb_b0 NOPAD true
        
   output         rsx0;         //exemplar attribute rsx0 NOPAD true
   output         rsop0;        //exemplar attribute rsop0 NOPAD true
   output         reop0;        //exemplar attribute reop0 NOPAD true
   output         rprty0;       //exemplar attribute rprty0 NOPAD true
   output         rval0;        //exemplar attribute rval0 NOPAD true
   output         rerr0;        //exemplar attribute rerr0 NOPAD true
   output [1:0]   rmod0;        //exemplar attribute rmod0 NOPAD true
   output [31:0]  rdat0;        //exemplar attribute rdat0 NOPAD true
   
   // transmit side I/O
   input          tenb0;        //exemplar attribute tenb0 NOPAD true
   input [31:0]   tdat0;        //exemplar attribute tdat0 NOPAD true
   input [1:0]    tmod0;        //exemplar attribute tmod0 NOPAD true
   input          tprty0;       //exemplar attribute tprty0 NOPAD true
   input          tsop0;        //exemplar attribute tsop0 NOPAD true
   input          teop0;        //exemplar attribute teop0 NOPAD true
   input          terr0;        //exemplar attribute terr0 NOPAD true
   input          tsx0;         //exemplar attribute tsx0 NOPAD true
   output [ports-1:0] dtpa0;    //exemplar attribute dtpa0 NOPAD true
   output         stpa0;        //exemplar attribute stpa0 NOPAD true
   output         ptpa0;        //exemplar attribute ptpa0 NOPAD true
   input [5:0]    tadr0;        //exemplar attribute tadr0 NOPAD true

`ifdef NUMINT2

// ------------------------------------
// SPI-3 INTERFACE NUMBER 1 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   input          rfclk1;       //exemplar attribute rfclk1 NOPAD true
   input          renb1;        //exemplar attribute renb1 NOPAD true
   input          renb_a1;      //exemplar attribute renb_a1 NOPAD true
   input          renb_b1;      //exemplar attribute renb_b1 NOPAD true
        
   output         rsx1;         //exemplar attribute rsx1 NOPAD true
   output         rsop1;        //exemplar attribute rsop1 NOPAD true
   output         reop1;        //exemplar attribute reop1 NOPAD true
   output         rprty1;       //exemplar attribute rprty1 NOPAD true
   output         rval1;        //exemplar attribute rval1 NOPAD true
   output         rerr1;        //exemplar attribute rerr1 NOPAD true
   output [1:0]   rmod1;        //exemplar attribute rmod1 NOPAD true
   output [31:0]  rdat1;        //exemplar attribute rdat1 NOPAD true
   
   // transmit side I/O
   input          tenb1;        //exemplar attribute tenb1 NOPAD true
   input [31:0]   tdat1;        //exemplar attribute tdat1 NOPAD true
   input [1:0]    tmod1;        //exemplar attribute tmod1 NOPAD true
   input          tprty1;       //exemplar attribute tprty1 NOPAD true
   input          tsop1;        //exemplar attribute tsop1 NOPAD true
   input          teop1;        //exemplar attribute teop1 NOPAD true
   input          terr1;        //exemplar attribute terr1 NOPAD true
   input          tsx1;         //exemplar attribute tsx1 NOPAD true
   output [ports-1:0] dtpa1;    //exemplar attribute dtpa1 NOPAD true
   output         stpa1;        //exemplar attribute stpa1 NOPAD true
   output         ptpa1;        //exemplar attribute ptpa1 NOPAD true
   input [5:0]    tadr1;        //exemplar attribute tadr1 NOPAD true

`endif

`ifdef NUMINT3

// ------------------------------------
// SPI-3 INTERFACE NUMBER 2 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   input          rfclk2;       //exemplar attribute rfclk2 NOPAD true
   input          renb2;        //exemplar attribute renb2 NOPAD true
   input          renb_a2;      //exemplar attribute renb_a2 NOPAD true
   input          renb_b2;      //exemplar attribute renb_b2 NOPAD true
        
   output         rsx2;         //exemplar attribute rsx2 NOPAD true
   output         rsop2;        //exemplar attribute rsop2 NOPAD true
   output         reop2;        //exemplar attribute reop2 NOPAD true
   output         rprty2;       //exemplar attribute rprty2 NOPAD true
   output         rval2;        //exemplar attribute rval2 NOPAD true
   output         rerr2;        //exemplar attribute rerr2 NOPAD true
   output [1:0]   rmod2;        //exemplar attribute rmod2 NOPAD true
   output [31:0]  rdat2;        //exemplar attribute rdat2 NOPAD true
   
   // transmit side I/O
   input          tenb2;        //exemplar attribute tenb2 NOPAD true
   input [31:0]   tdat2;        //exemplar attribute tdat2 NOPAD true
   input [1:0]    tmod2;        //exemplar attribute tmod2 NOPAD true
   input          tprty2;       //exemplar attribute tprty2 NOPAD true
   input          tsop2;        //exemplar attribute tsop2 NOPAD true
   input          teop2;        //exemplar attribute teop2 NOPAD true
   input          terr2;        //exemplar attribute terr2 NOPAD true
   input          tsx2;         //exemplar attribute tsx2 NOPAD true
   output [ports-1:0] dtpa2;    //exemplar attribute dtpa2 NOPAD true
   output         stpa2;        //exemplar attribute stpa2 NOPAD true
   output         ptpa2;        //exemplar attribute ptpa2 NOPAD true
   input [5:0]    tadr2;        //exemplar attribute tadr2 NOPAD true

`endif

`ifdef NUMINT4

// ------------------------------------
// SPI-3 INTERFACE NUMBER 3 I/O SIGNALS
// ------------------------------------

   // receive side I/O
   input          rfclk3;       //exemplar attribute rfclk3 NOPAD true
   input          renb3;        //exemplar attribute renb3 NOPAD true
   input          renb_a3;      //exemplar attribute renb_a3 NOPAD true
   input          renb_b3;      //exemplar attribute renb_b3 NOPAD true
        
   output         rsx3;         //exemplar attribute rsx3 NOPAD true
   output         rsop3;        //exemplar attribute rsop3 NOPAD true
   output         reop3;        //exemplar attribute reop3 NOPAD true
   output         rprty3;       //exemplar attribute rprty3 NOPAD true
   output         rval3;        //exemplar attribute rval3 NOPAD true
   output         rerr3;        //exemplar attribute rerr3 NOPAD true
   output [1:0]   rmod3;        //exemplar attribute rmod3 NOPAD true
   output [31:0]  rdat3;        //exemplar attribute rdat3 NOPAD true
   
   // transmit side I/O
   input          tenb3;        //exemplar attribute tenb3 NOPAD true
   input [31:0]   tdat3;        //exemplar attribute tdat3 NOPAD true
   input [1:0]    tmod3;        //exemplar attribute tmod3 NOPAD true
   input          tprty3;       //exemplar attribute tprty3 NOPAD true
   input          tsop3;        //exemplar attribute tsop3 NOPAD true
   input          teop3;        //exemplar attribute teop3 NOPAD true
   input          terr3;        //exemplar attribute terr3 NOPAD true
   input          tsx3;         //exemplar attribute tsx3 NOPAD true
   output [ports-1:0] dtpa3;    //exemplar attribute dtpa3 NOPAD true
   output         stpa3;        //exemplar attribute stpa3 NOPAD true
   output         ptpa3;        //exemplar attribute ptpa3 NOPAD true
   input [5:0]    tadr3;        //exemplar attribute tadr3 NOPAD true

`endif

// external pads

//ASIC side pins for the orspi.  These pins must exist for the embedded core.

  input  [15:0]	ARDATN;  	//exemplar attribute ARDATN NOPAD true
  input  [15:0] ARDATP;  	//exemplar attribute ARDATP NOPAD true
  input  	ARCTLN;  	//exemplar attribute ARCTLN NOPAD true
  input  	ARCTLP;  	//exemplar attribute ARCTLP NOPAD true
  input  	ARDCLKN;  	//exemplar attribute ARDCLKN NOPAD true
  input  	ARDCLKP;  	//exemplar attribute ARDCLKP NOPAD true
  output	RSCLKA;		//exemplar attribute RSCLKA NOPAD true
  output  [1:0]	RSTATA;		//exemplar attribute RSTATA NOPAD true
  output 	ARSCLKN;	//exemplar attribute ARSCLKN NOPAD true
  output 	ARSCLKP;	//exemplar attribute ARSCLKP NOPAD true
  output  [1:0] ARSTATN;	//exemplar attribute ARSTATN NOPAD true
  output  [1:0] ARSTATP;	//exemplar attribute ARSTATP NOPAD true
  input  [15:0]	BRDATN;  	//exemplar attribute BRDATN NOPAD true
  input  [15:0] BRDATP;  	//exemplar attribute BRDATP NOPAD true
  input  	BRCTLN;  	//exemplar attribute BRCTLN NOPAD true
  input  	BRCTLP;  	//exemplar attribute BRCTLP NOPAD true
  input  	BRDCLKN;  	//exemplar attribute BRDCLKN NOPAD true
  input  	BRDCLKP;  	//exemplar attribute BRDCLKP NOPAD true
  output	RSCLKB;		//exemplar attribute RSCLKB NOPAD true
  output  [1:0]	RSTATB;		//exemplar attribute RSTATB NOPAD true
  output 	BRSCLKN;	//exemplar attribute BRSCLKN NOPAD true
  output 	BRSCLKP;	//exemplar attribute BRSCLKP NOPAD true
  output  [1:0] BRSTATN;	//exemplar attribute BRSTATN NOPAD true
  output  [1:0] BRSTATP;	//exemplar attribute BRSTATP NOPAD true
  input		TSCLKA;		//exemplar attribute TSCLKA NOPAD true
  input	  [1:0]	TSTATA; 	//exemplar attribute TSTATA NOPAD true
  input		ATSCLKN;	//exemplar attribute ATSCLKN NOPAD true
  input		ATSCLKP;	//exemplar attribute ATSCLKP NOPAD true
  input   [1:0]	ATSTATN;	//exemplar attribute ATSTATN NOPAD true
  input   [1:0] ATSTATP;	//exemplar attribute ATSTATP NOPAD true
  output [15:0] ATDATN;		//exemplar attribute ATDATN NOPAD true
  output [15:0] ATDATP;		//exemplar attribute ATDATP NOPAD true
  output	ATCTLN;		//exemplar attribute ATCTLN NOPAD true
  output	ATCTLP;		//exemplar attribute ATCTLP NOPAD true
  output	ATDCLKN;	//exemplar attribute ATDCLKN NOPAD true
  output	ATDCLKP;	//exemplar attribute ATDCLKP NOPAD true
  input		ATREFCLK;	//exemplar attribute ATREFCLK NOPAD true
  input		TSCLKB;		//exemplar attribute TSCLKB NOPAD true
  input	[1:0]	TSTATB; 	//exemplar attribute TSTATB NOPAD true
  input		BTSCLKN;	//exemplar attribute BTSCLKN NOPAD true
  input		BTSCLKP;	//exemplar attribute BTSCLKP NOPAD true
  input	[1:0]	BTSTATN;	//exemplar attribute BTSTATN NOPAD true
  input [1:0]   BTSTATP;	//exemplar attribute BTSTATP NOPAD true
  output [15:0]	BTDATN;		//exemplar attribute BTDATN NOPAD true
  output [15:0] BTDATP;		//exemplar attribute BTDATP NOPAD true
  output	BTCTLN;		//exemplar attribute BTCTLN NOPAD true
  output	BTCTLP;		//exemplar attribute BTCTLP NOPAD true
  output	BTDCLKN;	//exemplar attribute BTDCLKN NOPAD true
  output 	BTDCLKP;	//exemplar attribute BTDCLKP NOPAD true
  input		BTREFCLK;	//exemplar attribute BTREFCLK NOPAD true

  inout		MCREFCLK;	//exemplar attribute MCREFCLK NOPAD true
  input		PDN;		//exemplar attribute PDN NOPAD true
  inout [17:0]	PMIA;		//exemplar attribute PMIA NOPAD true
  inout		PMIC;		//exemplar attribute PMIC NOPAD true
  inout		PMICN; 		//exemplar attribute PMICN NOPAD true
  inout [35:0]  PMID;		//exemplar attribute PMID NOPAD true
  inout		PMIK;		//exemplar attribute PMIK NOPAD true
  inout		PMIKN;		//exemplar attribute PMIKN NOPAD true
  inout	[35:0]	PMIQ;		//exemplar attribute PMIQ NOPAD true
  inout		PMIRN;		//exemplar attribute PMIRN NOPAD true
  inout		PMIWN;		//exemplar attribute PMIWN NOPAD true
  
  input		REF10;		//exemplar attribute REF10 NOPAD true
  input		REF14;		//exemplar attribute REF14 NOPAD true
  input		EXT_1K;		//exemplar attribute EXT_1K NOPAD true

  input		RESLO;		//exemplar attribute RESLO NOPAD true
  input		RESHI;		//exemplar attribute RESHI NOPAD true

  input		ALVCTAP1;	//exemplar attribute ALVCTAP1 NOPAD true
  input		ALVCTAP2;	//exemplar attribute ALVCTAP2 NOPAD true
  input		ALVCTAP3;	//exemplar attribute ALVCTAP3 NOPAD true
  input		ALVCTAP4;	//exemplar attribute ALVCTAP4 NOPAD true
  input		ALVCTAP5;	//exemplar attribute ALVCTAP5 NOPAD true
  input		BLVCTAP1;	//exemplar attribute BLVCTAP1 NOPAD true
  input		BLVCTAP2;	//exemplar attribute BLVCTAP2 NOPAD true
  input		BLVCTAP3;	//exemplar attribute BLVCTAP3 NOPAD true
  input		BLVCTAP4;	//exemplar attribute BLVCTAP4 NOPAD true
  input		BLVCTAP5;	//exemplar attribute BLVCTAP5 NOPAD true

  input		REFCLKN;	//exemplar attribute REFCLKN NOPAD true
  input		REFCLKP;	//exemplar attribute REFCLKP NOPAD true

  input		RESETN;		//exemplar attribute RESETN NOPAD true

  output	REXT;		//exemplar attribute REXT NOPAD true
  output	REXTN;		//exemplar attribute REXTN NOPAD true

  input 	TESTCLK;	//exemplar attribute TESTCLK NOPAD true

  input	[1:0]   TESTMDN; 	//exemplar attribute TESTMDN NOPAD true
  input		TRISTN;		//exemplar attribute TRISTN NOPAD true

  input		HDINN_A;	//exemplar attribute HDINN_A NOPAD true
  input		HDINN_B;	//exemplar attribute HDINN_B NOPAD true
  input		HDINN_C;	//exemplar attribute HDINN_C NOPAD true
  input		HDINN_D;	//exemplar attribute HDINN_D NOPAD true
  input		HDINP_A;	//exemplar attribute HDINP_A NOPAD true
  input		HDINP_B;	//exemplar attribute HDINP_B NOPAD true
  input		HDINP_C;	//exemplar attribute HDINP_C NOPAD true
  input		HDINP_D;	//exemplar attribute HDINP_D NOPAD true

  output	HDOUTN_A;	//exemplar attribute HDOUTN_A NOPAD true
  output	HDOUTN_B;	//exemplar attribute HDOUTN_B NOPAD true
  output	HDOUTN_C;	//exemplar attribute HDOUTN_C NOPAD true
  output	HDOUTN_D;	//exemplar attribute HDOUTN_D NOPAD true
  output	HDOUTP_A;	//exemplar attribute HDOUTP_A NOPAD true
  output	HDOUTP_B;	//exemplar attribute HDOUTP_B NOPAD true
  output	HDOUTP_C;	//exemplar attribute HDOUTP_C NOPAD true
  output	HDOUTP_D;	//exemplar attribute HDOUTP_D NOPAD true

//--MPI pins from the system bus 

  input MPI_CLK;	//exemplar attribute MPI_CLK NOPAD true
  input MPI_RDWR_N;	//exemplar attribute MPI_RDWR_N NOPAD true
  input MPI_STRBN;	//exemplar attribute MPI_STRBN NOPAD true
  input [0:1] MPI_TSZ;  //exemplar attribute MPI_TSZ NOPAD true
  input MPI_BURST;	//exemplar attribute MPI_BURST NOPAD true 
  input MPI_BDIP;	//exemplar attribute MPI_BDIP NOPAD true 
  input CS0N;		//exemplar attribute CSON NOPAD true
  input CS1;		//exemplar attribute CS1 NOPAD true
  input USR_CLK;
  input USR_IRQ_GENERAL;
  input [14:31] MPI_ADDR; //exemplar attribute MPI_ADDR NOPAD true
  output MPI_TA;	  //exemplar attribute MPI_TA NOPAD true
  output MPI_RETRY; 	  //exemplar attribute MPI_RETRY NOPAD true
  output MPI_TEA;	  //exemplar attribute MPI_TEA NOPAD true
  output MPI_IRQ;	  //exemplar attribute MPI_IRQ NOPAD true
  output USR_IRQ;	  
  inout [0:7] MPI_DATA;   //exemplar attribute MPI_DATA NOPAD true
//  inout MPI_PARITY;	  //exemplar attribute MPI_PARITY NOPAD true
//-- Signal definitions for the system bus and FPSC interface connections.  
//-- Some of these  signals are connected for you in this top level module 
//-- to the orspi and system bus modules.
wire	SPIA_RX32_CLK_0, SPIA_RX32_CLK_1, SPIA_RX32_CLK_2, SPIA_RX32_CLK_3;
wire    SPIA_RX32_RD_0, SPIA_RX32_RD_1, SPIA_RX32_RD_2, SPIA_RX32_RD_3;
wire	[2:0]	SPIA_RX32_ADDR_0;
wire	[2:0]	SPIA_RX32_ADDR_1;
wire    [2:0]   SPIA_RX32_ADDR_2;
wire	[2:0]	SPIA_RX32_ADDR_3;
wire    [7:0]	SPIA_RX32_PORT_ID;
wire		SPIA_RX32_EXT_STAT_EN;
wire	[1:0]	SPIA_RX32_STAT;
wire		SPIA_RX32_PSS_WE;
wire		SPIA_RX32_PSS_CLK;
wire	[31:0]	SPIA_RX32_DATA_0;
wire	[31:0]  SPIA_RX32_DATA_1;
wire	[31:0]  SPIA_RX32_DATA_2;
wire	[31:0]	SPIA_RX32_DATA_3;
wire    [3:0]	SPIA_RX32_BE_0, SPIA_RX32_BE_1, SPIA_RX32_BE_2, SPIA_RX32_BE_3;
wire		SPIA_RX32_CTL_0, SPIA_RX32_CTL_1, SPIA_RX32_CTL_2, SPIA_RX32_CTL_3;
wire		SPIA_RX32_ERR_0, SPIA_RX32_ERR_1, SPIA_RX32_ERR_2, SPIA_RX32_ERR_3;
wire		SPIA_RX32_SOP_0, SPIA_RX32_SOP_1, SPIA_RX32_SOP_2, SPIA_RX32_SOP_3;
wire		SPIA_RX32_EOP_0, SPIA_RX32_EOP_1, SPIA_RX32_EOP_2, SPIA_RX32_EOP_3;
wire		SPIA_RX32_FIFO_EMPTY_0, SPIA_RX32_FIFO_EMPTY_1;
wire		SPIA_RX32_FIFO_EMPTY_2, SPIA_RX32_FIFO_EMPTY_3;
wire	SPIB_RX32_CLK_0, SPIB_RX32_CLK_1, SPIB_RX32_CLK_2, SPIB_RX32_CLK_3;
wire    SPIB_RX32_RD_0, SPIB_RX32_RD_1, SPIB_RX32_RD_2, SPIB_RX32_RD_3;
wire	[2:0]	SPIB_RX32_ADDR_0;
wire	[2:0]	SPIB_RX32_ADDR_1;
wire    [2:0]   SPIB_RX32_ADDR_2;
wire	[2:0]	SPIB_RX32_ADDR_3;
wire    [7:0]	SPIB_RX32_PORT_ID;
wire		SPIB_RX32_EXT_STAT_EN;
wire	[1:0]	SPIB_RX32_STAT;
wire		SPIB_RX32_PSS_WE;
wire		SPIB_RX32_PSS_CLK;
wire	[31:0]	SPIB_RX32_DATA_0;
wire	[31:0]  SPIB_RX32_DATA_1;
wire	[31:0]  SPIB_RX32_DATA_2;
wire	[31:0]	SPIB_RX32_DATA_3;
wire    [3:0]	SPIB_RX32_BE_0, SPIB_RX32_BE_1, SPIB_RX32_BE_2, SPIB_RX32_BE_3;
wire		SPIB_RX32_CTL_0, SPIB_RX32_CTL_1, SPIB_RX32_CTL_2, SPIB_RX32_CTL_3;
wire		SPIB_RX32_ERR_0, SPIB_RX32_ERR_1, SPIB_RX32_ERR_2, SPIB_RX32_ERR_3;
wire		SPIB_RX32_SOP_0, SPIB_RX32_SOP_1, SPIB_RX32_SOP_2, SPIB_RX32_SOP_3;
wire		SPIB_RX32_EOP_0, SPIB_RX32_EOP_1, SPIB_RX32_EOP_2, SPIB_RX32_EOP_3;
wire		SPIB_RX32_FIFO_EMPTY_0, SPIB_RX32_FIFO_EMPTY_1;
wire		SPIB_RX32_FIFO_EMPTY_2, SPIB_RX32_FIFO_EMPTY_3;
wire	[31:0]	SPIA_TX32_DATA_0;
wire	[31:0]	SPIA_TX32_DATA_1;
wire	[31:0]	SPIA_TX32_DATA_2;
wire	[31:0]	SPIA_TX32_DATA_3;
wire	[7:0]	SPIA_TX32_PORT_0;
wire	[7:0]	SPIA_TX32_PORT_1;
wire	[7:0]	SPIA_TX32_PORT_2;
wire	[7:0]	SPIA_TX32_PORT_3;
wire	[3:0]	SPIA_TX32_BE_0;
wire	[3:0]	SPIA_TX32_BE_1;
wire	[3:0]	SPIA_TX32_BE_2;
wire	[3:0]	SPIA_TX32_BE_3;
wire		SPIA_TX32_CLK_0, SPIA_TX32_CLK_1;
wire		SPIA_TX32_CLK_2, SPIA_TX32_CLK_3;
wire		SPIA_TX32_ERR_0, SPIA_TX32_ERR_1;
wire		SPIA_TX32_ERR_2, SPIA_TX32_ERR_3;
wire		SPIA_TX32_SOP_0, SPIA_TX32_SOP_1;
wire		SPIA_TX32_SOP_2, SPIA_TX32_SOP_3;
wire		SPIA_TX32_EOP_0, SPIA_TX32_EOP_1;
wire		SPIA_TX32_EOP_2, SPIA_TX32_EOP_3;
wire		SPIA_TX32_WE_0, SPIA_TX32_WE_1;
wire		SPIA_TX32_WE_2, SPIA_TX32_WE_3;
wire	[2:0]	SPIA_TX32_ADDR_0, SPIA_TX32_ADDR_1;
wire	[2:0]	SPIA_TX32_ADDR_2, SPIA_TX32_ADDR_3;
wire		SPIA_TX32_WD_CNT_RST_0, SPIA_TX32_WD_CNT_RST_1;
wire		SPIA_TX32_WD_CNT_RST_2, SPIA_TX32_WD_CNT_RST_3;
wire            SPIA_TX32_LINK_DIS_0, SPIA_TX32_LINK_DIS_1;
wire            SPIA_TX32_LINK_DIS_2, SPIA_TX32_LINK_DIS_3;
wire		SPIA_TREFCLK_X8;
wire	[7:0]	SPIA_TX32_PORT_ID ;
wire	[1:0]   SPIA_TX32_STAT;
wire	[3:0]	SPIA_TX32_BURST_VAL;
wire		SPIA_TX32_FIFO_FULL_0, SPIA_TX32_FIFO_FULL_1;
wire		SPIA_TX32_FIFO_FULL_2, SPIA_TX32_FIFO_FULL_3;
wire	[31:0]	SPIB_TX32_DATA_0;
wire	[31:0]	SPIB_TX32_DATA_1;
wire	[31:0]	SPIB_TX32_DATA_2;
wire	[31:0]	SPIB_TX32_DATA_3;
wire	[7:0]	SPIB_TX32_PORT_0;
wire	[7:0]	SPIB_TX32_PORT_1;
wire	[7:0]	SPIB_TX32_PORT_2;
wire	[7:0]	SPIB_TX32_PORT_3;
wire	[3:0]	SPIB_TX32_BE_0;
wire	[3:0]	SPIB_TX32_BE_1;
wire	[3:0]	SPIB_TX32_BE_2;
wire	[3:0]	SPIB_TX32_BE_3;
wire		SPIB_TX32_CLK_2, SPIB_TX32_CLK_3;
wire		SPIB_TX32_ERR_0, SPIB_TX32_ERR_1;
wire		SPIB_TX32_ERR_2, SPIB_TX32_ERR_3;
wire		SPIB_TX32_SOP_0, SPIB_TX32_SOP_1;
wire		SPIB_TX32_SOP_2, SPIB_TX32_SOP_3;
wire		SPIB_TX32_EOP_0, SPIB_TX32_EOP_1;
wire		SPIB_TX32_EOP_2, SPIB_TX32_EOP_3;
wire		SPIB_TX32_WE_0, SPIB_TX32_WE_1;
wire		SPIB_TX32_WE_2, SPIB_TX32_WE_3;
wire	[2:0]	SPIB_TX32_ADDR_0, SPIB_TX32_ADDR_1;
wire	[2:0]	SPIB_TX32_ADDR_2, SPIB_TX32_ADDR_3;
wire		SPIB_TX32_WD_CNT_RST_0, SPIB_TX32_WD_CNT_RST_1;
wire		SPIB_TX32_WD_CNT_RST_2, SPIB_TX32_WD_CNT_RST_3;
wire            SPIB_TX32_LINK_DIS_0, SPIB_TX32_LINK_DIS_1;
wire            SPIB_TX32_LINK_DIS_2, SPIB_TX32_LINK_DIS_3;
wire		SPIB_TREFCLK_X8;
wire	[7:0]	SPIB_TX32_PORT_ID;
wire	[1:0]   SPIB_TX32_STAT;
wire	[3:0]	SPIB_TX32_BURST_VAL;
wire		SPIB_TX32_FIFO_FULL_0, SPIB_TX32_FIFO_FULL_1;
wire		SPIB_TX32_FIFO_FULL_2, SPIB_TX32_FIFO_FULL_3;
wire		ARLSCLK_F;
wire		ATREFCLK_F;
wire		SPI_SATM_A, SPI_DATM_A;
wire	[2:0]	SPI_DLYTAP_A;
wire		FPGA_RESET_S4A;
wire		ASTOP_ON_EOP0, ASTOP_ON_EOP1, ASTOP_ON_EOP2, ASTOP_ON_EOP3;
wire		SYS_RST_N;

wire		BRLSCLK_F;
wire		BTREFCLK_F;
wire		SPI_SATM_B, SPI_DATM_B;
wire		[2:0]	SPI_DLYTAP_B;
wire		FPGA_RESET_S4B;
wire		BSTOP_ON_EOP0, BSTOP_ON_EOP1, BSTOP_ON_EOP2, BSTOP_ON_EOP3;
wire	[73:0]	F_MC_WD;
wire	[31:0]	F_MC_WI;
wire	[31:0]	F_MC_RI;
wire	[71:0]	MC_RD;
//Serdes not used in this version.
//Memory Controller not used in this version.
//-- The following signals  are either test related
//-- or connect to system bus fpsc signals
  wire  DONE;
  wire  GSRN_TOA;
  wire  [17:0] HADDR;
  wire  HBURST;
  wire  HCLK;
  wire  HREADY_IN;
  wire  HRESET_N;
  wire  HSEL;
  wire  [1:0] HSIZE;
  wire  [1:0] HTRANS;
  wire  [35:0] HWDATA;
  wire  HWRITE;
  wire  INITN;
  wire  PWRUPRES;
  wire  TRI_IO;
  wire ASB_EN_SLI;
  wire ASB_IRQ_SLI;
  wire [35:0] HRDATA;
  wire HREADY_OUT;
  wire [1:0] HRESP;

  wire [35:0] us_rdata;//
  wire us_clk;
  wire us_reset;
  wire us_ack;//
  wire us_retry;//
  wire us_err;//
  wire us_irq;//
  wire [35:0] us_wdata;//
  wire [17:0] us_addr;//
  wire us_burst;//
  wire us_rdy;//
  wire us_wr;//
  wire [1:0] us_size;//

  wire fpsc_vlo;
  wire fpsc_vhi;

  wire renb0, rsx0, rsop0, reop0, rprty0, rval0, rerr0;
  wire [1:0] rmod0; 
  wire [31:0] rdat0;
  wire tenb0, tsx0, tsop0, teop0, tprty0, terr0;
  wire [ports-1:0] dtpa0;
  wire stpa0, ptpa0;
  wire [5:0] tadr0; 
  wire [1:0] tmod0; 
  wire [31:0] tdat0;
  wire fifofull0, txbkp0; 
  wire [7:0] tx_portid;

  wire rfclk0_int, rfclk0_int_ph, rfclk0_buf;
  wire rfclk1_int;
  wire rfclk2_int;
  wire rfclk3_int;


`ifdef NUMINT2

  wire rfclk1_int_ph, rfclk1_buf;
  wire renb1, rsx1, rsop1, reop1, rprty1, rval1, rerr1;
  wire [1:0] rmod1; 
  wire [31:0] rdat1;
  wire tenb1, tsx1, tsop1, teop1, tprty1, terr1;
  wire [ports-1:0] dtpa1;
  wire stpa1, ptpa1;
  wire [5:0] tadr1; 
  wire [1:0] tmod1; 
  wire [31:0] tdat1;
  wire fifofull1, txbkp1; 

`endif 

`ifdef NUMINT3

  wire rfclk2_int_ph, rfclk2_buf;
  wire renb2, rsx2, rsop2, reop2, rprty2, rval2, rerr2;
  wire [1:0] rmod2; 
  wire [31:0] rdat2;
  wire tenb2, tsx2, tsop2, teop2, tprty2, terr2;
  wire [ports-1:0] dtpa2;
  wire stpa2, ptpa2;
  wire [5:0] tadr2; 
  wire [1:0] tmod2; 
  wire [31:0] tdat2;
  wire fifofull2, txbkp2; 

`endif 

`ifdef NUMINT4

  wire rfclk3_int_ph, rfclk3_buf;
  wire renb3, rsx3, rsop3, reop3, rprty3, rval3, rerr3;
  wire [1:0] rmod3; 
  wire [31:0] rdat3;
  wire tenb3, tsx3, tsop3, teop3, tprty3, terr3;
  wire [ports-1:0] dtpa3;
  wire stpa3, ptpa3;
  wire [5:0] tadr3; 
  wire [1:0] tmod3; 
  wire [31:0] tdat3;
  wire fifofull3, txbkp3; 

`endif 

  wire rx_re0, rx_re1, rx_re2, rx_re3;
  wire [2:0]   rx_a0, rx_a1, rx_a2, rx_a3;

  wire spia_rx_fifo_empty0;
  wire spia_rx_fifo_empty1;
  wire spia_rx_fifo_empty2;
  wire spia_rx_fifo_empty3;

  wire [39:0]  spia_rxd0;
  wire [39:0]  spia_rxd1;
  wire [39:0]  spia_rxd2;
  wire [39:0]  spia_rxd3;

  wire [7:0]   rx_fpga_port_id;
  wire rx_ext_status_enable;
  wire [1:0]   rx_port_status;
  wire rx_pss_we;

  wire spib_rx_fifo_empty0;
  wire spib_rx_fifo_empty1;
  wire spib_rx_fifo_empty2;
  wire spib_rx_fifo_empty3;

  wire [39:0]  spib_rxd0;
  wire [39:0]  spib_rxd1;
  wire [39:0]  spib_rxd2;
  wire [39:0]  spib_rxd3;

  wire [1:0] txstat;

  wire [7:0] tx_port0;
  wire [7:0] tx_port1;
  wire [7:0] tx_port2;
  wire [7:0] tx_port3;

  wire [38:0] txd0;
  wire [38:0] txd1;
  wire [38:0] txd2;
  wire [38:0] txd3;

  wire tx_we0;
  wire tx_we1;
  wire tx_we2;
  wire tx_we3;

  wire [2:0] tx_a0;
  wire [2:0] tx_a1;
  wire [2:0] tx_a2;
  wire [2:0] tx_a3;

  wire wcntrst0;
  wire wcntrst1;
  wire wcntrst2;
  wire wcntrst3;

  wire sys_reset;
  wire sys_resetn_buf;

//Logic 1/0 instantiations for connection tie-off of unused signals
  VLO fpsc_vlo_inst (.Z(fpsc_vlo));
  VHI fpsc_vhi_inst (.Z(fpsc_vhi));

// -------------------
// DRIVE LINK DISABLES
// -------------------
assign SPIA_TX32_LINK_DIS_0 = 1'b0; 
assign SPIA_TX32_LINK_DIS_1 = 1'b0; 
assign SPIA_TX32_LINK_DIS_2 = 1'b0; 
assign SPIA_TX32_LINK_DIS_3 = 1'b0; 

assign SPIB_TX32_LINK_DIS_0 = 1'b0; 
assign SPIB_TX32_LINK_DIS_1 = 1'b0; 
assign SPIB_TX32_LINK_DIS_2 = 1'b0; 
assign SPIB_TX32_LINK_DIS_3 = 1'b0; 

// drive ASB inputs which are sourced from unused SPI3 interfaces

`ifdef NUMINT2
`else
assign rfclk1_int = 1'b0;
assign rx_re1     = 1'b0;
assign rx_a1      = 3'b0;
assign txd1       = 39'd0;
assign tx_we1     = 1'b0;
assign tx_a1      = 3'd0;
assign wcntrst1   = 1'b0;
assign tx_port1   = 8'd0;
`endif

`ifdef NUMINT3
`else
assign rfclk2_int = 1'b0;
assign rx_re2     = 1'b0;
assign rx_a2      = 3'b0;
assign txd2       = 39'd0;
assign tx_we2     = 1'b0;
assign tx_a2      = 3'd0;
assign wcntrst2   = 1'b0;
assign tx_port2   = 8'd0;
`endif

`ifdef NUMINT4
`else
assign rfclk3_int = 1'b0;
assign rx_re3     = 1'b0;
assign rx_a3      = 3'b0;
assign txd3       = 39'd0;
assign tx_we3     = 1'b0;
assign tx_a3      = 3'd0;
assign wcntrst3   = 1'b0;
assign tx_port3   = 8'd0;
`endif

//asb instance

mycore mycore_inst(
.REXT(REXT),
.REXTN(REXTN),
.REF10(REF10),
.REF14(REF14),
.RESLO(RESLO),
.RESHI(RESHI),
.EXT_1K(EXT_1K),
.ALVCTAP1(ALVCTAP1),
.ALVCTAP2(ALVCTAP2),
.ALVCTAP3(ALVCTAP3),
.ALVCTAP4(ALVCTAP4),
.ALVCTAP5(ALVCTAP5),
.BLVCTAP1(BLVCTAP1),
.BLVCTAP2(BLVCTAP2),
.BLVCTAP3(BLVCTAP3),
.BLVCTAP4(BLVCTAP4),
.BLVCTAP5(BLVCTAP5),

.SPIA_RX32_CLK_0(rfclk0_int),
.SPIA_RX32_CLK_1(rfclk1_int),
.SPIA_RX32_CLK_2(rfclk2_int),
.SPIA_RX32_CLK_3(rfclk3_int),

.SPIA_RX32_RD_0(rx_re0),
.SPIA_RX32_RD_1(rx_re1),
.SPIA_RX32_RD_2(rx_re2),
.SPIA_RX32_RD_3(rx_re3),

.SPIA_RX32_ADDR_0(rx_a0),
.SPIA_RX32_ADDR_1(rx_a1),
.SPIA_RX32_ADDR_2(rx_a2),
.SPIA_RX32_ADDR_3(rx_a3),

.SPIA_RX32_PORT_ID(rx_fpga_port_id),
.SPIA_RX32_EXT_STAT_EN(rx_ext_status_enable),
.SPIA_RX32_STAT(rx_port_status),
.SPIA_RX32_PSS_WE(rx_pss_we),
.SPIA_RX32_PSS_CLK(~rfclk0_int),

.SPIA_RX32_DATA_0(spia_rxd0[31:0]),
.SPIA_RX32_DATA_1(spia_rxd1[31:0]),
.SPIA_RX32_DATA_2(spia_rxd2[31:0]),
.SPIA_RX32_DATA_3(spia_rxd3[31:0]),

.SPIA_RX32_SOP_0(spia_rxd0[32]),
.SPIA_RX32_SOP_1(spia_rxd1[32]),
.SPIA_RX32_SOP_2(spia_rxd2[32]),
.SPIA_RX32_SOP_3(spia_rxd3[32]),

.SPIA_RX32_EOP_0(spia_rxd0[33]),
.SPIA_RX32_EOP_1(spia_rxd1[33]),
.SPIA_RX32_EOP_2(spia_rxd2[33]),
.SPIA_RX32_EOP_3(spia_rxd3[33]),

.SPIA_RX32_BE_0(spia_rxd0[37:34]),
.SPIA_RX32_BE_1(spia_rxd1[37:34]),
.SPIA_RX32_BE_2(spia_rxd2[37:34]),
.SPIA_RX32_BE_3(spia_rxd3[37:34]),

.SPIA_RX32_ERR_0(spia_rxd0[38]),
.SPIA_RX32_ERR_1(spia_rxd1[38]),
.SPIA_RX32_ERR_2(spia_rxd2[38]),
.SPIA_RX32_ERR_3(spia_rxd3[38]),

.SPIA_RX32_CTL_0(spia_rxd0[39]),
.SPIA_RX32_CTL_1(spia_rxd1[39]),
.SPIA_RX32_CTL_2(spia_rxd2[39]),
.SPIA_RX32_CTL_3(spia_rxd3[39]),

//.SPIA_RX32_REF_CLK(SPIA_RX32_REF_CLK),
.SPIA_RX32_FIFO_EMPTY_0(spia_rx_fifo_empty0),
.SPIA_RX32_FIFO_EMPTY_1(spia_rx_fifo_empty1),
.SPIA_RX32_FIFO_EMPTY_2(spia_rx_fifo_empty2),
.SPIA_RX32_FIFO_EMPTY_3(spia_rx_fifo_empty3),

.SPIB_RX32_CLK_0(1'b0),		// mph
.SPIB_RX32_CLK_1(1'b0),		// mph
.SPIB_RX32_CLK_2(1'b0),		// mph
.SPIB_RX32_CLK_3(1'b0),		// mph

.SPIB_RX32_RD_0(1'b0),
.SPIB_RX32_RD_1(1'b0),
.SPIB_RX32_RD_2(1'b0),
.SPIB_RX32_RD_3(1'b0),

.SPIB_RX32_ADDR_0(3'b000),
.SPIB_RX32_ADDR_1(3'b000),
.SPIB_RX32_ADDR_2(3'b000),
.SPIB_RX32_ADDR_3(3'b000),

.SPIB_RX32_PORT_ID(rx_fpga_port_id),
.SPIB_RX32_EXT_STAT_EN(rx_ext_status_enable),
.SPIB_RX32_STAT(rx_port_status),
.SPIB_RX32_PSS_WE(rx_pss_we),
.SPIB_RX32_PSS_CLK(~rfclk0_int),

.SPIB_RX32_DATA_0(spib_rxd0[31:0]),
.SPIB_RX32_DATA_1(spib_rxd1[31:0]),
.SPIB_RX32_DATA_2(spib_rxd2[31:0]),
.SPIB_RX32_DATA_3(spib_rxd3[31:0]),

.SPIB_RX32_SOP_0(spib_rxd0[32]),
.SPIB_RX32_SOP_1(spib_rxd1[32]),
.SPIB_RX32_SOP_2(spib_rxd2[32]),
.SPIB_RX32_SOP_3(spib_rxd3[32]),

.SPIB_RX32_EOP_0(spib_rxd0[33]),
.SPIB_RX32_EOP_1(spib_rxd1[33]),
.SPIB_RX32_EOP_2(spib_rxd2[33]),
.SPIB_RX32_EOP_3(spib_rxd3[33]),

.SPIB_RX32_BE_0(spib_rxd0[37:34]),
.SPIB_RX32_BE_1(spib_rxd1[37:34]),
.SPIB_RX32_BE_2(spib_rxd2[37:34]),
.SPIB_RX32_BE_3(spib_rxd3[37:34]),

.SPIB_RX32_ERR_0(spib_rxd0[38]),
.SPIB_RX32_ERR_1(spib_rxd1[38]),
.SPIB_RX32_ERR_2(spib_rxd2[38]),
.SPIB_RX32_ERR_3(spib_rxd3[38]),

.SPIB_RX32_CTL_0(spib_rxd0[39]),
.SPIB_RX32_CTL_1(spib_rxd1[39]),
.SPIB_RX32_CTL_2(spib_rxd2[39]),
.SPIB_RX32_CTL_3(spib_rxd3[39]),

//.SPIB_RX32_REF_CLK(SPIB_RX32_REF_CLK),
.SPIB_RX32_FIFO_EMPTY_0(spib_rx_fifo_empty0),
.SPIB_RX32_FIFO_EMPTY_1(spib_rx_fifo_empty1),
.SPIB_RX32_FIFO_EMPTY_2(spib_rx_fifo_empty2),
.SPIB_RX32_FIFO_EMPTY_3(spib_rx_fifo_empty3),

.SPIA_TX32_PORT_0(tx_port0),
.SPIA_TX32_PORT_1(tx_port1),
.SPIA_TX32_PORT_2(tx_port2),
.SPIA_TX32_PORT_3(tx_port3),

.SPIA_TX32_CLK_0(rfclk0_int),
.SPIA_TX32_CLK_1(rfclk1_int),
.SPIA_TX32_CLK_2(rfclk2_int),
.SPIA_TX32_CLK_3(rfclk3_int),

.SPIA_TX32_DATA_0(txd0[31:0]),
.SPIA_TX32_DATA_1(txd1[31:0]),
.SPIA_TX32_DATA_2(txd2[31:0]),
.SPIA_TX32_DATA_3(txd3[31:0]),

.SPIA_TX32_SOP_0(txd0[32]),
.SPIA_TX32_SOP_1(txd1[32]),
.SPIA_TX32_SOP_2(txd2[32]),
.SPIA_TX32_SOP_3(txd3[32]),

.SPIA_TX32_EOP_0(txd0[33]),
.SPIA_TX32_EOP_1(txd1[33]),
.SPIA_TX32_EOP_2(txd2[33] ),
.SPIA_TX32_EOP_3(txd3[33]),

.SPIA_TX32_BE_0(txd0[37:34]),
.SPIA_TX32_BE_1(txd1[37:34]),
.SPIA_TX32_BE_2(txd2[37:34]),
.SPIA_TX32_BE_3(txd3[37:34]),

.SPIA_TX32_ERR_0(txd0[38]),
.SPIA_TX32_ERR_1(txd1[38]),
.SPIA_TX32_ERR_2(txd2[38]),
.SPIA_TX32_ERR_3(txd3[38]),

.SPIA_TX32_WE_0(tx_we0),
.SPIA_TX32_WE_1(tx_we1 ),
.SPIA_TX32_WE_2(tx_we2 ),
.SPIA_TX32_WE_3(tx_we3),

.SPIA_TX32_ADDR_0(tx_a0),
.SPIA_TX32_ADDR_1(tx_a1),
.SPIA_TX32_ADDR_2(tx_a2),
.SPIA_TX32_ADDR_3(tx_a3),

.SPIA_TX32_WD_CNT_RST_0(wcntrst0),
.SPIA_TX32_WD_CNT_RST_1(wcntrst1),
.SPIA_TX32_WD_CNT_RST_2(wcntrst2),
.SPIA_TX32_WD_CNT_RST_3(wcntrst3),

.SPIA_TX32_LINK_DIS_0(SPIA_TX32_LINK_DIS_0),
.SPIA_TX32_LINK_DIS_1(SPIA_TX32_LINK_DIS_1),
.SPIA_TX32_LINK_DIS_2(SPIA_TX32_LINK_DIS_2),
.SPIA_TX32_LINK_DIS_3(SPIA_TX32_LINK_DIS_3),

.SPIA_TX32_PORT_ID(tx_portid),
.SPIA_TX32_STAT(txstat),
.SPIA_TX32_BURST_VAL(SPIA_TX32_BURST_VAL),

.SPIA_TX32_FIFO_FULL_0(fifofull0),
.SPIA_TX32_FIFO_FULL_1(fifofull1),
.SPIA_TX32_FIFO_FULL_2(fifofull2),
.SPIA_TX32_FIFO_FULL_3(fifofull3),

//.SPIA_TX32_REF_CLK(SPIA_TX32_REF_CLK),

.SPIB_TX32_DATA_0(SPIB_TX32_DATA_0),
.SPIB_TX32_DATA_1(SPIB_TX32_DATA_1),
.SPIB_TX32_DATA_2(SPIB_TX32_DATA_2),
.SPIB_TX32_DATA_3(SPIB_TX32_DATA_3),
.SPIB_TX32_PORT_0(SPIB_TX32_PORT_0),
.SPIB_TX32_PORT_1(SPIB_TX32_PORT_1),
.SPIB_TX32_PORT_2(SPIB_TX32_PORT_2),
.SPIB_TX32_PORT_3(SPIB_TX32_PORT_3),
.SPIB_TX32_BE_0(SPIB_TX32_BE_0),
.SPIB_TX32_BE_1(SPIB_TX32_BE_1),
.SPIB_TX32_BE_2(SPIB_TX32_BE_2),
.SPIB_TX32_BE_3(SPIB_TX32_BE_3),
.SPIB_TX32_CLK_0(1'b0),		// mph
.SPIB_TX32_CLK_1(1'b0),		// mph
.SPIB_TX32_CLK_2(1'b0),		// mph
.SPIB_TX32_CLK_3(1'b0),		// mph
.SPIB_TX32_ERR_0(SPIB_TX32_ERR_0),
.SPIB_TX32_ERR_1(SPIB_TX32_ERR_1),
.SPIB_TX32_ERR_2(SPIB_TX32_ERR_2),
.SPIB_TX32_ERR_3(SPIB_TX32_ERR_3),
.SPIB_TX32_SOP_0(SPIB_TX32_SOP_0),
.SPIB_TX32_SOP_1(SPIB_TX32_SOP_1),
.SPIB_TX32_SOP_2(SPIB_TX32_SOP_2),
.SPIB_TX32_SOP_3(SPIB_TX32_SOP_3),
.SPIB_TX32_EOP_0(SPIB_TX32_EOP_0),
.SPIB_TX32_EOP_1(SPIB_TX32_EOP_1),
.SPIB_TX32_EOP_2(SPIB_TX32_EOP_2 ),
.SPIB_TX32_EOP_3(SPIB_TX32_EOP_3),
.SPIB_TX32_WE_0(SPIB_TX32_WE_0),
.SPIB_TX32_WE_1(SPIB_TX32_WE_1 ),
.SPIB_TX32_WE_2(SPIB_TX32_WE_2 ),
.SPIB_TX32_WE_3(SPIB_TX32_WE_3),
.SPIB_TX32_ADDR_0(SPIB_TX32_ADDR_0),
.SPIB_TX32_ADDR_1(SPIB_TX32_ADDR_1),
.SPIB_TX32_ADDR_2(SPIB_TX32_ADDR_2),
.SPIB_TX32_ADDR_3(SPIB_TX32_ADDR_3),
.SPIB_TX32_WD_CNT_RST_0(SPIB_TX32_WD_CNT_RST_0),
.SPIB_TX32_WD_CNT_RST_1(SPIB_TX32_WD_CNT_RST_1),
.SPIB_TX32_WD_CNT_RST_2(SPIB_TX32_WD_CNT_RST_2),
.SPIB_TX32_WD_CNT_RST_3(SPIB_TX32_WD_CNT_RST_3),
.SPIB_TX32_LINK_DIS_0(SPIB_TX32_LINK_DIS_0),
.SPIB_TX32_LINK_DIS_1(SPIB_TX32_LINK_DIS_1),
.SPIB_TX32_LINK_DIS_2(SPIB_TX32_LINK_DIS_2),
.SPIB_TX32_LINK_DIS_3(SPIB_TX32_LINK_DIS_3),
.SPIB_TX32_PORT_ID(SPIB_TX32_PORT_ID ),
.SPIB_TX32_STAT(SPIB_TX32_STAT),
.SPIB_TX32_BURST_VAL(SPIB_TX32_BURST_VAL),
.SPIB_TX32_FIFO_FULL_0(SPIB_TX32_FIFO_FULL_0),
.SPIB_TX32_FIFO_FULL_1(SPIB_TX32_FIFO_FULL_1),
.SPIB_TX32_FIFO_FULL_2(SPIB_TX32_FIFO_FULL_2),
.SPIB_TX32_FIFO_FULL_3(SPIB_TX32_FIFO_FULL_3),
//.SPIB_TX32_REF_CLK(SPIB_TX32_REF_CLK),
.ARDATN(ARDATN),
.ARDATP(ARDATP),
.ARCTLN(ARCTLN),
.ARCTLP(ARCTLP),
.ARDCLKN(ARDCLKN),
.ARDCLKP(ARDCLKP),
.RSCLKA(RSCLKA),
.RSTATA(RSTATA),
.ARSCLKN(ARSCLKN),
.ARSCLKP(ARSCLKP),
.ARSTATN(ARSTATN),
.ARSTATP(ARSTATP),
.BRDATN(BRDATN),
.BRDATP(BRDATP),
.BRCTLN(BRCTLN),
.BRCTLP(BRCTLP),
.BRDCLKN(BRDCLKN),
.BRDCLKP(BRDCLKP),
.RSCLKB(RSCLKB),
.RSTATB(RSTATB),
.BRSCLKN(BRSCLKN),
.BRSCLKP(BRSCLKP),
.BRSTATN(BRSTATN),
.BRSTATP(BRSTATP),
.ATDATN(ATDATN),
.ATDATP(ATDATP),
.ATCTLN(ATCTLN),
.ATCTLP(ATCTLP),
.ATDCLKN(ATDCLKN),
.ATDCLKP(ATDCLKP),
.ATREFCLK(ATREFCLK),
.TSCLKA(TSCLKA),
.TSTATA(TSTATA),
.ATSCLKN(ATSCLKN),
.ATSCLKP(ATSCLKP),
.ATSTATN(ATSTATN),
.ATSTATP(ATSTATP),
.BTDATN(BTDATN),
.BTDATP(BTDATP),
.BTCTLN(BTCTLN),
.BTCTLP(BTCTLP),
.BTDCLKN(BTDCLKN),
.BTDCLKP(BTDCLKP),
.BTREFCLK(BTREFCLK),
.TSCLKB(TSCLKB),
.TSTATB(TSTATB),
.BTSCLKN(BTSCLKN),
.BTSCLKP(BTSCLKP),
.BTSTATN(BTSTATN),
.BTSTATP(BTSTATP),
// .CV_SELA(CV_SELA),
// .CV_SELB(CV_SELB),
// .CV_SELC(CV_SELC),
// .CV_SELD(CV_SELD),
.DONE(DONE),
.GSRN_TOA(GSRN_TOA),
.HADDR(HADDR),
.HBURST(HBURST),
.HCLK(HCLK),
.HDINN_A(HDINN_A),
.HDINN_B(HDINN_B),
.HDINN_C(HDINN_C),
.HDINN_D(HDINN_D),
.HDINP_A(HDINP_A),
.HDINP_B(HDINP_B),
.HDINP_C(HDINP_C),
.HDINP_D(HDINP_D),
.HREADY_IN(HREADY_IN),
.HRESET_N(HRESET_N),
.HSEL(HSEL),
.HSIZE(HSIZE),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HWRITE(HWRITE),
.PWRUPRES(PWRUPRES),
.REFCLKN(REFCLKN),
.REFCLKP(REFCLKP),
// .RSYS_CLK_AB(RSYS_CLK_AB),
// .RSYS_CLK_CD(RSYS_CLK_CD),
.SYS_RST_N(sys_rst_n),      // mph
// .SYS_RST_N(sys_reset),      // mph
.ARLSCLK_F(ARLSCLK_F),
.BRLSCLK_F(BRLSCLK_F),
.ATREFCLK_F(ATREFCLK_F),
.BTREFCLK_F(BTREFCLK_F),
.SPI_SATM_A(1'b0),       // mph
.SPI_SATM_B(1'b0),       // mph
.SPI_DATM_A(1'b0),       // mph
.SPI_DATM_B(1'b0),       // mph
.SPI_DLYTAP_A(3'b000),       // mph
.SPI_DLYTAP_B(3'b000),       // mph
// .TBIT9A(TBIT9A),
// .TBIT9B(TBIT9B),
// .TBIT9C(TBIT9C),
// .TBIT9D(TBIT9D),
// .TCOMMAA(TCOMMAA),
// .TCOMMAB(TCOMMAB),
// .TCOMMAC(TCOMMAC),
// .TCOMMAD(TCOMMAD),
.TRI_IO(TRI_IO),
// .TSYS_CLK_A(TSYS_CLK_A),
// .TSYS_CLK_B(TSYS_CLK_B),
// .TSYS_CLK_C(TSYS_CLK_C),
// .TSYS_CLK_D(TSYS_CLK_D),
// .TWDA(TWDA),
// .TWDB(TWDB),
// .TWDC(TWDC),
// .TWDD(TWDD),
// .SERDES_LS_LOOP_MODE(SERDES_LS_LOOP_MODE),
.ASB_EN_SLI(ASB_EN_SLI),
.ASB_IRQ_SLI(ASB_IRQ_SLI),
.HDOUTN_A(HDOUTN_A),
.HDOUTN_B(HDOUTN_B),
.HDOUTN_C(HDOUTN_C),
.HDOUTN_D(HDOUTN_D),
.HDOUTP_A(HDOUTP_A),
.HDOUTP_B(HDOUTP_B),
.HDOUTP_C(HDOUTP_C),
.HDOUTP_D(HDOUTP_D),
.HRDATA(HRDATA),
.HREADY_OUT(HREADY_OUT),
.HRESP(HRESP),
// .RCK78(RCK78),
// .RWCKA(RWCKA),
// .RWCKB(RWCKB),
// .RWCKC(RWCKC),
// .RWCKD(RWCKD),
// .TCK78(TCK78),
.PMIC(PMIC),
.PMICN(PMICN),
.PMIQ(PMIQ),
.MCREFCLK(MCREFCLK),
.PMIA(PMIA),
.PMID(PMID),
.PMIWN(PMIWN),
.PMIRN(PMIRN),
.PMIK(PMIK),
.PMIKN(PMIKN),
.RESETN(RESETN),
.F_MC_WD(F_MC_WD),
.F_MC_WI(F_MC_WI),
.F_MC_RI(F_MC_RI),
.F_MC_WCLK(F_MC_WCLK),
.F_MC_RCLK(F_MC_RCLK),
.F_MC_WIFIFO_WE(F_MC_WIFIFO_WE),
.F_MC_WDFIFO_WE(F_MC_WDFIFO_WE),
.F_MC_RIFIFO_WE(F_MC_RIFIFO_WE),
.F_MC_RDFIFO_RE(F_MC_RDFIFO_RE),
.F_MC_REFCLK(F_MC_REFCLK),
.MC_RD(MC_RD),
.MC_RDFIFO_EMPTY(MC_RDFIFO_EMPTY),
.MC_RIFIFO_FULL(MC_RIFIFO_FULL),
.MC_WDFIFO_FULL(MC_WDFIFO_FULL),
.MC_WIFIFO_FULL(MC_WIFIFO_FULL),
.MC_SYSCLK(MC_SYSCLK),
// .FPGA_RESET_FC(sys_reset),	// mph
.FPGA_RESET_MC(sys_reset),	// mph
.FPGA_RESET_S4A(sys_reset),	// mph
.FPGA_RESET_S4B(sys_reset),	// mph
.PDN(PDN),
.TESTMDN(TESTMDN),
.TRISTN(TRISTN),
.TESTCLK(TESTCLK),
.ASTOP_ON_EOP0(fpsc_vlo),
.ASTOP_ON_EOP1(fpsc_vlo),
.ASTOP_ON_EOP2(fpsc_vlo),
.ASTOP_ON_EOP3(fpsc_vlo),
.BSTOP_ON_EOP0(fpsc_vlo),
.BSTOP_ON_EOP1(fpsc_vlo),
.BSTOP_ON_EOP2(fpsc_vlo),
.BSTOP_ON_EOP3(fpsc_vlo),

.SPIA_TREFCLK_X8(SPIA_TREFCLK_X8),
.SPIB_TREFCLK_X8(SPIB_TREFCLK_X8)

);

//-- Component definition for the system bus.  This system 
//-- bus module contains an FPSC interface and MPI.  
//-- If more interfaces are required for your design you will 
//-- need to add ports to this component definition.  The 
//-- system bus module should be created using the SCUBA wizard.

sysbus_fpsc sysbus_inst (
    .mpi_clk(MPI_CLK), 
    .mpi_rdwr_n(MPI_RDWR_N), 
    .mpi_strbn(MPI_STRBN), 
    .mpi_tsz(MPI_TSZ), 
    .mpi_burst(MPI_BURST), 
    .mpi_bdip(MPI_BDIP), 
    .cs0n(CS0N), 
    .cs1(CS1), 
    .mpi_addr(MPI_ADDR), 
    .mpi_data(MPI_DATA), 
//    .mpi_parity(MPI_PARITY), 
    .mpi_ta(MPI_TA), 
    .mpi_retry(MPI_RETRY), 
    .mpi_tea(MPI_TEA), 
    .mpi_irq(MPI_IRQ), 
    .us_rdata(us_rdata), 
    .us_clk(USR_CLK),
    .us_reset(sys_reset),
    .us_ack(us_ack),
    .us_retry(us_retry),
    .us_err(us_err),
    .us_irq(us_irq),
    .us_wdata(us_wdata),
    .us_addr(us_addr),
    .us_burst(us_burst),
    .us_rdy(us_rdy),
    .us_wr(us_wr),
    .us_size(us_size),
    .fpsc_in_addr({fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi,
                   fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi,
                   fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi, fpsc_vhi,
                   fpsc_vhi, fpsc_vhi, fpsc_vhi}),
    .fpsc_in_trans({fpsc_vlo, fpsc_vlo}), 
    .fpsc_in_write(fpsc_vlo), 
    .fpsc_in_size({fpsc_vlo, fpsc_vlo}), 
    .fpsc_in_burst(fpsc_vlo), 
    .fpsc_in_wdata({fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, 
		   fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo, fpsc_vlo}), 
    .fpsc_in_busreq(fpsc_vlo), 
    .fpsc_in_lock(fpsc_vlo), 
    .fpsc_in_rdata({HRDATA[35],HRDATA[34],HRDATA[33],
		    HRDATA[32],HRDATA[31],HRDATA[30],
		    HRDATA[29],HRDATA[28],HRDATA[27],
		    HRDATA[26],HRDATA[25],HRDATA[24],
    		    HRDATA[23],HRDATA[22],HRDATA[21],
		    HRDATA[20],HRDATA[19],HRDATA[18],
		    HRDATA[17],HRDATA[16],HRDATA[15],
		    HRDATA[14],HRDATA[13],HRDATA[12],
    		    HRDATA[11],HRDATA[10],HRDATA[9],
		    HRDATA[8],HRDATA[7],HRDATA[6],
		    HRDATA[5],HRDATA[4],HRDATA[3],
		    HRDATA[2],HRDATA[1],HRDATA[0]}),
    .fpsc_in_ready_out(HREADY_OUT), 
    .fpsc_in_resp({HRESP[1],HRESP[0]}), 
    .fpsc_clk(fpsc_vlo), 
    .fpsc_gsr(fpsc_vlo), 
    .fpsc_en_sli(ASB_EN_SLI), 
    .fpsc_irq_mri(fpsc_vlo), 
    .fpsc_irq_sli(ASB_IRQ_SLI), 
    .fpsc_out_mclk(), 
    .fpsc_out_mrstn(), 
    .fpsc_out_ready(), 
    .fpsc_out_resp(), 
    .fpsc_out_grant(), 
    .fpsc_out_rdata(), 
    .fpsc_out_sclk(HCLK), 
    .fpsc_out_srstn(HRESET_N), 
    .fpsc_out_addr({HADDR[17],HADDR[16],HADDR[15],
		    HADDR[14],HADDR[13],HADDR[12],
		    HADDR[11],HADDR[10],HADDR[9],
		    HADDR[8],HADDR[7],HADDR[6],
		    HADDR[5],HADDR[4],HADDR[3],
		    HADDR[2],HADDR[1],HADDR[0]}), 
    .fpsc_out_trans({HTRANS[1],HTRANS[0]}), 
    .fpsc_out_write(HWRITE), 
    .fpsc_out_size({HSIZE[1],HSIZE[0]}), 
    .fpsc_out_wdata        ({HWDATA[35],HWDATA[34],HWDATA[33],
                          HWDATA[32],HWDATA[31],HWDATA[30],
                          HWDATA[29],HWDATA[28],HWDATA[27],
                          HWDATA[26],HWDATA[25],HWDATA[24],
                          HWDATA[23],HWDATA[22],HWDATA[21],
                          HWDATA[20],HWDATA[19],HWDATA[18],
                          HWDATA[17],HWDATA[16],HWDATA[15],
                          HWDATA[14],HWDATA[13],HWDATA[12],
                          HWDATA[11],HWDATA[10],HWDATA[9],
                          HWDATA[8],HWDATA[7],HWDATA[6],
                          HWDATA[5],HWDATA[4],HWDATA[3],
                          HWDATA[2],HWDATA[1],HWDATA[0]}),
    .fpsc_out_burst(HBURST), 
    .fpsc_out_sel(HSEL), 
    .fpsc_out_ready_in(HREADY_IN), 
    .fpsc_out_asb_irq(), 
    .fpsc_pwrupres(PWRUPRES), 
    .fpsc_initn(INITN), 
    .fpsc_trion(TRI_IO), 
    .fpsc_done(DONE), 
    .fpsc_gsrn(GSRN_TOA), 
    .usr_clk(USR_CLK), 
    .usr_irq_general(USR_IRQ_GENERAL), 
    .usr_irq(USR_IRQ)
    );

// Instantiation of quad-SPI3 bridge for the FPGA section.

IBM BUF_sys_resetn (.I(sys_resetn), .O(sys_resetn_buf));
INV INV_sys_reset (.A(sys_resetn_buf), .Z(sys_reset));


// Instantiation of PLLs and clock buffers

IBM IBM_rfclk0     (.I(rfclk0), .O(rfclk0_buf));

rfclk_pll_ph rfclk_pll0(

    .clk              (rfclk0_buf),
    .fb               (rfclk0_int),
    .mclk             (rfclk0_int),
    .nclk             (rfclk0_int_ph),
    .intfb            (),
    .lock             ()
);


`ifdef NUMINT2

IBM IBM_rfclk1     (.I(rfclk1), .O(rfclk1_buf));

rfclk_pll_ph rfclk_pll1(

    .clk              (rfclk1_buf),
    .fb               (rfclk1_int),
    .mclk             (rfclk1_int),
    .nclk             (rfclk1_int_ph),
    .intfb            (),
    .lock             ()
);
`endif

`ifdef NUMINT3

IBM IBM_rfclk2     (.I(rfclk2), .O(rfclk2_buf));

rfclk_hpll_ph rfclk_pll2(

    .clk              (rfclk2_buf),
    .fb               (rfclk2_int),
    .mclk             (rfclk2_int),
    .nclk             (rfclk2_int_ph),
    .intfb            (),
    .lock             ()
);
`endif

`ifdef NUMINT4

IBM IBM_rfclk3     (.I(rfclk3), .O(rfclk3_buf));

rfclk_hpll_ph rfclk_pll3(

    .clk              (rfclk3_buf),
    .fb               (rfclk3_int),
    .mclk             (rfclk3_int),
    .nclk             (rfclk3_int_ph),
    .intfb            (),
    .lock             ()
);
`endif


spi_324p_o4_1_001 qspi3_u(

     .sys_reset         (sys_reset),

     .rfclk0_int        (rfclk0_int),
     .rfclk0_int_ph     (rfclk0_int_ph),
     .renb0             (renb0),
     .renb_a0           (renb_a0),
     .renb_b0           (renb_b0),
     .rsx0              (rsx0),
     .rsop0             (rsop0),
     .reop0             (reop0),
     .rprty0            (rprty0),
     .rval0             (rval0),
     .rerr0             (rerr0),
     .rmod0             (rmod0),
     .rdat0             (rdat0),

     .rx_re0            (rx_re0),
     .rx_a0             (rx_a0),
     .rx_fifo_empty0    (spia_rx_fifo_empty0),
     .rxd0              (spia_rxd0),

     .tenb0             (tenb0),
     .tdat0             (tdat0),
     .tmod0             (tmod0),
     .tprty0            (tprty0),
     .tsop0             (tsop0),
     .teop0             (teop0),
     .terr0             (terr0),
     .tsx0              (tsx0),
     .dtpa0             (dtpa0),
     .stpa0             (stpa0),
     .ptpa0             (ptpa0),
     .tadr0             (tadr0),

     .txd0              (txd0),
     .tx_we0            (tx_we0),
     .tx_a0             (tx_a0),
     .wcntrst0          (wcntrst0),
     .fifofull0         (fifofull0),
     .tx_port0          (tx_port0),
     .tx_portid0        (tx_portid),
     .txbkp0            (txbkp0),
     .txstat0           (txstat),

`ifdef NUMINT2

     .rfclk1_int        (rfclk1_int),
     .rfclk1_int_ph     (rfclk1_int_ph),
     .renb1             (renb1),
     .renb_a1           (renb_a1),
     .renb_b1           (renb_b1),
     .rsx1              (rsx1),
     .rsop1             (rsop1),
     .reop1             (reop1),
     .rprty1            (rprty1),
     .rval1             (rval1),
     .rerr1             (rerr1),
     .rmod1             (rmod1),
     .rdat1             (rdat1),

     .rx_re1            (rx_re1),
     .rx_a1             (rx_a1),
     .rx_fifo_empty1    (spia_rx_fifo_empty1),
     .rxd1              (spia_rxd1),

     .tenb1             (tenb1),
     .tdat1             (tdat1),
     .tmod1             (tmod1),
     .tprty1            (tprty1),
     .tsop1             (tsop1),
     .teop1             (teop1),
     .terr1             (terr1),
     .tsx1              (tsx1),
     .dtpa1             (dtpa1),
     .stpa1             (stpa1),
     .ptpa1             (ptpa1),
     .tadr1             (tadr1),

     .txd1              (txd1),
     .tx_we1            (tx_we1),
     .tx_a1             (tx_a1),
     .wcntrst1          (wcntrst1),
     .fifofull1         (fifofull1),
     .tx_port1          (tx_port1),
     .tx_portid1        (tx_portid),
     .txbkp1            (txbkp1),
     .txstat1           (txstat),

`endif 

`ifdef NUMINT3

     .rfclk2_int        (rfclk2_int),
     .rfclk2_int_ph     (rfclk2_int_ph),
     .renb2             (renb2),
     .renb_a2           (renb_a2),
     .renb_b2           (renb_b2),
     .rsx2              (rsx2),
     .rsop2             (rsop2),
     .reop2             (reop2),
     .rprty2            (rprty2),
     .rval2             (rval2),
     .rerr2             (rerr2),
     .rmod2             (rmod2),
     .rdat2             (rdat2),

     .rx_re2            (rx_re2),
     .rx_a2             (rx_a2),
     .rx_fifo_empty2    (spia_rx_fifo_empty2),
     .rxd2              (spia_rxd2),

     .tenb2             (tenb2),
     .tdat2             (tdat2),
     .tmod2             (tmod2),
     .tprty2            (tprty2),
     .tsop2             (tsop2),
     .teop2             (teop2),
     .terr2             (terr2),
     .tsx2              (tsx2),
     .dtpa2             (dtpa2),
     .stpa2             (stpa2),
     .ptpa2             (ptpa2),
     .tadr2             (tadr2),

     .txd2              (txd2),
     .tx_we2            (tx_we2),
     .tx_a2             (tx_a2),
     .wcntrst2          (wcntrst2),
     .fifofull2         (fifofull2),
     .tx_port2          (tx_port2),
     .tx_portid2        (tx_portid),
     .txbkp2            (txbkp2),
     .txstat2           (txstat),

`endif 

`ifdef NUMINT4

     .rfclk3_int        (rfclk3_int),
     .rfclk3_int_ph     (rfclk3_int_ph),
     .renb3             (renb3),
     .renb_a3           (renb_a3),
     .renb_b3           (renb_b3),
     .rsx3              (rsx3),
     .rsop3             (rsop3),
     .reop3             (reop3),
     .rprty3            (rprty3),
     .rval3             (rval3),
     .rerr3             (rerr3),
     .rmod3             (rmod3),
     .rdat3             (rdat3),

     .rx_re3            (rx_re3),
     .rx_a3             (rx_a3),
     .rx_fifo_empty3    (spia_rx_fifo_empty3),
     .rxd3              (spia_rxd3),

     .tenb3             (tenb3),
     .tdat3             (tdat3),
     .tmod3             (tmod3),
     .tprty3            (tprty3),
     .tsop3             (tsop3),
     .teop3             (teop3),
     .terr3             (terr3),
     .tsx3              (tsx3),
     .dtpa3             (dtpa3),
     .stpa3             (stpa3),
     .ptpa3             (ptpa3),
     .tadr3             (tadr3),

     .txd3              (txd3),
     .tx_we3            (tx_we3),
     .tx_a3             (tx_a3),
     .wcntrst3          (wcntrst3),
     .fifofull3         (fifofull3),
     .tx_port3          (tx_port3),
     .tx_portid3        (tx_portid),
     .txbkp3            (txbkp3),
     .txstat3           (txstat),

`endif 
     
     .mpi_clk           (USR_CLK),
     .us_rdata          (us_rdata),
     .us_wdata          (us_wdata),
     .us_addr           (us_addr),
     .us_wr             (us_wr),
     .us_ack            (us_ack),
     .us_err            (us_err),
     .us_rdy            (us_rdy),
     .us_retry          (us_retry),
     .us_irq            (us_irq),
     .us_burst          (us_burst),
     .us_size           (us_size),
     
     .rx_ext_status_enable (rx_ext_status_enable),
     .rx_fpga_port_id      (rx_fpga_port_id),
     .rx_port_status       (rx_port_status),
     .rx_pss_we            (rx_pss_we)
);

endmodule

