///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor
// Corporation.
// The entire notice above must be reproduced on all authorized
// copies and copies may only be made to the extent permitted
// by a licensing agreement from Lattice Semiconductor Corporation.
//

// ====================================================================
// File Details
// ====================================================================
// Project              :       ORSPII
// Filename             :       footer.v
// Author               :       Ben_Kerr,bkerr@latticesemi.com
// Created on           :       Tuesday July 09 2002 (WW27)
// Last Modified By     :       $Author: bkerr $
// Last Modified On     :       $Date: Tue Oct 22 07:35:05 2002 $ 
// Revision             :       $Revision: 1.19 $
// Status               :       Development
// Dependencies         :       reg_desc.v, addr_params.v
//=====================================================================

//=====================================================================
// Description          :
//=====================================================================
// Footer file used at the bottom of the automatically created toptest.v
//
// After running the simany_ph1 script, toptest.v is created
// This file is built from the following files:
//
//   +-----------------------------------+
//   | `defines generated by script      |  Time of day, user information & configuration feedback
//   +-----------------------------------+
//   |                                   |  top level module statement, global variables
//   |             header.v              |  module instantiations, clock & reset generation
//   |                                   |  initial ....
//   +-----------------------------------+
//   |                                   |    DUT register settings (configuration specific)
//   |     SFnn - from command line      |
//   |                                   |
//   +-----------------------------------+
//   |                                   |    DUT memory configurations (configuration specific)
//   |     Mnn - from command line       |
//   |                                   |
//   +-----------------------------------+
//   |                                   |    Task calls to configure DUT
//   |             body.v                |    Task calls to enable checkers
//   |                                   |    Task calls to perform data format tests
//   +-----------------------------------+
//   |                                   |    Report pass/fail
//   |       footer.v (this file)        |    `include common tasks
//   |                                   |  endmodule
//   +-----------------------------------+
//
//
//=====================================================================

//=====================================================================
// Revision History
//=====================================================================
// $Log: footer.v.rca $
// 
//  Revision: 1.19 Tue Oct 22 07:35:05 2002 bkerr
//  Changed clear_stats task to clear rx_fpga_bfm Rx eop counters that were missed
// 
//  Revision: 1.18 Tue Oct 15 11:35:46 2002 rproudlo
//  Reversed SPI4_CORE Associated Registers
// 
//  Revision: 1.17 Tue Oct  1 07:39:06 2002 bkerr
//  Corrected typo in ISR $display
// 
//  Revision: 1.16 Tue Oct  1 04:02:14 2002 bkerr
//  Enhanced ISR to provide full decode of interrupt registers
// 
//  Revision: 1.15 Thu Sep 26 06:21:47 2002 rproudlo
//  Added very basic ISR
// 
//  Revision: 1.14 Thu Sep 26 05:44:49 2002 bkerr
//  Added clear_stat task to clear all SPO and EOP counters
// 
//  Revision: 1.13 Wed Sep 25 11:04:35 2002 bkerr
//  Altered check_stats task to verify correct counters when performing
//  high-speed loopback
// 
//  Revision: 1.12 Tue Sep 24 08:11:52 2002 rproudlo
//  Modified check_stats_rx for FPGA_LB mode
// 
//  Revision: 1.11 Mon Sep 23 12:36:28 2002 rproudlo
//  Modified check_stats_rx for loopback
// 
//  Revision: 1.10 Tue Sep 17 12:32:18 2002 rproudlo
//  Added check_stats_rx task
// 
//  Revision: 1.9 Mon Sep 16 05:13:52 2002 bkerr
//  Added Write_Norm and Read_Norm tasks as memory read and writes
//  do not require "bit-flipping"
// 
//  Revision: 1.8 Fri Sep 13 10:31:04 2002 bkerr
//  Added "bit-flipper" to move bit[7]MSB to the bit[0] position
//  as all the registers are specified LSB-MSB, but the bmaster is
//  writing MSB-LSB
// 
//  Revision: 1.7 Fri Sep 13 09:43:30 2002 bkerr
//  Debugging MPI_Read task
// 
//  Revision: 1.6 Fri Sep 13 08:25:31 2002 rproudlo
//  Added 'include "verify_task.v"
// 
//  Revision: 1.5 Fri Sep 13 05:40:07 2002 bkerr
//  Updated MPI_Write and MPI_Read tasks to call singe_read and
//  single_write tasks in AHB bmaster
// 
//  Revision: 1.4 Wed Sep  4 05:45:22 2002 bkerr
//  Added check_stats task to verify correct number of SOPs and EOPs
//  were received
// 
//  Revision: 1.3 Fri Aug 23 08:10:42 2002 bkerr
//  Commented out bmaster task calls as the bmaster is no longer present
//  They are kept in as the bmaster will return when the orspii_asb
//  is updated and access to the MPIF is possible.
// 
//  Revision: 1.2 Tue Aug 20 12:00:42 2002 bkerr
//  Added MPI_Write and MPI_Read wrapper tasks to call read & write tasks
//  in the AHB bus master model instantiated in top.v
// 
//  Revision: 1.1 Tue Jul  9 11:59:12 2002 bkerr
//  Initial creation
//=====================================================================

// ---------------------------------------------------------------------------
// Report PASS/FAIL  
// ---------------------------------------------------------------------------

   if(error_count == 0)
   begin
      $display("%t: *******************************************************",$time);
      $display("%t: ****               T E S T   P A S S E D",$time);
      $display("%t: *******************************************************",$time);
   end
   else
   begin
      $display("%t: *******************************************************",$time);
      $display("%t: ****               T E S T   F A I L E D",$time);
      $display("%t: ****        Number of errors:%0d",$time,error_count);
      $display("%t: *******************************************************",$time);
   end
   
// ---------------------------------------------------------------------------
// Simulation termination 
// ---------------------------------------------------------------------------
   if($test$plusargs("STOP"))
      $stop(2);
   else
      $finish(2);

end // initial - begin in header.v
  

// ---------------------------------------------------------------------------
// Interrupt Service Routine
// ---------------------------------------------------------------------------  
always @(posedge ASB_IRQ_SLI)
begin : ISR
  
    reg [7:0]  csr_30b29;
    reg [7:0]  csr_30b2a;
    reg [7:0]  status_reg;
    reg [7:0]  count_reg;
    reg [17:0] int_addr;
    integer    i;
      
    if (test_go == 1'b1)
    begin
      $display("%t: *******************************************************",$time);
      $display("%t: ****        ASB_IRQ_SLI Interrupt positive edge",$time);
      $display("%t: *******************************************************",$time);
      
      MPI_Read  (18'h30b29, csr_30b29);
      $display("%t: Status Register 1 (%h) read %b", $time,18'h30b29,csr_30b29);
                        
      if(csr_30b29[0])
      begin
         $display("%t: \tSPI_A_COR2_INT",$time);
         MPI_Read (18'h3091c, status_reg);
         $display("%t: \t\tSPI4 A Status Register 2 (%h) read %b", $time,18'h3091c,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tTX_STATUS_LOF_STS_A",$time);
         if(status_reg[1])
            $display("%t: \t\t\tALGN_OFF_STS_A",$time);
         if(status_reg[2])
            $display("%t: \t\t\tRDI_TRN_DET_STS_A",$time);
         if(status_reg[3])
            $display("%t: \t\t\tRDI_DSKW_ERR_STS_A",$time);
         if(status_reg[4])
            $display("%t: \t\t\tRDI_DSKW_DONE_STS_A",$time);
         if(status_reg[5])
            $display("%t: \t\t\tRDI_BAS_ERR_STS_A",$time);
         if(status_reg[6])
            $display("%t: \t\t\tRDI_BAS_DONE_STS_A",$time);
         if(status_reg[7])
            $display("%t: \t\t\tRDI_PLL_LOL_STS_A",$time);
      end
 
       if(csr_30b29[1])
      begin     
         $display("%t: \tSPI_A_COR1_INT",$time);
         MPI_Read (18'h3091d, status_reg);
         $display("%t: \t\tSPI4 A Status Register 1 (%h) read %b", $time,18'h3091d,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tASYNC_FIFO_RX_OVERRUN_STS_A",$time);
         if(status_reg[1])
            $display("%t: \t\t\tDIP2_ERR_STS_A",$time);
         if(status_reg[2])
	   begin
             $display("%t: \t\t\tDIP4_ERR_STS_A",$time);
//	       MPI_Read (18'h3090a, count_reg);
//               $display("%t: \t\tSPI4 A DIP4_ERR_CNT (%h) read %d", $time,18'h3090a,count_reg);
	   end 
         if(status_reg[3])
            $display("%t: \t\t\tTX_SOP_ALIGN_ERR_STS_A",$time);
         if(status_reg[4])
            $display("%t: \t\t\tRX_SOP_ALIGN_ERR_STS_A",$time);
      end
                                   
      if(csr_30b29[2])
      begin
         $display("%t: \tSPI_B_COR2_INT",$time);
         MPI_Read (18'h30a1c, status_reg);
         $display("%t: \t\tSPI4 B Status Register 2 (%h) read %b", $time,18'h30a1c,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tTX_STATUS_LOF_STS_B",$time);
         if(status_reg[1])
            $display("%t: \t\t\tALGN_OFF_STS_B",$time);
         if(status_reg[2])
            $display("%t: \t\t\tRDI_TRN_DET_STS_B",$time);
         if(status_reg[3])
            $display("%t: \t\t\tRDI_DSKW_ERR_STS_B",$time);
         if(status_reg[4])
            $display("%t: \t\t\tRDI_DSKW_DONE_STS_B",$time);
         if(status_reg[5])
            $display("%t: \t\t\tRDI_BAS_ERR_STS_B",$time);
         if(status_reg[6])
            $display("%t: \t\t\tRDI_BAS_DONE_STS_B",$time);
         if(status_reg[7])
            $display("%t: \t\t\tRDI_PLL_LOL_STS_B",$time);
      end

      if(csr_30b29[3])
      begin     
         $display("%t: \tSPI_B_COR1_INT",$time);
         MPI_Read (18'h30a1d, status_reg);
         $display("%t: \t\tSPI4 B Status Register 1 (%h) read %b", $time,18'h30a1d,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tASYNC_FIFO_RX_OVERRUN_STS_B",$time);
         if(status_reg[1])
            $display("%t: \t\t\tDIP2_ERR_STS_B",$time);
         if(status_reg[2])
            $display("%t: \t\t\tDIP4_ERR_STS_B",$time);
         if(status_reg[3])
            $display("%t: \t\t\tTX_SOP_ALIGN_ERR_STS_B",$time);
         if(status_reg[4])
            $display("%t: \t\t\tRX_SOP_ALIGN_ERR_STS_B",$time);
      end
 
      if(csr_30b29[4])
      begin
         $display("%t: \tDPRAM_INT",$time);
         MPI_Read (18'h30b2a, csr_30b2a);
         $display("%t: \tStatus Register 2 (%h) read %b", $time,18'h30b2a,csr_30b2a);
         
         if(csr_30b2a[7])
         begin
            $display("%t: \t\tTX_INT_B",$time);
            int_addr = 18'h30a28;
         end
         if(csr_30b2a[6])
         begin
            $display("%t: \t\tRX_INT_B",$time);
            int_addr = 18'h30a0c;
         end
         if(csr_30b2a[5])
         begin
            $display("%t: \t\tTX_INT_A",$time);
            int_addr = 18'h30928;
         end
         if(csr_30b2a[4])
         begin
            $display("%t: \t\tRX_INT_A",$time);
            int_addr = 18'h3090c;
         end
         
         if(csr_30b2a[3])
         begin
            $display("%t: \t\tBANK_3_INT",$time);
            int_addr = int_addr + 18'h00003;
            MPI_Read(int_addr, status_reg);
            $display("%t: \t\t\tOVERRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tOVERRUN_STS[%0d]",$time,i);
            end
                  
            int_addr = int_addr + 18'h00004;
            $display("%t: \t\t\tURRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tURRUN_STS[%0d]",$time,i);
            end
         end
         
         if(csr_30b2a[2])
         begin
            $display("%t: \t\tBANK_2_INT",$time);
            int_addr = int_addr + 18'h00002;
            MPI_Read(int_addr, status_reg);
            $display("%t: \t\t\tOVERRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tOVERRUN_STS[%0d]",$time,i);
            end
                  
            int_addr = int_addr + 18'h00004;
            $display("%t: \t\t\tURRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tURRUN_STS[%0d]",$time,i);
            end
         end
         
         if(csr_30b2a[1])
         begin
            $display("%t: \t\tBANK_1_INT",$time);
            int_addr = int_addr + 18'h00001;
            MPI_Read(int_addr, status_reg);
            $display("%t: \t\t\tOVERRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tOVERRUN_STS[%0d]",$time,i);
            end
                  
            int_addr = int_addr + 18'h00004;
            $display("%t: \t\t\tURRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tURRUN_STS[%0d]",$time,i);
            end
         end
         
         if(csr_30b2a[0])
         begin
            $display("%t: \t\tBANK_0_INT",$time);
            int_addr = int_addr + 18'h00000;
            MPI_Read(int_addr, status_reg);
            $display("%t: \t\t\tOVERRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tOVERRUN_STS[%0d]",$time,i);
            end
                  
            int_addr = int_addr + 18'h00004;
            $display("%t: \t\t\tURRUN_STS @ %h read %b",$time,int_addr,status_reg);
            for(i=0;i<8;i=i+1)
            begin
               if(status_reg[i])
                  $display("%t: \t\t\t\tURRUN_STS[%0d]",$time,i);
            end
         end         
      end
         
      if(csr_30b29[5])
      begin
         $display("%t: \tMEM_CTRL1_INT",$time);
         MPI_Read (18'h30b09, status_reg);
         $display("%t: \t\tMemory Controller Status Register 1 (%h) read %b", $time,18'h30b09,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tMC_ID_ERR_STS",$time);
      end
         
      if(csr_30b29[6])
      begin
         $display("%t: \tMEM_CTRL2_INT",$time);
         MPI_Read (18'h30b08, status_reg);
         $display("%t: \t\tMemory Controller Status Register 2 (%h) read %b", $time,18'h30b08,status_reg);
         if(status_reg[0])
            $display("%t: \t\t\tMC_WR_DFIFO_OVERRUN_STS",$time);
         if(status_reg[1])
            $display("%t: \t\t\tMC_WR_IFIFO_OVERRUN_STS",$time);
         if(status_reg[2])
            $display("%t: \t\t\tMC_RD_IFIFO_OVERRUN_STS",$time);
         if(status_reg[3])
            $display("%t: \t\t\tMC_RD_DFIFO_OVERRUN_STS",$time);
         if(status_reg[4])
            $display("%t: \t\t\tMC_WR_DFIFO_URRUN_STS",$time);
         if(status_reg[5])
            $display("%t: \t\t\tMC_WR_IFIFO_URRUN_STS",$time);
         if(status_reg[6])
            $display("%t: \t\t\tMC_RD_IFIFO_URRUN_STS",$time);
         if(status_reg[7])
            $display("%t: \t\t\tMC_RD_DFIFO_URRUN_STS",$time);
      end
         
      if(csr_30b29[7])
         $display("%t: \tSERDES_INT",$time);                                       

      $display("%t: *******************************************************",$time);
         
   end // if(test_go...)
end // always
    
//
// Common Tasks
//

`include "config_task.v"
`include "verify_task.v"

// Bit flipped write (for registers)
task MPI_Write;
input [17:0]   address;
input [ 7:0]   data;
reg            ret_status;
begin
bmaster.single_write(address,3'b000,{data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]},ret_status);
end
endtask

// Non bit flipped write (for memories)
task MPI_Write_Norm;
input [17:0]   address;
input [ 7:0]   data;
reg            ret_status;
begin
bmaster.single_write(address,3'b000,data,ret_status);
end
endtask

// Bit-flipped read (for registers)
task MPI_Read;
input  [17:0]  address;
output [ 7:0]  data;
reg            ret_status;
reg   [35:0]   read_data;
begin
bmaster.single_read(address,3'b000,read_data,ret_status);
data[7] = read_data[0];
data[6] = read_data[1];
data[5] = read_data[2];
data[4] = read_data[3];
data[3] = read_data[4];
data[2] = read_data[5];
data[1] = read_data[6];
data[0] = read_data[7];   
end
endtask

// Non bit-flipped read (for memories)
task MPI_Read_Norm;
input  [17:0]  address;
output [ 7:0]  data;
reg            ret_status;
reg   [35:0]   read_data;
begin
bmaster.single_read(address,3'b000,read_data,ret_status);
data = read_data[7:0];
end
endtask


task check_stats_tx;
integer i;
integer sop_count_rx;
integer eop_count_rx;
begin
   $display("%t: *******************************************************",$time);
   $display("%t: ****            Port SOP and EOP counters",$time);
   $display("%t: *******************************************************",$time);
   $display("%t: Port   Tx SOP    Tx EOP      Rx SOP   Rx EOP",$time);
         
   for(i=0;i<TX_PDM_ACTIVE_PORTS;i=i+1)
   begin
      if(LOOPBACK_HS || LOOPBACK_LS)
      begin
//         sop_count_rx = a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_sop_count[TX_PDM_PORT_ID[i]] +
//                        a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_sop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_sop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_sop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_sop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_sop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_sop_count[TX_PDM_PORT_ID[i]];
//         eop_count_rx = a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_eop_count[TX_PDM_PORT_ID[i]] +
//                        a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_eop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_eop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_eop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_eop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_eop_count[TX_PDM_PORT_ID[i]] +
//				            a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_sop_count[TX_PDM_PORT_ID[i]];
      end
      else
      begin
         sop_count_rx = a_latspi4.rx_sop_count[TX_PDM_PORT_ID[i]];
         eop_count_rx = a_latspi4.rx_eop_count[TX_PDM_PORT_ID[i]];
      end
   
//      $display("%t: [%0d]    %0d        %0d          %0d       %0d",
//            $time,
//            TX_PDM_PORT_ID[i],
//            a_fpga_bfm_tx.tx_sop_count[TX_PDM_PORT_ID[i]],
//            a_fpga_bfm_tx.tx_eop_count[TX_PDM_PORT_ID[i]],
//            sop_count_rx,
//            eop_count_rx);
            
//      if(a_fpga_bfm_tx.tx_sop_count[TX_PDM_PORT_ID[i]] != sop_count_rx)
//      begin
//         $display("%t: ERROR: Incorrect number of SOPs received for port [%0d]",$time,TX_PDM_PORT_ID[i]);
//         error_count = error_count + 1;
//      end
//      if(a_fpga_bfm_tx.tx_eop_count[TX_PDM_PORT_ID[i]] != eop_count_rx)
//      begin
//         $display("%t: ERROR: Incorrect number of EOPs received for port [%0d]",$time,TX_PDM_PORT_ID[i]);
//         error_count = error_count + 1;
//      end      
   end
   
   $display("%t: *******************************************************",$time);
end
endtask
        

task check_stats_rx;
integer i;

reg [15:0] a_fpga_bfm_rx_sop_count [0:255];
reg [15:0] a_fpga_bfm_rx_eop_count [0:255];

begin
   $display("%t: *******************************************************",$time);
   $display("%t: ****            Port SOP and EOP counters          ****",$time);
   $display("%t: *******************************************************",$time);
   $display("%t:       LATSPI    LATSPI        FPGA       FPGA         LATSPI     LATSPI",$time);
   $display("%t: Port  Tx SOP    Tx EOP       Rx SOP     Rx EOP        Rx SOP     Rx EOP",$time);

//for (i=0;i<=255;i=i+1)
//  begin   
//    a_fpga_bfm_rx_sop_count[i] = (a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_sop_count[i] +
//                                  a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_sop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_sop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_sop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_sop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_sop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_sop_count[i]);
//  end
//
//for (i=0;i<=255;i=i+1)
//  begin   
//    a_fpga_bfm_rx_eop_count[i] = (a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_eop_count[i] +
//                                  a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_eop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_eop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_eop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_eop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_eop_count[i] +
//				  a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_eop_count[i]);
//  end
    
   for(i=0;i<RX_PDM_ACTIVE_PORTS;i=i+1)
   begin
      $display("%t: [%0d]    %0d        %0d          %0d       %0d          %0d       %0d",
            $time,
            RX_PDM_ACTIVE_PORT_ID[i],
            a_latspi4.tx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]],
            a_latspi4.tx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]],
	         a_fpga_bfm_rx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]],
            a_fpga_bfm_rx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]],
	         a_latspi4.rx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]],
            a_latspi4.rx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]]);
            
      if(a_latspi4.tx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]] != a_fpga_bfm_rx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]])
      begin
         $display("%t: ERROR: Incorrect number of SOPs received (FPGA) for port [%0d]",$time,RX_PDM_ACTIVE_PORT_ID[i]);
         error_count = error_count + 1;
      end
      if(a_latspi4.tx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]] != a_fpga_bfm_rx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]])
      begin
         $display("%t: ERROR: Incorrect number of EOPs received (FPGA) for port [%0d]",$time,RX_PDM_ACTIVE_PORT_ID[i]);
         error_count = error_count + 1;
      end

  if (FPGA_LB == 1'b1)
    begin
      if(a_latspi4.tx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]] != a_latspi4.rx_sop_count[RX_PDM_ACTIVE_PORT_ID[i]])
      begin
         $display("%t: ERROR: Incorrect number of SOPs received (LATSPI) for port [%0d]",$time,RX_PDM_ACTIVE_PORT_ID[i]);
         error_count = error_count + 1;
      end
      if(a_latspi4.tx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]] != a_latspi4.rx_eop_count[RX_PDM_ACTIVE_PORT_ID[i]])
      begin
         $display("%t: ERROR: Incorrect number of EOPs received (LATSPI) for port [%0d]",$time,RX_PDM_ACTIVE_PORT_ID[i]);
         error_count = error_count + 1;
      end
    end
      
   end
   
   $display("%t: *******************************************************",$time);
   
end
endtask
	    
task clear_stats;
integer i;
begin
   for(i=0;i<256;i=i+1)
   begin
   
   // LatSPI4
      a_latspi4.tx_sop_count[i] = 0;            
      a_latspi4.tx_eop_count[i] = 0;            
      a_latspi4.rx_sop_count[i] = 0;            
      a_latspi4.rx_eop_count[i] = 0;            

//   // FPGA BFM Tx
//      a_fpga_bfm_tx.tx_sop_count[i] = 0;
//      a_fpga_bfm_tx.tx_eop_count[i] = 0;
//      
//   // FPGA BFM Rx      
//      a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_sop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_sop_count[i]= 0;
//      
//      a_fpga_bfm_rx.fpga_bfm_rx32_0.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_1.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_2.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx32_3.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx64_0.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx64_2.rx_eop_count[i] = 0;
//      a_fpga_bfm_rx.fpga_bfm_rx128_0.rx_eop_count[i]= 0;      
   end
   
   $display("%t: Cleared all SOP & EOP Counters",$time);
end
endtask                         

endmodule
