/* Verilog netlist generated by SCUBA ORCA Foundry 2001 Production (114) */
/* /sopt/ORCA/bin/sol/scuba -w -e -lang verilog -n rfclk_pll -bus_exp 7 -bb -type pll -arch orca4 -fin 104 -mfreq 104 -nfreq 104 -pllmode phase -tap 0  */
/* Tue Sep  3 09:54:41 2002 */

`timescale 1 ns / 100 ps
module rfclk_pll (clk, mclk, nclk, lock);
    input clk;
    output mclk;
    output nclk;
    output lock;

    wire nclk_t;
    wire mclk_t;

    defparam rfclk_pll_0_0.VCOTAP = 0;
    defparam rfclk_pll_0_0.NCLKMODE = "PHSHIFT";
    defparam rfclk_pll_0_0.MCLKMODE = "PHSHIFT";
    defparam rfclk_pll_0_0.DIV3 = 1;
    defparam rfclk_pll_0_0.DIV2 = 1;
    defparam rfclk_pll_0_0.DIV1 = 1;
    defparam rfclk_pll_0_0.DIV0 = 1;
    PPLL rfclk_pll_0_0 (.CLKIN(clk), .FB(fb), .MCLK(mclk_t), .NCLK(nclk_t), 
        .LOCK(lock), .INTFB(fb));

    assign nclk = nclk_t;
    assign mclk = mclk_t;

endmodule
