
//Memory configuration file 03

for (i=0;i<=(CALENDAR_LEN_TX-1'd1);i=i+1)
  begin
    TX_MAIN_CAL_SEQ[i]  = i[7:0];
  end
  
TX_SHADOW_CAL_SEQ[0]  = 8'dx;

for (i=0;i<=(CALENDAR_LEN_RX-1'd1);i=i+1)
  begin
    RX_MAIN_CAL_SEQ[i]  = i[7:0];
  end

RX_SHADOW_CAL_SEQ[0]  = 8'dx;

//

TX_PDM_ACTIVE_PORTS = 16;

for (i=0;i<=(TX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
  begin
    TX_PDM_ACTIVE_PORT_ID[i]  = i[7:0];
    TX_PDM_MBEN[i]            = 1'b1;
    TX_PDM_M_BIT[i]           = 1'b0;
    TX_PDM_BVAL[i]            = 5'd4;
    TX_PDM_PORT_ID[i]         = i[7:0];
    TX_PDM_BANK_ID[i]         = i[3:2];
    TX_PDM_PA[i]              = {1'b0,i[1:0]};    
  end

//

RX_PDM_ACTIVE_PORTS = 16;

for (i=0;i<=(RX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
  begin
    RX_PDM_ACTIVE_PORT_ID[i]  = i[7:0];
    RX_PDM_BANK_ID[i]         = i[3:2];
    RX_PDM_PA[i]              = {1'b0,i[1:0]};    
  end

// MAX_BURST1_RX = 512/RX_PDM_ACTIVE_PORTS * 0.4; 
// MAX_BURST2_RX = 512/RX_PDM_ACTIVE_PORTS * 0.2; 

MAX_BURST1_RX = 512/RX_PDM_ACTIVE_PORTS * 0.2;  // mph
MAX_BURST2_RX = 512/RX_PDM_ACTIVE_PORTS * 0.1;  // mph

MAX_BURST1    = MAX_BURST1_RX; 
MAX_BURST2    = MAX_BURST2_RX; 
