/* Verilog netlist generated by SCUBA ORCA Foundry 2001 Production (114) */
/* /sopt/ORCA/bin/sol/scuba -w -e -lang verilog -n rfclk_pll -synth synplify -bus_exp 7 -bb -type pll -arch orca4 -fin 104 -mfreq 104 -nfreq 104 -pllmode phase -tap 1  */
/* Tue Sep  3 09:55:23 2002 */

// PLL model modified to build out delay to meet I/O timing - mph 9/10/03

`timescale 1 ns / 100 ps
module rfclk_pll_ph (clk, fb, mclk, nclk, intfb, lock);
    input clk;
    input fb;
    output mclk;
    output nclk;
    output intfb;
    output lock;

    wire nclk_t/*synthesis syn_keep=1 FREQUENCY = "104.000" */;
    wire mclk_t/*synthesis syn_keep=1 FREQUENCY = "104.000" */;

    PPLL rfclk_pll_ph_0_0 (.CLKIN(clk), .FB(fb), .MCLK(mclk_t), .NCLK(nclk_t), 
        .LOCK(lock), .INTFB(intfb)) 
	/* synthesis VCOTAP="1" */ 
	/* synthesis NCLKMODE="PHSHIFT" */ 
	/* synthesis MCLKMODE="PHSHIFT" */ 
	/* synthesis DIV3="1" */ 
	/* synthesis DIV2="1" */ 
	/* synthesis DIV1="1" */ 
	/* synthesis DIV0="1" */
	/* synthesis FB_PDEL="DEL3" */;

    assign nclk = nclk_t;
    assign mclk = mclk_t;

endmodule
