///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor
// Corporation.
// The entire notice above must be reproduced on all authorized
// copies and copies may only be made to the extent permitted
// by a licensing agreement from Lattice Semiconductor Corporation.
//
// ====================================================================
// File Details
// ====================================================================
// Project              :       ORSPII
// Filename             :       config_task.v
// Author               :       Rob Proudlock, rproudlo@latticesemi.com
// Created on           :       Wednesday 10th July 2002
// Last Modified By     :       $Author: bkerr $
// Last Modified On     :       $Date: Thu Nov 21 09:20:12 2002 $ 
// Revision             :       $Revision: 1.23 $
// Status               :       Development
// Dependencies         :       None
//=====================================================================

//=====================================================================
// Description          :
//=====================================================================
// This module implements the configuration task required to set up the 
// ORSPII SPI4.2 design following a reset.
//
//
//=====================================================================

//=====================================================================
// Revision History
//=====================================================================
// $Log: config_task.v.rca $
// 
//  Revision: 1.23 Thu Nov 21 09:20:12 2002 bkerr
//  Added LOOPBACK_FE register bit introduced in top8 release
// 
//  Revision: 1.22 Thu Oct 24 11:53:37 2002 rproudlo
//  Added new register bits.
//  
// 
//  Revision: 1.21 Wed Oct  9 04:31:05 2002 rproudlo
//  Change Memory Write from Mem_Write_Norm to Mem_Write
// 
//  Revision: 1.20 Wed Sep 18 06:31:03 2002 bkerr
//  Corrected byte ordering of DATA_MAX_T and ALPHA registers
// 
//  Revision: 1.19 Mon Sep 16 05:13:38 2002 rproudlo
//  Renamed memory write/read task due to msb/lsb error
// 
//  Revision: 1.18 Fri Sep 13 09:45:00 2002 bkerr
//  Debugging register verification
// 
//  Revision: 1.17 Thu Sep 12 10:29:05 2002 rproudlo
//  Reworked for new register map
// 
//  Revision: 1.16 Thu Sep 12 09:22:38 2002 bkerr
//  Deleted write_mem task and used MPI_Write to perform transactions
// 
//  Revision: 1.15 Mon Sep  9 10:11:26 2002 bkerr
//  Moved write_en away from write data as this is used as the write clock
//  in the Rx implementation
// 
//  Revision: 1.14 Mon Sep  9 08:18:53 2002 bkerr
//  Changed reference clock for memory read & write tasks due to addition
//  of s4_top
// 
//  Revision: 1.13 Fri Sep  6 11:22:53 2002 rproudlo
//  Modified Rx Cal memory write
// 
//  Revision: 1.12 Fri Sep  6 05:09:51 2002 rproudlo
//  Fixed Typo
// 
//  Revision: 1.11 Fri Sep  6 05:06:48 2002 rproudlo
//  Added Rx Memory interface/task for CAL/PDM
// 
//  Revision: 1.10 Wed Sep  4 11:40:14 2002 bkerr
//  Altered bit ordering on the 2nd PDM write to place the PA field in the
//  correct location
// 
//  Revision: 1.9 Wed Sep  4 05:52:05 2002 bkerr
//  Removed reference to tclk as it is removed
//  Synchronised writes to internal trefclk_2
// 
//  Revision: 1.8 Thu Aug 29 06:42:08 2002 rproudlo
//  Modified memory write for Tx PDM
// 
//  Revision: 1.7 Fri Aug 23 08:16:56 2002 bkerr
//  Added write_mem_tx task that is used to (temporarily) program the
//  memories in the tx_path. This will be removed when the MPIF & orspii_asb
//  modules are tied together
// 
//  Revision: 1.6 Fri Aug 16 05:59:01 2002 rproudlo
//  Remove redundant task
// 
//  Revision: 1.5 Thu Aug 15 09:49:44 2002 rproudlo
//  Updated after initial verification
// 
//  Revision: 1.4 Thu Jul 11 09:32:19 2002 bkerr
//  Added dummy MPI_Write task to allow simulations to run in the
//  absence of the MPIF module
// 
//  Revision: 1.3 Wed Jul 10 11:30:46 2002 rproudlo
//  Fixed typo (again)
// 
//  Revision: 1.2 Wed Jul 10 11:27:44 2002 rproudlo
//  Fixed typo
// 
//  Revision: 1.1 Wed Jul 10 11:17:24 2002 rproudlo
//  Initial Creation
// 
// 
//=====================================================================

task config_mem;

reg [7:0] read_reg;

integer i;

  begin

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// Program Tx Calendar A
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Write (18'h30917,8'b0000_1000);
    MPI_Read (18'h30917,read_reg);

    MEMORY_BASE_ADDR = 18'h31000;
    
    for (i=0;i<=(CALENDAR_LEN_TX-1'd1);i=i+1)
      begin
        MPI_Write (MEMORY_BASE_ADDR, TX_MAIN_CAL_SEQ[i]);                        
        MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
      end
      
// Program Tx Shadow Calendar

  if (CALENDAR_SW_EN_TX == 1'b1)
    begin
    
    MEMORY_BASE_ADDR = 18'h31400;
    
      for (i=0;i<=(CALENDAR_LEN_TX_SHDW-1'd1);i=i+1)
        begin
          MPI_Write (MEMORY_BASE_ADDR, TX_SHADOW_CAL_SEQ[i]);
          MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
        end

    end

    MEMORY_BASE_ADDR = 18'h31000;

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// Program Rx Calendar A
// +++++++++++++++++++++++++++++++++++++++++++++++++++++


    MPI_Write (18'h30917,8'b0010_0000);

    for (i=0;i<=(CALENDAR_LEN_RX-1'd1);i=i+1)
      begin
        MPI_Write (MEMORY_BASE_ADDR, RX_MAIN_CAL_SEQ[i]);
        MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
      end

// Program Rx Shadow Calendar

  if (CALENDAR_SW_EN_RX == 1'b1)
    begin    

    MEMORY_BASE_ADDR = 18'h31400;

      for (i=0;i<=(CALENDAR_LEN_RX_SHDW-1'd1);i=i+1)
        begin
          MPI_Write (MEMORY_BASE_ADDR, RX_SHADOW_CAL_SEQ[i]);
          MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
        end

    end

    MEMORY_BASE_ADDR = 18'h31000;

// +++++++++++++++++++++++++++++++++++++++++++++++++++++    
// Program Tx PDM
// +++++++++++++++++++++++++++++++++++++++++++++++++++++
    
    MPI_Write (18'h30917,8'b0000_0100);
    
    for (i=0;i<=(TX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
      begin
        // Write 1 - Port address      
        MPI_Write (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b00}, TX_PDM_PORT_ID[TX_PDM_PORT_ID[i]]);        
	                 
        // Write 2 - PA,BurstVAL        		   
        MPI_Write (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b01},
	                                {TX_PDM_PA[TX_PDM_PORT_ID[i]],1'b0,TX_PDM_BVAL[TX_PDM_PORT_ID[i]]});

        // Write 3 - MBEN,M,BankID   		  
        MPI_Write (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b10}, 
	           {4'b0000,TX_PDM_MBEN[TX_PDM_PORT_ID[i]],TX_PDM_M_BIT[TX_PDM_PORT_ID[i]],
		   TX_PDM_BANK_ID[TX_PDM_PORT_ID[i]]});
		  
        // Write 4 - unused

     end
      
      MEMORY_BASE_ADDR = 18'h31000;

// +++++++++++++++++++++++++++++++++++++++++++++++++++++    
// Program Rx PDM
// +++++++++++++++++++++++++++++++++++++++++++++++++++++
      
    MPI_Write (18'h30917,8'b0001_0000);

    for (i=0;i<=(RX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
      begin      
        MPI_Write (MEMORY_BASE_ADDR + RX_PDM_ACTIVE_PORT_ID[i], {3'b000,RX_PDM_BANK_ID[i],RX_PDM_PA[i]});
	
      end

      MEMORY_BASE_ADDR = 18'h31000;

  end
endtask

task config_regs;
  begin  
// Program Control Registers

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Rx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Write (18'h30900, CALENDAR_M_RX);
    MPI_Write (18'h30901, {6'b00_0000,CALENDAR_LEN_RX[9:8]});
    MPI_Write (18'h30902, CALENDAR_LEN_RX[7:0]);

    MPI_Write (18'h30903, CALENDAR_M_RX_SHDW);
    MPI_Write (18'h30904, {6'b00_0000,CALENDAR_LEN_RX_SHDW[9:8]});
    MPI_Write (18'h30905, CALENDAR_LEN_RX_SHDW[7:0]);
				      
    MPI_Write (18'h30906, RX_DPRAM_PART_SIZE);
    MPI_Write (18'h30907, RX_DPRAM_AGGR_MODE);
    
    MPI_Write (18'h30910, {1'b0,LOSS_SYNC,DISABLE_STATUS,MASK_DIP4,EN_TRAINING,EN_BASELINE});

    MPI_Write (18'h30911, FIFO_THRESHOLD_H_RX);
    
    MPI_Write (18'h30912, DPRAM_RX_FIFO_OVER_UR_RUN_INT_EN);

    MPI_Write (18'h30913, RDI_INT_EN);

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Tx/Rx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Write (18'h30914, {2'b00,SOP_DIP_ASF_INT_EN});
    MPI_Write (18'h30915, {1'b0,LS_STIO_LB_FERR});
    MPI_Write (18'h30916, {4'b0000,CALENDAR_SW_EN_RX,CALENDAR_SW_SEL_RX,
                           CALENDAR_SW_EN_TX,TX_BURST_TERMINATION});

//    MPI_Write (18'h30917, {2'b00,MEM_SEL_RXCAL,MEM_SEL_RXPDM,MEM_SEL_TXCAL
//                           MEM_SEL_TXMAIN,MEM_SEL_TXCRED,MEM_SEL_TXSTAT});

    MPI_Write (18'h30920, DPRAM_FULL_EMPTY_SEL);

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Tx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Write (18'h30921, CALENDAR_M_TX);
    MPI_Write (18'h30922, {6'b00_0000,CALENDAR_LEN_TX[9:8]});
    MPI_Write (18'h30923, CALENDAR_LEN_TX[7:0]);

    MPI_Write (18'h30924, CALENDAR_M_TX_SHDW);
    MPI_Write (18'h30925, {6'b00_0000,CALENDAR_LEN_TX_SHDW[9:8]});
    MPI_Write (18'h30926, CALENDAR_LEN_TX_SHDW[7:0]);
				      
    MPI_Write (18'h30927, TX_DPRAM_PART_SIZE);
    MPI_Write (18'h30930, TX_DPRAM_AGGR_MODE);

    MPI_Write (18'h30931, {6'b00_0000,MAX_BURST1[9:8]});
    MPI_Write (18'h30932, MAX_BURST1[7:0]);

    MPI_Write (18'h30933, {6'b00_0000,MAX_BURST2[9:8]});
    MPI_Write (18'h30934, MAX_BURST2[7:0]);

    MPI_Write (18'h30935, DATA_MAX_T[31:24]);
    MPI_Write (18'h30936, DATA_MAX_T[23:16]);
    MPI_Write (18'h30937, DATA_MAX_T[15: 8]);
    MPI_Write (18'h30940, DATA_MAX_T[ 7: 0]);

    MPI_Write (18'h30941, ALPHA[15:8]);
    MPI_Write (18'h30942, ALPHA[ 7:0]);

    MPI_Write (18'h30943, DPRAM_TX_FIFO_OVER_UR_RUN_INT_EN);

    MPI_Write (18'h30944, {5'b0_0000,DIP2_ERR_TH});

    MPI_Write (18'h30945, {3'b000,FIFO_THRESHOLD_H_TX});

end
  
endtask
