/* Verilog netlist generated by SCUBA ispLever_v3_Prod_Test_Build (68c) */
/* /sopt/lattice/ispLEVER30/isptools/ispfpga/bin/sol/scuba -w -e -lang verilog -n rfclk_pll_ph -synth spectrum -arch orca4 -bus_exp 1 -bb -type pll -fin 104 -mfreq 104 -nfreq 104 -pllmode phase -tap 1  */
/* Wed Apr 23 10:55:48 2003 */

`timescale 1 ns / 100 ps
module rfclk_pll_ph (clk, fb, mclk, nclk, intfb, lock);
    input clk;
    input fb;
    output mclk;
    output nclk;
    output intfb;
    output lock;

    wire nclk_t;
    wire mclk_t;

    PPLL rfclk_pll_ph_0_0 (.CLKIN(clk), .FB(fb), .MCLK(mclk_t), .NCLK(nclk_t), 
        .LOCK(lock), .INTFB(intfb));
    assign nclk = nclk_t;
    assign mclk = mclk_t;


    // exemplar begin
    // exemplar attribute rfclk_pll_ph_0_0 VCOTAP 1
    // exemplar attribute rfclk_pll_ph_0_0 NCLKMODE PHSHIFT
    // exemplar attribute rfclk_pll_ph_0_0 MCLKMODE PHSHIFT
    // exemplar attribute rfclk_pll_ph_0_0 DIV3 1
    // exemplar attribute rfclk_pll_ph_0_0 DIV2 1
    // exemplar attribute rfclk_pll_ph_0_0 DIV1 1
    // exemplar attribute rfclk_pll_ph_0_0 DIV0 1
    // exemplar attribute rfclk_pll_ph_0_0 FB_PDEL DEL3
    // exemplar attribute nclk_t FREQUENCY 104.000
    // exemplar attribute mclk_t FREQUENCY 104.000
    // exemplar end

endmodule
