///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor
// Corporation.
// The entire notice above must be reproduced on all authorized
// copies and copies may only be made to the extent permitted
// by a licensing agreement from Lattice Semiconductor Corporation.
//
// ====================================================================
// File Details
// ====================================================================
// Project              :       ORSPII
// Filename             :       verify_task.v
// Author               :       Rob Proudlock, rproudlo@latticesemi.com
// Created on           :       Friday 9th August 2002
// Last Modified By     :       $Author: bkerr $
// Last Modified On     :       $Date: Thu Nov 21 09:20:38 2002 $ 
// Revision             :       $Revision: 1.11 $
// Status               :       Development
// Dependencies         :       None
//=====================================================================

//=====================================================================
// Description          :
//=====================================================================
//
//=====================================================================

//=====================================================================
// Revision History
//=====================================================================
// $Log: verify_task.v.rca $
// 
//  Revision: 1.11 Thu Nov 21 09:20:38 2002 bkerr
//  Added LOOPBACK_FE register bit introduced in top8 release
// 
//  Revision: 1.10 Thu Oct 24 11:53:38 2002 rproudlo
//  Added new register bits.
//  
// 
//  Revision: 1.9 Fri Oct 18 06:39:39 2002 rproudlo
//  Added Status registers to verify task for Reset testing
// 
//  Revision: 1.8 Wed Oct  9 04:34:28 2002 rproudlo
//  Change Memory Read from Mem_Read_Norm to Mem_Read
// 
//  Revision: 1.7 Tue Sep 24 12:29:36 2002 bkerr
//  Corrected byte ordering of DATA_MAX_T and ALPHA register verify
// 
//  Revision: 1.6 Mon Sep 16 05:41:07 2002 rproudlo
//  Fixed typo in verify memory task
// 
//  Revision: 1.5 Mon Sep 16 05:13:39 2002 rproudlo
//  Renamed memory write/read task due to msb/lsb error
// 
//  Revision: 1.4 Fri Sep 13 11:50:51 2002 rproudlo
//  Initial debugging
// 
//  Revision: 1.3 Fri Sep 13 09:44:11 2002 bkerr
//  Debugging register verification
// 
//  Revision: 1.2 Fri Sep 13 08:37:05 2002 rproudlo
//  Reworked for new register map
// 
//  Revision: 1.1 Thu Aug 15 09:50:38 2002 rproudlo
//  Initial Checkin
// 
// 
//=====================================================================

task verify_mem;

integer i;

reg [7:0] read_reg;

  begin

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// Tx Calendar A
// +++++++++++++++++++++++++++++++++++++++++++++++++++++
    
    MPI_Write (18'h30917,8'b0000_1000);
    
    MPI_Read  (18'h30917, read_reg);
	  if (read_reg != 8'b0000_1000)
	    $display("Read back ERROR on %h read %b expect %b", 18'h30917,read_reg,8'b0000_1000);
	    
    MEMORY_BASE_ADDR = 18'h31000;
    
    for (i=0;i<=(CALENDAR_LEN_TX-1'd1);i=i+1)
      begin
        MPI_Read (MEMORY_BASE_ADDR, read_reg);
	  if (read_reg != TX_MAIN_CAL_SEQ[i])
	    $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR,read_reg,TX_MAIN_CAL_SEQ[i]);

        MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
      end
      
// Tx Shadow Calendar

  if (CALENDAR_SW_EN_TX == 1'b1)
    begin

    MEMORY_BASE_ADDR = 18'h31400;
    
      for (i=0;i<=(CALENDAR_LEN_TX_SHDW-1'd1);i=i+1)
        begin
          MPI_Read (MEMORY_BASE_ADDR, read_reg);
	    if (read_reg != TX_SHADOW_CAL_SEQ[i])
	      $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR,read_reg,TX_SHADOW_CAL_SEQ[i]);

	  MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
        end

    end

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// Rx Calendar A
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Write (18'h30917,8'b0010_0000);
    
    MPI_Read  (18'h30917, read_reg);
	  if (read_reg != 8'b0010_0000)
	    $display("Read back ERROR on %h read %b expect %b", 18'h30917, read_reg, 8'b0010_0000);

    MEMORY_BASE_ADDR = 18'h31000;

    for (i=0;i<=(CALENDAR_LEN_RX-1'd1);i=i+1)
      begin
        MPI_Read (MEMORY_BASE_ADDR, read_reg);
	  if (read_reg != RX_MAIN_CAL_SEQ[i])
	    $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR,read_reg,RX_MAIN_CAL_SEQ[i]);

        MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
      end

// Program Rx Shadow Calendar

  if (CALENDAR_SW_EN_RX == 1'b1)
    begin    

    MEMORY_BASE_ADDR = 18'h31400;

      for (i=0;i<=(CALENDAR_LEN_RX-1'd1);i=i+1)
        begin
          MPI_Read (MEMORY_BASE_ADDR, read_reg);
	    if (read_reg != RX_SHADOW_CAL_SEQ[i])
	      $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR,read_reg,RX_SHADOW_CAL_SEQ[i]);

          MEMORY_BASE_ADDR = MEMORY_BASE_ADDR + 1;
        end

    end
    
// +++++++++++++++++++++++++++++++++++++++++++++++++++++    
// Program Tx PDM
// +++++++++++++++++++++++++++++++++++++++++++++++++++++
    
    MPI_Write (18'h30917,8'b0000_0100);

    MPI_Read  (18'h30917, read_reg);
	  if (read_reg != 8'b0000_0100)
	    $display("Read back ERROR on %h read %b expect %b", 18'h30917, read_reg, 8'b0000_0100);

    MEMORY_BASE_ADDR = 18'h31000;
    
    for (i=0;i<=(TX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
      begin
        // Read 1 - Port address      
        MPI_Read (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b00}, read_reg);
	  if (read_reg != TX_PDM_PORT_ID[TX_PDM_PORT_ID[i]])        
	    $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b00},
	        read_reg,TX_PDM_PORT_ID[TX_PDM_PORT_ID[i]]);
	                 
        // Read 2 - PA,BurstVAL        		   
        MPI_Read (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b01}, read_reg);
	  if (read_reg != {TX_PDM_PA[TX_PDM_PORT_ID[i]],1'b0,TX_PDM_BVAL[TX_PDM_PORT_ID[i]]})
	    $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b01},
	         read_reg,{TX_PDM_PA[TX_PDM_PORT_ID[i]],1'b0,TX_PDM_BVAL[TX_PDM_PORT_ID[i]]});

        // Read 3 - MBEN,M,BankID   		  
        MPI_Read (MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b10}, read_reg); 
	  if (read_reg != {4'b0000,TX_PDM_MBEN[TX_PDM_PORT_ID[i]],TX_PDM_M_BIT[TX_PDM_PORT_ID[i]],
		   TX_PDM_BANK_ID[TX_PDM_PORT_ID[i]]})
	    $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR + {TX_PDM_PORT_ID[i], 2'b10},
	         read_reg,{4'b0000,TX_PDM_MBEN[TX_PDM_PORT_ID[i]],TX_PDM_M_BIT[TX_PDM_PORT_ID[i]],TX_PDM_BANK_ID[TX_PDM_PORT_ID[i]]});
		  
        // Read 4 - unused

     end
      
// Rx PDM
      
    MPI_Write (18'h30917,8'b0001_0000);
    
    MPI_Read  (18'h30917, read_reg);
	  if (read_reg != 8'b0001_0000)
	    $display("Read back ERROR on %h read %b expect %b", 18'h30917,read_reg,8'b0001_0000);

    MEMORY_BASE_ADDR = 18'h31000;

    for (i=0;i<=(RX_PDM_ACTIVE_PORTS-1'd1);i=i+1)
      begin

          MPI_Read (MEMORY_BASE_ADDR + RX_PDM_ACTIVE_PORT_ID[i], read_reg);
	    if (read_reg != {3'b000, RX_PDM_BANK_ID[i], RX_PDM_PA[i]})
	      $display("Read back ERROR on %h read %b expect %b", MEMORY_BASE_ADDR + RX_PDM_ACTIVE_PORT_ID[i],
	            read_reg,{3'b000, RX_PDM_BANK_ID[i], RX_PDM_PA[i]});
      
      end

      MEMORY_BASE_ADDR = 18'h31000;

  end
endtask

task verify_regs;

reg [7:0] read_reg;

  begin

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Rx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Read (18'h30900, read_reg);
      if (read_reg != CALENDAR_M_RX)
        $display("Read back ERROR on %h read %b expect %b", 18'h30900,read_reg,CALENDAR_M_RX);
	
    MPI_Read (18'h30901, read_reg);
      if (read_reg != {6'b00_0000,CALENDAR_LEN_RX[9:8]})
        $display("Read back ERROR on %h read %b expect %b", 18'h30901,read_reg,CALENDAR_LEN_RX[9:8]);
    
    MPI_Read (18'h30902, read_reg);
      if (read_reg != CALENDAR_LEN_RX[7:0])
        $display("Read back ERROR on %h read %b expect %b", 18'h30902,read_reg,CALENDAR_LEN_RX[7:0]);
				      
    MPI_Read (18'h30903, read_reg);
      if (read_reg != CALENDAR_M_RX_SHDW)
        $display("Read back ERROR on %h read %b expect %b", 18'h30903,read_reg,CALENDAR_M_RX_SHDW);

    MPI_Read (18'h30904, read_reg);
      if (read_reg != {6'b00_0000,CALENDAR_LEN_RX_SHDW[9:8]})
        $display("Read back ERROR on %h read %b expect %b", 18'h30904,read_reg,{6'b00_0000,CALENDAR_LEN_RX_SHDW[9:8]});

    MPI_Read (18'h30905, read_reg);
      if (read_reg != CALENDAR_LEN_RX_SHDW[7:0])
        $display("Read back ERROR on %h read %b expect %b", 18'h30905,read_reg,CALENDAR_LEN_RX_SHDW[7:0]);
   
    MPI_Read (18'h30906, read_reg);
      if (read_reg != RX_DPRAM_PART_SIZE)
        $display("Read back ERROR on %h read %b expect %b", 18'h30906,read_reg,RX_DPRAM_PART_SIZE);

    MPI_Read (18'h30907, read_reg);
      if (read_reg != RX_DPRAM_AGGR_MODE)
        $display("Read back ERROR on %h read %b expect %b", 18'h30907,read_reg,RX_DPRAM_AGGR_MODE);

    MPI_Read (18'h30910, read_reg);
      if (read_reg != {1'b0,LOSS_SYNC,DISABLE_STATUS,MASK_DIP4,EN_TRAINING,EN_BASELINE})
        $display("Read back ERROR on %h read %b expect %b", 18'h30910,read_reg,{1'b0,LOSS_SYNC,DISABLE_STATUS,MASK_DIP4,EN_TRAINING,EN_BASELINE});

    MPI_Read (18'h30911, read_reg);
      if (read_reg != FIFO_THRESHOLD_H_RX)
        $display("Read back ERROR on %h read %b expect %b", 18'h30911,read_reg,FIFO_THRESHOLD_H_RX);

    MPI_Read (18'h30912, read_reg);
      if (read_reg != DPRAM_RX_FIFO_OVER_UR_RUN_INT_EN)
        $display("Read back ERROR on %h read %b expect %b", 18'h30912,read_reg,DPRAM_RX_FIFO_OVER_UR_RUN_INT_EN);

    MPI_Read (18'h30913, read_reg);
      if (read_reg != RDI_INT_EN)
        $display("Read back ERROR on %h read %b expect %b", 18'h30913,read_reg,RDI_INT_EN);

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Tx/Rx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Read (18'h30914, read_reg);
      if (read_reg != {2'b00,SOP_DIP_ASF_INT_EN})
        $display("Read back ERROR on %h read %b expect %b", 18'h30914,read_reg,{2'b00,SOP_DIP_ASF_INT_EN});
      
    MPI_Read (18'h30915, read_reg);
      if (read_reg != {1'b0,LS_STIO_LB_FERR})
        $display("Read back ERROR on %h read %b expect %b", 18'h30915,read_reg,{2'b00,LS_STIO_LB_FERR});
      
    MPI_Read (18'h30916, read_reg);
     if (read_reg != {4'b0000,CALENDAR_SW_EN_RX,CALENDAR_SW_SEL_RX,CALENDAR_SW_EN_TX,TX_BURST_TERMINATION})
        $display("Read back ERROR on %h read %b expect %b", 18'h30916,read_reg,
	  {4'b0000,CALENDAR_SW_EN_RX,CALENDAR_SW_SEL_RX,CALENDAR_SW_EN_TX,TX_BURST_TERMINATION});

    MPI_Read (18'h30920, read_reg); 
     if (read_reg != DPRAM_FULL_EMPTY_SEL)
        $display("Read back ERROR on %h read %b expect %b", 18'h30920,read_reg,DPRAM_FULL_EMPTY_SEL);

// +++++++++++++++++++++++++++++++++++++++++++++++++++++
// SPI-4 Core A Tx Control Registers
// +++++++++++++++++++++++++++++++++++++++++++++++++++++

    MPI_Read (18'h30921, read_reg);
     if (read_reg != CALENDAR_M_TX)
       $display("Read back ERROR on %h read %b expect %b", 18'h30921,read_reg,CALENDAR_M_TX);

    MPI_Read (18'h30922, read_reg);
     if (read_reg != {6'b00_0000,CALENDAR_LEN_TX[9:8]})
       $display("Read back ERROR on %h read %b expect %b", 18'h30922,read_reg,{6'b00_0000,CALENDAR_LEN_TX[9:8]});
     
    MPI_Read (18'h30923, read_reg);
     if (read_reg != CALENDAR_LEN_TX[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30923,read_reg,CALENDAR_LEN_TX[7:0]);

    MPI_Read (18'h30924, read_reg);
     if (read_reg != CALENDAR_M_TX_SHDW)
       $display("Read back ERROR on %h read %b expect %b", 18'h30924,read_reg,CALENDAR_M_TX_SHDW);
     
    MPI_Read (18'h30925, read_reg);
     if (read_reg != {6'b00_0000,CALENDAR_LEN_TX_SHDW[9:8]})
       $display("Read back ERROR on %h read %b expect %b", 18'h30925,read_reg,{6'b00_0000,CALENDAR_LEN_TX_SHDW[9:8]});
     
    MPI_Read (18'h30926, read_reg);
     if (read_reg != CALENDAR_LEN_TX_SHDW[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30926,read_reg,CALENDAR_LEN_TX_SHDW[7:0]);
				      
    MPI_Read (18'h30927, read_reg);
     if (read_reg != TX_DPRAM_PART_SIZE)
       $display("Read back ERROR on %h read %b expect %b", 18'h30927,read_reg,TX_DPRAM_PART_SIZE);
     
    MPI_Read (18'h30930, read_reg);
     if (read_reg != TX_DPRAM_AGGR_MODE)
       $display("Read back ERROR on %h read %b expect %b", 18'h30930,read_reg,TX_DPRAM_AGGR_MODE);

    MPI_Read (18'h30931, read_reg);
     if (read_reg != {6'b00_0000,MAX_BURST1[9:8]})
       $display("Read back ERROR on %h read %b expect %b", 18'h30931,read_reg,{6'b00_0000,MAX_BURST1[9:8]});
     
    MPI_Read (18'h30932, read_reg);
     if (read_reg != MAX_BURST1[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30932,read_reg,MAX_BURST1[7:0]);

    MPI_Read (18'h30933, read_reg);
     if (read_reg != {6'b00_0000,MAX_BURST2[9:8]})
       $display("Read back ERROR on %h read %b expect %b", 18'h30933,read_reg,{6'b00_0000,MAX_BURST2[9:8]});
     
    MPI_Read (18'h30934, read_reg);
     if (read_reg != MAX_BURST2[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30934,read_reg,MAX_BURST2[7:0]);

    MPI_Read (18'h30935, read_reg);
     if (read_reg != DATA_MAX_T[31:24])
       $display("Read back ERROR on %h read %b expect %b", 18'h30935,read_reg,DATA_MAX_T[31:24]);
     
    MPI_Read (18'h30936, read_reg);
     if (read_reg != DATA_MAX_T[23:16])
       $display("Read back ERROR on %h read %b expect %b", 18'h30936,read_reg,DATA_MAX_T[23:16]);
     
    MPI_Read (18'h30937, read_reg);
     if (read_reg != DATA_MAX_T[15:8])
       $display("Read back ERROR on %h read %b expect %b", 18'h30937,read_reg,DATA_MAX_T[15:8]);
     
    MPI_Read (18'h30940, read_reg);
     if (read_reg != DATA_MAX_T[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30940,read_reg,DATA_MAX_T[7:0]);

    MPI_Read (18'h30941, read_reg);
     if (read_reg != ALPHA[15:8])
       $display("Read back ERROR on %h read %b expect %b", 18'h30941,read_reg,ALPHA[15:8]);
     
    MPI_Read (18'h30942, read_reg);
     if (read_reg != ALPHA[7:0])
       $display("Read back ERROR on %h read %b expect %b", 18'h30942,read_reg,ALPHA[7:0]);

    MPI_Read (18'h30943, read_reg);
     if (read_reg != DPRAM_TX_FIFO_OVER_UR_RUN_INT_EN)
       $display("Read back ERROR on %h read %b expect %b", 18'h30943,read_reg,DPRAM_TX_FIFO_OVER_UR_RUN_INT_EN);

    MPI_Read (18'h30944, read_reg);
     if (read_reg != {5'b0_0000,DIP2_ERR_TH})
       $display("Read back ERROR on %h read %b expect %b", 18'h30944,read_reg,{5'b0_0000,DIP2_ERR_TH});

    MPI_Read (18'h30945, read_reg);
     if (read_reg != {3'b000,FIFO_THRESHOLD_H_TX})
       $display("Read back ERROR on %h read %b expect %b", 18'h30945,read_reg,{3'b000,FIFO_THRESHOLD_H_TX});

//
// Status Registers
//
    MPI_Read (18'h3090a, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090a,read_reg,8'b0);
   
    MPI_Read (18'h3090b, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090b,read_reg,8'b0);

//

    MPI_Read (18'h3090c, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090c,read_reg,8'b0);

    MPI_Read (18'h3090d, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090d,read_reg,8'b0);

    MPI_Read (18'h3090e, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090e,read_reg,8'b0);

    MPI_Read (18'h3090f, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3090f,read_reg,8'b0);

    MPI_Read (18'h30918, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h30918,read_reg,8'b0);

    MPI_Read (18'h30919, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h30919,read_reg,8'b0);

    MPI_Read (18'h3091a, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3091a,read_reg,8'b0);

    MPI_Read (18'h3091b, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3091b,read_reg,8'b0);

//
   
    MPI_Read (18'h3091c, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3091c,read_reg,8'b0);

    MPI_Read (18'h3091d, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3091d,read_reg,8'b0);

//

    MPI_Read (18'h30928, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h30928,read_reg,8'b0);

    MPI_Read (18'h30929, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h30929,read_reg,8'b0);

    MPI_Read (18'h3092a, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092a,read_reg,8'b0);

    MPI_Read (18'h3092b, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092b,read_reg,8'b0);
   
    MPI_Read (18'h3092c, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092c,read_reg,8'b0);

    MPI_Read (18'h3092d, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092d,read_reg,8'b0);

    MPI_Read (18'h3092e, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092e,read_reg,8'b0);

    MPI_Read (18'h3092f, read_reg);
     if (read_reg != 8'b0)
       $display("Read back ERROR on %h read %b expect %b", 18'h3092f,read_reg,8'b0);
   
end
  
endtask

//
//
//

task verify_control;
  begin
//      if (toptest.orspii_asb.mpi.CAL_M_RX_MAIN_A != CALENDAR_M_RX)
//       $display("Output control error on CALENDAR_M_RX_A");     	
  
  end
endtask
