// Copyright (c) 2002 - Lattice Semiconductor
//                    - August 2002.
//
// This program is controlled by a written license agreement.
// Unauthorized Reproduction or Use is Expressly Prohibited.
// ********************************************************************
//
//
//  Name   : spi_324p_o4_1_001
//
//  Parent : none
//
//  Children : rtop [1-4]
//           : ttop [1-4]
//           : pssmux
//
//  Overview: Black box model of quad-SPI3/SPI4 bridge designed for the ORSPII FPSC.
//
//  Log:
//
//  Revision 1.0 10/10/02 Mike Hammer
//                        Vishnu Balaraman
//
//  Initial revision
//  Modified :  01/07/03 Changed to allow this model to be instantiated under
//           :           orspi.v top level (mph).
//           :  05/22/03 Created black box model (mph).
//           :  07/18/03 Changed name of core (mph).
//
// *********************************************************************

`timescale 1 ns/100 ps

`include "qspi3_define.v"

module spi_324p_o4_1_001 (

   sys_reset,      // system reset (active high)

   rfclk0_int,     // 104 MHz SPI-3 interface clock 
   rfclk0_int_ph,
   renb0,          // spi3 receive enable 
   renb_a0,   
   renb_b0,   

   rsx0,           // spi3 receive start of transmission 
   rsop0,          // spi3 receive start of packet
   reop0,          // spi3 receive end of packet
   rprty0,         // spi3 receive parity
   rval0,          // spi3 receive valid
   rerr0,          // spi3 receive error
   rmod0,          // spi3 receive word modulo
   rdat0,          // spi3 receive data

   rx_re0,         // ASB receive side read enable
   rx_a0,          // ASB receive side read address
   rx_fifo_empty0, // ASB receive side fifo empty
   rxd0,           // ASB receive side data

   tenb0,          // spi3 transmit enable
   tdat0,          // spi3 transmit data
   tmod0,          // spi3 transmit word modulo
   tprty0,         // spi3 transmit parity
   tsop0,          // spi3 transmit start of packet
   teop0,          // spi3 transmit end of packet
   terr0,          // spi3 transmit error
   tsx0,           // spi3 transmit start of transmission
   dtpa0,          // spi3 direct transmit packet available
   stpa0,          // spi3 selected PHY transmit packet available
   ptpa0,          // spi3 polled-PHY transmit packet available
   tadr0,          // spi3 transmit PHY address

   txd0,           // ASB transmit side data
   tx_we0,         // ASB transmit side write enable
   tx_a0,          // ASB transmit side address
   wcntrst0,       // ASB write counter reset
   fifofull0,      // ASB FIFO full
   tx_port0,       // ASB transmit port
   tx_portid0,     // ASB transmit port ID
   txbkp0,          
   txstat0,        // ASB transmit status

`ifdef NUMINT2

   rfclk1_int,     // 104 MHz SPI-3 interface clock 
   rfclk1_int_ph,
   renb1,          // spi3 receive enable 
   renb_a1,   
   renb_b1,   

   rsx1,           // spi3 receive start of transmission 
   rsop1,          // spi3 receive start of packet
   reop1,          // spi3 receive end of packet
   rprty1,         // spi3 receive parity
   rval1,          // spi3 receive valid
   rerr1,          // spi3 receive error
   rmod1,          // spi3 receive word modulo
   rdat1,          // spi3 receive data

   rx_re1,         // ASB receive side read enable
   rx_a1,          // ASB receive side read address
   rx_fifo_empty1, // ASB receive side fifo empty
   rxd1,           // ASB receive side data
   tenb1,          // spi3 transmit enable
   tdat1,          // spi3 transmit data
   tmod1,          // spi3 transmit word modulo
   tprty1,         // spi3 transmit parity
   tsop1,          // spi3 transmit start of packet
   teop1,          // spi3 transmit end of packet
   terr1,          // spi3 transmit error
   tsx1,           // spi3 transmit start of transmission
   dtpa1,          // spi3 direct transmit packet available
   stpa1,          // spi3 selected PHY transmit packet available
   ptpa1,          // spi3 polled-PHY transmit packet available
   tadr1,          // spi3 transmit PHY address
   txd1,           // ASB transmit side data
   tx_we1,         // ASB transmit side write enable
   tx_a1,          // ASB transmit side address
   wcntrst1,       // ASB write counter reset
   fifofull1,      // ASB FIFO full
   tx_port1,       // ASB transmit port
   tx_portid1,     // ASB transmit port ID
   txbkp1,          
   txstat1,        // ASB transmit status

`endif

`ifdef NUMINT3

   rfclk2_int,     // 104 MHz SPI-3 interface clock 
   rfclk2_int_ph,
   renb2,          // spi3 receive enable 
   renb_a2,   
   renb_b2,   

   rsx2,           // spi3 receive start of transmission 
   rsop2,          // spi3 receive start of packet
   reop2,          // spi3 receive end of packet
   rprty2,         // spi3 receive parity
   rval2,          // spi3 receive valid
   rerr2,          // spi3 receive error
   rmod2,          // spi3 receive word modulo
   rdat2,          // spi3 receive data
   rx_re2,         // ASB receive side read enable
   rx_a2,          // ASB receive side read address
   rx_fifo_empty2, // ASB receive side fifo empty
   rxd2,           // ASB receive side data

   tenb2,          // spi3 transmit enable
   tdat2,          // spi3 transmit data
   tmod2,          // spi3 transmit word modulo
   tprty2,         // spi3 transmit parity
   tsop2,          // spi3 transmit start of packet
   teop2,          // spi3 transmit end of packet
   terr2,          // spi3 transmit error
   tsx2,           // spi3 transmit start of transmission
   dtpa2,          // spi3 direct transmit packet available
   stpa2,          // spi3 selected PHY transmit packet available
   ptpa2,          // spi3 polled-PHY transmit packet available
   tadr2,          // spi3 transmit PHY address
   txd2,           // ASB transmit side data
   tx_we2,         // ASB transmit side write enable
   tx_a2,          // ASB transmit side address
   wcntrst2,       // ASB write counter reset
   fifofull2,      // ASB FIFO full
   tx_port2,       // ASB transmit port
   tx_portid2,     // ASB transmit port ID
   txbkp2,          
   txstat2,        // ASB transmit status

`endif

`ifdef NUMINT4

   rfclk3_int,     // 104 MHz SPI-3 interface clock 
   rfclk3_int_ph,
   renb3,          // spi3 receive enable 
   renb_a3,   
   renb_b3,   

   rsx3,           // spi3 receive start of transmission 
   rsop3,          // spi3 receive start of packet
   reop3,          // spi3 receive end of packet
   rprty3,         // spi3 receive parity
   rval3,          // spi3 receive valid
   rerr3,          // spi3 receive error
   rmod3,          // spi3 receive word modulo
   rdat3,          // spi3 receive data

   rx_re3,         // ASB receive side read enable
   rx_a3,          // ASB receive side read address
   rx_fifo_empty3, // ASB receive side fifo empty
   rxd3,           // ASB receive side data

   tenb3,          // spi3 transmit enable
   tdat3,          // spi3 transmit data
   tmod3,          // spi3 transmit word modulo
   tprty3,         // spi3 transmit parity
   tsop3,          // spi3 transmit start of packet
   teop3,          // spi3 transmit end of packet
   terr3,          // spi3 transmit error
   tsx3,           // spi3 transmit start of transmission
   dtpa3,          // spi3 direct transmit packet available
   stpa3,          // spi3 selected PHY transmit packet available
   ptpa3,          // spi3 polled-PHY transmit packet available
   tadr3,          // spi3 transmit PHY address

   txd3,           // ASB transmit side data
   tx_we3,         // ASB transmit side write enable
   tx_a3,          // ASB transmit side address
   wcntrst3,       // ASB write counter reset
   fifofull3,      // ASB FIFO full
   tx_port3,       // ASB transmit port
   tx_portid3,     // ASB transmit port ID
   txbkp3,          
   txstat3,        // ASB transmit status

`endif

   mpi_clk,        // 
   us_rdata,       //
   us_wdata,       //
   us_addr,        //
   us_wr,          //
   us_ack,         //
   us_err,         //
   us_rdy,         //
   us_retry,       //
   us_irq,         //
   us_burst,       //
   us_size,        //
   
   rx_ext_status_enable,  // ASB PSS status enable
   rx_fpga_port_id,       // ASB PSS port id
   rx_port_status,        // ASB PSS port status
   rx_pss_we              // ASB PSS write enable pulse

`ifdef NUMPORTS1
)  /* synthesis syn_black_box black_box_pad_pin = "renb0,renb_a0,renb_b0,rsx0,rsop0,reop0,rprty0,rval0,rerr0,rmod0[1:0],rdat0[31:0],tenb0,tdat0[31:0],tmod0[1:0],tprty0,tsop0,teop0,terr0,tsx0,dtpa0[0],renb1,renb_a1,renb_b1,rsx1,rsop1,reop1,rprty1,rval1,rerr1,rmod1[1:0],rdat1[31:0],tenb1,tdat1[31:0],tmod1[1:0],tprty1,tsop1,teop1,terr1,tsx1,dtpa1[0],renb2,renb_a2,renb_b2,rsx2,rsop2,reop2,rprty2,rval2,rerr2,rmod2[1:0],rdat2[31:0],tenb2,tdat2[31:0],tmod2[1:0],tprty2,tsop2,teop2,terr2,tsx2,dtpa2[0],renb3,renb_a3,renb_b3,rsx3,rsop3,reop3,rprty3,rval3,rerr3,rmod3[1:0],rdat3[31:0],tenb3,tdat3[31:0],tmod3[1:0],tprty3,tsop3,teop3,terr3,tsx3,dtpa3[0]" */;
   /* synthesis syn_props=""IP_Version = Ver1_0"" */
   /* exemplar attribute spi_324p_o4_1_001 IP_Version Ver1_0 */
`endif

`ifdef NUMPORTS2
)  /* synthesis syn_black_box black_box_pad_pin = "renb0,renb_a0,renb_b0,rsx0,rsop0,reop0,rprty0,rval0,rerr0,rmod0[1:0],rdat0[31:0],tenb0,tdat0[31:0],tmod0[1:0],tprty0,tsop0,teop0,terr0,tsx0,dtpa0[1:0],renb1,renb_a1,renb_b1,rsx1,rsop1,reop1,rprty1,rval1,rerr1,rmod1[1:0],rdat1[31:0],tenb1,tdat1[31:0],tmod1[1:0],tprty1,tsop1,teop1,terr1,tsx1,dtpa1[1:0],renb2,renb_a2,renb_b2,rsx2,rsop2,reop2,rprty2,rval2,rerr2,rmod2[1:0],rdat2[31:0],tenb2,tdat2[31:0],tmod2[1:0],tprty2,tsop2,teop2,terr2,tsx2,dtpa2[1:0],renb3,renb_a3,renb_b3,rsx3,rsop3,reop3,rprty3,rval3,rerr3,rmod3[1:0],rdat3[31:0],tenb3,tdat3[31:0],tmod3[1:0],tprty3,tsop3,teop3,terr3,tsx3,dtpa3[1:0]" */;
   /* synthesis syn_props=""IP_Version = Ver1_0"" */
   /* exemplar attribute spi_324p_o4_1_001 IP_Version Ver1_0 */
`endif 

`ifdef NUMPORTS4
)  /* synthesis syn_black_box black_box_pad_pin = "renb0,renb_a0,renb_b0,rsx0,rsop0,reop0,rprty0,rval0,rerr0,rmod0[1:0],rdat0[31:0],tenb0,tdat0[31:0],tmod0[1:0],tprty0,tsop0,teop0,terr0,tsx0,dtpa0[3:0],renb1,renb_a1,renb_b1,rsx1,rsop1,reop1,rprty1,rval1,rerr1,rmod1[1:0],rdat1[31:0],tenb1,tdat1[31:0],tmod1[1:0],tprty1,tsop1,teop1,terr1,tsx1,dtpa1[3:0],renb2,renb_a2,renb_b2,rsx2,rsop2,reop2,rprty2,rval2,rerr2,rmod2[1:0],rdat2[31:0],tenb2,tdat2[31:0],tmod2[1:0],tprty2,tsop2,teop2,terr2,tsx2,dtpa2[3:0],renb3,renb_a3,renb_b3,rsx3,rsop3,reop3,rprty3,rval3,rerr3,rmod3[1:0],rdat3[31:0],tenb3,tdat3[31:0],tmod3[1:0],tprty3,tsop3,teop3,terr3,tsx3,dtpa3[3:0]" */;
   /* synthesis syn_props=""IP_Version = Ver1_0"" */
   /* exemplar attribute spi_324p_o4_1_001 IP_Version Ver1_0 */
`endif

`ifdef NUMPORTS8
)  /* synthesis syn_black_box black_box_pad_pin = "renb0,renb_a0,renb_b0,rsx0,rsop0,reop0,rprty0,rval0,rerr0,rmod0[1:0],rdat0[31:0],tenb0,tdat0[31:0],tmod0[1:0],tprty0,tsop0,teop0,terr0,tsx0,dtpa0[7:0],renb1,renb_a1,renb_b1,rsx1,rsop1,reop1,rprty1,rval1,rerr1,rmod1[1:0],rdat1[31:0],tenb1,tdat1[31:0],tmod1[1:0],tprty1,tsop1,teop1,terr1,tsx1,dtpa1[7:0],renb2,renb_a2,renb_b2,rsx2,rsop2,reop2,rprty2,rval2,rerr2,rmod2[1:0],rdat2[31:0],tenb2,tdat2[31:0],tmod2[1:0],tprty2,tsop2,teop2,terr2,tsx2,dtpa2[7:0],renb3,renb_a3,renb_b3,rsx3,rsop3,reop3,rprty3,rval3,rerr3,rmod3[1:0],rdat3[31:0],tenb3,tdat3[31:0],tmod3[1:0],tprty3,tsop3,teop3,terr3,tsx3,dtpa3[7:0]" */;
   /* synthesis syn_props=""IP_Version = Ver1_0"" */
   /* exemplar attribute spi_324p_o4_1_001 IP_Version Ver1_0 */
`endif

// ------------------------------
// USER DEFINED GLOBAL PARAMETERS
// ------------------------------


// parameters for SPI3 bridge
parameter num_fifo  = `NUM_FIFO;  //1,2,4,8 : number of FCFIFOs per SPI3 interface
parameter fifo_selb = `FIFO_SELB; //3,2,1   : number of bits used for fifo select
parameter port_selb = `PORT_SELB; //5,4,3,2,1 : number of bits used for port select
parameter width     = `WIDTH;     //5,6,7,8 : width of read/write counters in bits
parameter burst_len = `BURST_LEN; //256,128,64,32 : burst length in bytes
parameter pcnt      = 16;         // number of bits in FCFIFO EOP shift register

// parameters for receive side of SPI3 bridge
parameter smfifo_thr = 5'd23; //    : rx smoothing FIFO almost-full threshold

// parameters for transmit side of SPI3 bridge
parameter ports      = `PORTS;

// receive side I/O
input        sys_reset;    // system reset (active high)

// ------------------------------
// INTERFACE NUMBER 0 I/O SIGNALS
// ------------------------------
input          rfclk0_int;
input          rfclk0_int_ph;
input          renb0;
input          renb_a0;
input          renb_b0;
     
output         rsx0;
output         rsop0;
output         reop0;
output         rprty0;
output         rval0;
output         rerr0;
output [1:0]   rmod0;
output [31:0]  rdat0;

output         rx_re0;
output [2:0]   rx_a0;
input          rx_fifo_empty0;
input [39:0]   rxd0;

input          tenb0;
input [31:0]   tdat0;
input [1:0]    tmod0;
input          tprty0;
input          tsop0;
input          teop0;
input          terr0;
input          tsx0;
output [ports-1:0]    dtpa0;
output         stpa0;
output         ptpa0;
input [5:0]    tadr0;

output [38:0]  txd0;
output         tx_we0;
output [2:0]   tx_a0;
output         wcntrst0;
input          fifofull0;
output [7:0]   tx_port0;
input [7:0]    tx_portid0;
input          txbkp0;
input [1:0]    txstat0;

`ifdef NUMINT2 

// ------------------------------
// INTERFACE NUMBER 1 I/O SIGNALS
// ------------------------------
input          rfclk1_int;
input          rfclk1_int_ph;
input          renb1;
input          renb_a1;
input          renb_b1;
     
output         rsx1;
output         rsop1;
output         reop1;
output         rprty1;
output         rval1;
output         rerr1;
output [1:0]   rmod1;
output [31:0]  rdat1;

output         rx_re1;
output [2:0]   rx_a1;
input          rx_fifo_empty1;
input [39:0]   rxd1;

input          tenb1;
input [31:0]   tdat1;
input [1:0]    tmod1;
input          tprty1;
input          tsop1;
input          teop1;
input          terr1;
input          tsx1;
output [ports-1:0]    dtpa1;
output         stpa1;
output         ptpa1;
input [5:0]    tadr1;

output [38:0]  txd1;
output         tx_we1;
output [2:0]   tx_a1;
output         wcntrst1;
input          fifofull1;
output [7:0]   tx_port1;
input [7:0]    tx_portid1;
input          txbkp1;
input [1:0]    txstat1;

`endif 

`ifdef NUMINT3

// ------------------------------
// INTERFACE NUMBER 2 I/O SIGNALS
// ------------------------------
input          rfclk2_int;
input          rfclk2_int_ph;
input          renb2;
input          renb_a2;
input          renb_b2;
     
output         rsx2;
output         rsop2;
output         reop2;
output         rprty2;
output         rval2;
output         rerr2;
output [1:0]   rmod2;
output [31:0]  rdat2;

output         rx_re2;
output [2:0]   rx_a2;
input          rx_fifo_empty2;
input [39:0]   rxd2;

input          tenb2;
input [31:0]   tdat2;
input [1:0]    tmod2;
input          tprty2;
input          tsop2;
input          teop2;
input          terr2;
input          tsx2;
output [ports-1:0]    dtpa2;
output         stpa2;
output         ptpa2;
input [5:0]    tadr2;

output [38:0]  txd2;
output         tx_we2;
output [2:0]   tx_a2;
output         wcntrst2;
input          fifofull2;
output [7:0]   tx_port2;
input [7:0]    tx_portid2;
input          txbkp2;
input [1:0]    txstat2;

`endif 

`ifdef NUMINT4

// ------------------------------
// INTERFACE NUMBER 3 I/O SIGNALS
// ------------------------------
input          rfclk3_int;
input          rfclk3_int_ph;
input          renb3;
input          renb_a3;
input          renb_b3;
     
output         rsx3;
output         rsop3;
output         reop3;
output         rprty3;
output         rval3;
output         rerr3;
output [1:0]   rmod3;
output [31:0]  rdat3;

output         rx_re3;
output [2:0]   rx_a3;
input          rx_fifo_empty3;
input [39:0]   rxd3;

input          tenb3;
input [31:0]   tdat3;
input [1:0]    tmod3;
input          tprty3;
input          tsop3;
input          teop3;
input          terr3;
input          tsx3;
output [ports-1:0]    dtpa3;
output         stpa3;
output         ptpa3;
input [5:0]    tadr3;

output [38:0]  txd3;
output         tx_we3;
output [2:0]   tx_a3;
output         wcntrst3;
input          fifofull3;
output [7:0]   tx_port3;
input [7:0]    tx_portid3;
input          txbkp3;
input [1:0]    txstat3;

`endif 

// -------------------------
// MICROPROCESSOR INTERFACE
// -------------------------
input          mpi_clk;
output [35:0]  us_rdata;
input  [35:0]  us_wdata;
input  [17:0]  us_addr;
input          us_wr;
output         us_ack;
output         us_err;
input          us_rdy;
output         us_retry;
output         us_irq;
input          us_burst;
input  [1:0]   us_size;

// -------------------------
// COMMON OUTPUTS TO ASB PSS
// -------------------------
output        rx_ext_status_enable;
output [7:0]  rx_fpga_port_id;
output [1:0]  rx_port_status;
output        rx_pss_we;

endmodule
