
//Register (SPI/O and FIFO) configuration file 03

//Calendar configuration 

CALENDAR_M_RX           = 8'd7;
CALENDAR_LEN_RX         = 10'd16;

CALENDAR_M_RX_SHDW      = 8'd7;
CALENDAR_LEN_RX_SHDW    = 10'd16;

CALENDAR_SW_EN_RX       = 1'b0;
CALENDAR_SW_SEL_RX      = 1'b0;

CALENDAR_M_TX           = 8'd7;
CALENDAR_LEN_TX         = 10'd16;

CALENDAR_M_TX           = 8'd7;
CALENDAR_LEN_TX         = 10'd16;

CALENDAR_SW_EN_TX       = 1'b0;

TX_BURST_TERMINATION    = 1'b0;

//RX Async FIFO Threshold 

FIFO_THRESHOLD_H_RX = 8'd120;
FIFO_THRESHOLD_H_TX = 5'h17;

//Maxburst 1 and 2 values

MAX_BURST1 = 10'd16; 
MAX_BURST2 = 10'd8; 

// MAX_BURST1_RX = 512/RX_PDM_ACTIVE_PORTS * 0.4; 
// MAX_BURST2_RX = 512/RX_PDM_ACTIVE_PORTS * 0.2; 

//Limit 64byte bursts, Loss Sync count value
//Enable training detection (RX) and Baseline (?)

DISABLE_STATUS = 1'b0;
MASK_DIP4 = 1'b0;
LOSS_SYNC = 3'd7;
EN_TRAINING = 1'b0;
EN_BASELINE = 1'b0;
DIP2_ERR_TH = 3'd4;

//Training configuration (TX)

DATA_MAX_T = 32'd300;
ALPHA = 16'd2;

// Interrupt Enables

RDI_PLL_LOL_INT_EN   = 1'b0;
RDI_BAS_DONE_INT_EN  = 1'b0;
RDI_BAS_ERR_INT_EN   = 1'b0;
RDI_DSKW_DONE_INT_EN = 1'b0;
RDI_DSKW_ERR_INT_EN  = 1'b0;
RDI_TRN_DET_INT_EN   = 1'b0;
ALGN_OFF_INT_EN      = 1'b0;
TX_STATUS_LOF_INT_EN = 1'b0;

RDI_INT_EN = {RDI_PLL_LOL_INT_EN, 
              RDI_BAS_DONE_INT_EN,
	      RDI_BAS_ERR_INT_EN,
	      RDI_DSKW_DONE_INT_EN,
	      RDI_DSKW_ERR_INT_EN,
	      RDI_TRN_DET_INT_EN,
	      ALGN_OFF_INT_EN,
	      TX_STATUS_LOF_INT_EN};

ILLEGAL_CTL_EN = 1'b0;
RX_SOP_ALIGN_ERR_INT_EN = 1'b0;
TX_SOP_ALIGN_ERR_INT_EN = 1'b0;
DIP4_ERR_INT_EN = 1'b0;
DIP2_ERR_INT_EN = 1'b0;
ASYNC_FIFO_RX_OVRRUN_INT_EN = 1'b1;

SOP_DIP_ASF_INT_EN = {ILLEGAL_CTL_EN,
                      RX_SOP_ALIGN_ERR_INT_EN,
                      TX_SOP_ALIGN_ERR_INT_EN,
		      DIP4_ERR_INT_EN,
		      DIP2_ERR_INT_EN,
		      ASYNC_FIFO_RX_OVRRUN_INT_EN};
  
  
//RX FIFO Overrun Interrupt Enables

DPRAM_0_RXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_1_RXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_2_RXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_3_RXFIFO_OVERRUN_INT_EN = 1'b1;

//TX FIFO Overrun Interrupt Enables

DPRAM_0_TXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_1_TXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_2_TXFIFO_OVERRUN_INT_EN = 1'b1;
DPRAM_3_TXFIFO_OVERRUN_INT_EN = 1'b1;

//RX FIFO Underrun Interrupt Enables

DPRAM_0_RXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_1_RXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_2_RXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_3_RXFIFO_URRUN_INT_EN = 1'b0;

//TX FIFO Underrun Interrupt Enables

DPRAM_0_TXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_1_TXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_2_TXFIFO_URRUN_INT_EN = 1'b0;
DPRAM_3_TXFIFO_URRUN_INT_EN = 1'b0;

DPRAM_RX_FIFO_OVER_UR_RUN_INT_EN = {DPRAM_0_RXFIFO_OVERRUN_INT_EN,
                                    DPRAM_1_RXFIFO_OVERRUN_INT_EN,
				    DPRAM_2_RXFIFO_OVERRUN_INT_EN,
				    DPRAM_3_RXFIFO_OVERRUN_INT_EN,
				    DPRAM_0_RXFIFO_URRUN_INT_EN,
				    DPRAM_1_RXFIFO_URRUN_INT_EN,
				    DPRAM_2_RXFIFO_URRUN_INT_EN,
				    DPRAM_3_RXFIFO_URRUN_INT_EN
                                    };

DPRAM_TX_FIFO_OVER_UR_RUN_INT_EN = {DPRAM_0_TXFIFO_OVERRUN_INT_EN,
                                    DPRAM_1_TXFIFO_OVERRUN_INT_EN,
				    DPRAM_2_TXFIFO_OVERRUN_INT_EN,
				    DPRAM_3_TXFIFO_OVERRUN_INT_EN,
				    DPRAM_0_TXFIFO_URRUN_INT_EN,
				    DPRAM_1_TXFIFO_URRUN_INT_EN,
				    DPRAM_2_TXFIFO_URRUN_INT_EN,
				    DPRAM_3_TXFIFO_URRUN_INT_EN
                                    };
				    
//FIFO Aggregation and Partition

RX_DPRAM_0_PART_SIZE = 2'b10;
RX_DPRAM_1_PART_SIZE = 2'b10;
RX_DPRAM_2_PART_SIZE = 2'b10;
RX_DPRAM_3_PART_SIZE = 2'b10;

RX_DPRAM_PART_SIZE = {RX_DPRAM_0_PART_SIZE,
                      RX_DPRAM_1_PART_SIZE,
		      RX_DPRAM_2_PART_SIZE,
		      RX_DPRAM_3_PART_SIZE};

RX_DPRAM_0_AGGR_MODE = 2'b00;
RX_DPRAM_1_AGGR_MODE = 2'b00;
RX_DPRAM_2_AGGR_MODE = 2'b00;
RX_DPRAM_3_AGGR_MODE = 2'b00;

RX_DPRAM_AGGR_MODE = {RX_DPRAM_0_AGGR_MODE,
                      RX_DPRAM_1_AGGR_MODE,
		      RX_DPRAM_2_AGGR_MODE,
		      RX_DPRAM_3_AGGR_MODE};

TX_DPRAM_0_PART_SIZE = 2'b10;
TX_DPRAM_1_PART_SIZE = 2'b10;
TX_DPRAM_2_PART_SIZE = 2'b10;
TX_DPRAM_3_PART_SIZE = 2'b10;

TX_DPRAM_PART_SIZE = {TX_DPRAM_0_PART_SIZE,
                      TX_DPRAM_1_PART_SIZE,
		      TX_DPRAM_2_PART_SIZE,
		      TX_DPRAM_3_PART_SIZE};

TX_DPRAM_0_AGGR_MODE = 2'b00;
TX_DPRAM_1_AGGR_MODE = 2'b00;
TX_DPRAM_2_AGGR_MODE = 2'b00;
TX_DPRAM_3_AGGR_MODE = 2'b00;

TX_DPRAM_AGGR_MODE = {TX_DPRAM_0_AGGR_MODE,
                      TX_DPRAM_1_AGGR_MODE,
		      TX_DPRAM_2_AGGR_MODE,
		      TX_DPRAM_3_AGGR_MODE};

//Full and Empty Fill Level Selects

TX_DPRAM_0_FULL_TYPE_SEL = 1'b1;
TX_DPRAM_1_FULL_TYPE_SEL = 1'b1;
TX_DPRAM_2_FULL_TYPE_SEL = 1'b1;
TX_DPRAM_3_FULL_TYPE_SEL = 1'b1;

RX_DPRAM_0_EMPTY_TYPE_SEL = 1'b0;
RX_DPRAM_1_EMPTY_TYPE_SEL = 1'b0;
RX_DPRAM_2_EMPTY_TYPE_SEL = 1'b0;
RX_DPRAM_3_EMPTY_TYPE_SEL = 1'b0;

DPRAM_FULL_EMPTY_SEL = {TX_DPRAM_0_FULL_TYPE_SEL,
                        TX_DPRAM_1_FULL_TYPE_SEL,
			TX_DPRAM_2_FULL_TYPE_SEL,
			TX_DPRAM_3_FULL_TYPE_SEL,
			RX_DPRAM_0_EMPTY_TYPE_SEL,
			RX_DPRAM_1_EMPTY_TYPE_SEL,
			RX_DPRAM_2_EMPTY_TYPE_SEL,
			RX_DPRAM_3_EMPTY_TYPE_SEL};

//SPI4.2 Speed, Status I/O, Loopback and Error Insert

LOW_SPEED_DATA_SEL = 1'b1;
LOOPBACK_FE = 1'b0;
STATUS_IO_SEL = 1'b0;
LOOPBACK_HS = 1'b0;
LOOPBACK_LS = 1'b0;
FORCE_DIP4_ERR = 1'b0;
FORCE_DIP2_ERR = 1'b0;

LS_STIO_LB_FERR = {LOOPBACK_FE,
LOW_SPEED_DATA_SEL,
                   STATUS_IO_SEL,
		   LOOPBACK_HS,
		   LOOPBACK_LS,
		   FORCE_DIP4_ERR,
		   FORCE_DIP2_ERR};

RX_EXT_STAT_EN = 1'b0;
