library verilog;
use verilog.vl_types.all;
entity ddr_initctrl is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        start_init      : in     vl_logic;
        count_trp       : in     vl_logic_vector(2 downto 0);
        count_tmrd      : in     vl_logic_vector(2 downto 0);
        count_trfc      : in     vl_logic_vector(3 downto 0);
        init_done       : out    vl_logic;
        ism_state_0     : out    vl_logic_vector(3 downto 0);
        ism_state_1     : out    vl_logic_vector(3 downto 0)
    );
end ddr_initctrl;
