// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
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// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
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// =============================================================================
//                         FILE DETAILS         
// Project          : DDR Controller 
// File             : ddrct_np_o4_1_008.v
// Title            : ddrct_np_o4_1_008
// Dependencies     : ddr_params.v
// Description      : This is the core module with generic, initctrl, datapath & 
// cmd exe modules.
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : Apr 03, 2001
// Changes Made     : Initial Creation
//
// =============================================================================

`timescale 100ps / 10ps

module  ddrct_np_o4_1_008(
        //-------INPUTS
        clk,                            // System clock
        clk2x,                          // 2x System clock
        reset_n,                        // Generic I/F Active low system reset
        cmd,                            // Generic I/F Command for controller
        dmsel,                          // Generic I/F Data mask inputs
        addr,                           // Generic I/F Address bus
        datain,                         // Generic I/F Data input bus
        ddr_dq_in,                      // DDR SDRAM I/F Data bus input 

        //-------OUTPUTS
        dataout,                        // Generic I/F Data output bus
        dataout_valid,                  // Generic I/F indicates Dataout bus has a valid data
        datain_valid,                   // Generic I/F indicates controller has accepted a data from Datain bus 
        busy,                           // Generic I/F Busy signal 
        ddr_cke,                        // DDR SDRAM I/F Clock enable
        ddr_cs_n,                       // DDR SDRAM I/F Chip select
        ddr_we_n,                       // DDR SDRAM I/F Write enable
        ddr_cas_n,                      // DDR SDRAM I/F Column address strobe
        ddr_ras_n,                      // DDR SDRAM I/F Row address strobe
        ddr_ad,                         // DDR SDRAM I/F Address bus
        ddr_ba,                         // DDR SDRAM I/F Bank bus
        ddr_dqoe,                       // DDR SDRAM I/F Data bus output enable signal 
        ddr_dq_out,                     // DDR SDRAM I/F Data bus output 
        ddr_dqm,                        // DDR SDRAM I/F Data mask lines
        ddr_dqsoe,                      // DDR SDRAM I/F Data strobe output enable signal 
        ddr_dqs_out                     // DDR SDRAM I/F Data strobe output 
        )/* synthesis syn_black_box */;

// ====================================================================
// Define all inputs / outputs
// ====================================================================
//--------Inputs
input                           clk;            // System clock
input                           clk2x;          // 2x System clock
input                           reset_n;        // Generic I/F Active low system reset
input   [2:0]                   cmd;            // Generic I/F Command for controller
input   [`DSIZE/8-1:0]          dmsel;          // Generic I/F Data mask select inputs
input   [`ASIZE-1:0]            addr;           // Generic I/F Address bus
input   [`DSIZE-1:0]            datain;         // Generic I/F Data input bus
input   [`DSIZE/2-1:0]          ddr_dq_in;      // DDR SDRAM I/F Data bus input 

        
//-------OUTPUTS
output  [`DSIZE-1:0]            dataout;        // Generic I/F Data output bus
output                          dataout_valid;  // Generic I/F indicates Dataout bus has a valid data
output                          datain_valid;   // Generic I/F indicates controller has 
                                                // accepted a data from Datain bus 
output                          busy;           // Generic I/F Busy signal 
output                          ddr_cke;        // DDR SDRAM I/F Clock enable
output  [`RANK-1:0]             ddr_cs_n;       // DDR SDRAM I/F Chip select
output                          ddr_we_n;       // DDR SDRAM I/F Write enable
output                          ddr_cas_n;      // DDR SDRAM I/F Column address strobe
output                          ddr_ras_n;      // DDR SDRAM I/F Row address strobe
output  [`RSIZE-1:0]            ddr_ad;         // DDR SDRAM I/F Address bus
output  [`BSIZE-1:0]            ddr_ba;         // DDR SDRAM I/F Bank bus
output  [`DSIZE/2-1:0]          ddr_dqoe;       // DDR SDRAM I/F Data bus output enable signal 
output  [`DSIZE/16-1:0]         ddr_dqsoe;      // DDR SDRAM I/F Data strobe output enable signal 
output  [`DSIZE/2-1:0]          ddr_dq_out;     // DDR SDRAM I/F Data bus output 
output  [`DSIZE/16-1:0]         ddr_dqm;        // DDR SDRAM I/F Data mask lines
output  [`DSIZE/16-1:0]         ddr_dqs_out;    // DDR SDRAM I/F Data strobe output 



endmodule


