library verilog;
use verilog.vl_types.all;
entity syn3ram is
    generic(
        init_value      : integer := 0;
        disabled_gsr    : integer := 0
    );
    port(
        di3             : in     vl_logic;
        di2             : in     vl_logic;
        di1             : in     vl_logic;
        di0             : in     vl_logic;
        wad4            : in     vl_logic;
        wad3            : in     vl_logic;
        wad2            : in     vl_logic;
        wad1            : in     vl_logic;
        wad0            : in     vl_logic;
        wren            : in     vl_logic;
        wpe0            : in     vl_logic;
        wpe1            : in     vl_logic;
        ck              : in     vl_logic;
        gsr             : in     vl_logic;
        pur             : in     vl_logic;
        rad4            : in     vl_logic;
        rad3            : in     vl_logic;
        rad2            : in     vl_logic;
        rad1            : in     vl_logic;
        rad0            : in     vl_logic;
        do3             : out    vl_logic;
        do2             : out    vl_logic;
        do1             : out    vl_logic;
        do0             : out    vl_logic;
        qdo3            : out    vl_logic;
        qdo2            : out    vl_logic;
        qdo1            : out    vl_logic;
        qdo0            : out    vl_logic
    );
end syn3ram;
