///////////////////////////////////////////////////////////////////////
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ====================================================================
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
//
// This confidential and proprietary software may be used only as
// authorised by a licensing agreement from Lattice Semiconductor 
// Corporation.
// The entire notice above must be reproduced on all authorized
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// by a licensing agreement from Lattice Semiconductor Corporation.
//
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//
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// web: http://www.latticesemi.com/
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// ====================================================================
//
// File Details 	
// ====================================================================
// Project		: 	DDR SDRAM Controller
// File			: 	ddr_top_tb.v
// Title		: 	ddr_top_tb
// Dependencies		: 	
// 
// Description		: This module is the top test becnch for the 
//                        customer to use the test vectors. Instantiates
//                        DDR controller.
// Notes		: 
// 
//
// Additional info.	:
//
//
// ====================================================================
//

`timescale 1 ps / 1 ps
module	ddr_top_tb(
	);

// ====================================================================
// Register all outputs
// ====================================================================      
// -- NA -- //
reg				clk;

// ====================================================================
// Internal signals
// ====================================================================
wire				reset_n;   
wire	[2:0]			cmd;				// Generic I/F Command for controller
wire	[`DSIZE/8-1:0]		dmsel;				// Generic I/F Data mask select inputs
wire	[`ASIZE-1:0]		addr;				// Generic I/F Address bus
wire	[`DSIZE-1:0]		datain;				// Generic I/F Data input bus

wire	[`DSIZE-1:0]		dataout;			// Generic I/F Data output bus
wire    [`RANK-1:0]		ddr_cs_n;			// DDR SDRAM chip select
wire	[`RSIZE-1:0]		ddr_ad;				// DDR SDRAM I/F Address bus
wire	[`BSIZE-1:0]		ddr_ba;				// DDR SDRAM I/F Bank bus
wire	[`DSIZE/16-1:0]		ddr_dqm;			// DDR SDRAM I/F Data mask lines
tri0	[`DSIZE/2-1:0]		ddr_dq;				// DDR SDRAM I/F Data bus output 
wire	[`DSIZE/16-1:0]		ddr_dqs;			// DDR SDRAM I/F Data strobe output 

// ====================================================================
// Instantiate the sub blocks  of the top level 
// ====================================================================

// ====================================================================
// DDR SDRAM Controller Top  
// ====================================================================
ddr_top U1_ddr_top(
        //-------INPUTS
	.clk(clk),		 		// System clock
	.reset_n(reset_n),			// Generic I/F Active low system reset
	.cmd(cmd),				// Generic I/F Command for controller
	.dmsel(dmsel),				// Generic I/F Data mask inputs
	.addr(addr),				// Generic I/F Address bus
	.datain(datain),			// Generic I/F Data input bus

	//-------OUTPUTS
	.dataout(dataout),			// Generic I/F Data output bus
	.dataout_valid(dataout_valid),		// Generic I/F indicates Dataout bus has a valid data
 	.datain_valid(datain_valid),		// Generic I/F indicates controller has accepted a data from Datain bus 
	.busy(busy),				// Generic I/F Busy signal 
	.ddr_clk(ddr_clk),			// DDR SDRAM Clock
	.ddr_clk_n(ddr_clk_n),			// DDR SDRAM Inverted Clock
	.ddr_cke(ddr_cke),			// DDR SDRAM I/F Clock enable
	.ddr_cs_n(ddr_cs_n),			// DDR SDRAM I/F Chip select
	.ddr_we_n(ddr_we_n),			// DDR SDRAM I/F Write enable
	.ddr_cas_n(ddr_cas_n),			// DDR SDRAM I/F Column address strobe
	.ddr_ras_n(ddr_ras_n),			// DDR SDRAM I/F Row address strobe
	.ddr_ad(ddr_ad),			// DDR SDRAM I/F Address bus
	.ddr_ba(ddr_ba),			// DDR SDRAM I/F Bank bus
	.ddr_dqm(ddr_dqm),			// DDR SDRAM I/F Data mask lines
	.ddr_dq(ddr_dq),			// DDR SDRAM I/F Data bus output 
	.ddr_dqs(ddr_dqs)			// DDR SDRAM I/F Data strobe output 
	);


// ====================================================================
// Testbench clock generator  
// ====================================================================
reg clk1;
reg clk2;
reg clk3;

initial begin 
  clk1   <= 1;
end
// generate a 3.8 ns Clock Period (131MHz)
// Delaying the clk by (clk-1ns) to avoid assigning & capturing on the same clk 
always  #3800 clk1 <= ~clk1;
always  @ (clk1) #3700 clk2 = clk1;
always  @ (clk2) #3700 clk3 = clk2;
always  @ (clk3) #100 clk = clk3;

// STIMULI Declaration


`define INPUTS        {reset_n, cmd,  dmsel,       addr,    datain,  ddr_dq}
`define INPUTS_WIDTH  (1        + 3   +(`DSIZE/8)  +`ASIZE  +`DSIZE  +(`DSIZE/2))
   
reg [`INPUTS_WIDTH -1: 0] stimuli;

assign  `INPUTS = stimuli;

// Include tests
initial begin
`include "stimuli_basicrw_cmd.v"
 #50 $finish;
end


endmodule


