library verilog;
use verilog.vl_types.all;
entity orca_dpram32x12 is
    port(
        waddr           : in     vl_logic_vector(4 downto 0);
        datain          : in     vl_logic_vector(11 downto 0);
        clk             : in     vl_logic;
        wren            : in     vl_logic;
        raddr           : in     vl_logic_vector(4 downto 0);
        dataout         : out    vl_logic_vector(11 downto 0)
    );
end orca_dpram32x12;
