library verilog;
use verilog.vl_types.all;
entity ddr_dbgen is
    port(
        reset_n         : in     vl_logic;
        clk             : in     vl_logic;
        clk2x           : in     vl_logic;
        write_enable    : in     vl_logic;
        dqsoe_reg       : out    vl_logic;
        dqsout_en       : out    vl_logic
    );
end ddr_dbgen;
