library verilog;
use verilog.vl_types.all;
entity ddr_msm is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        msm_cmd_v       : in     vl_logic;
        msm_cmdin       : in     vl_logic_vector(1 downto 0);
        emr_for_msm     : in     vl_logic;
        twr_wait        : in     vl_logic;
        tras_wait       : in     vl_logic;
        trc_wait        : in     vl_logic;
        count_trfc      : in     vl_logic_vector(3 downto 0);
        count_tmrd      : in     vl_logic_vector(2 downto 0);
        count_trp       : in     vl_logic_vector(2 downto 0);
        ref_req_del     : in     vl_logic;
        datapath_wait   : in     vl_logic;
        exe_state_idle1 : in     vl_logic;
        exe_state_idle2 : in     vl_logic;
        msm_cmd_applied_for_cs: out    vl_logic;
        msm_cmd_applied : out    vl_logic;
        msm_pre_applied : out    vl_logic;
        msm_loadmr_applied: out    vl_logic;
        msm_loademr_applied: out    vl_logic;
        msm_pdown_applied: out    vl_logic;
        msm_selfref_applied: out    vl_logic;
        msm_ref_applied : out    vl_logic;
        msm_ref_applied_fortimer: out    vl_logic;
        msm_ras         : out    vl_logic;
        msm_cas         : out    vl_logic;
        msm_we          : out    vl_logic
    );
end ddr_msm;
