library verilog;
use verilog.vl_types.all;
entity ddr_cmd_exe is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        cmd             : in     vl_logic_vector(2 downto 0);
        addr            : in     vl_logic_vector(26 downto 0);
        start_init      : in     vl_logic;
        count_cl        : in     vl_logic_vector(1 downto 0);
        count_bl        : in     vl_logic_vector(1 downto 0);
        count_trcd      : in     vl_logic_vector(2 downto 0);
        count_trfc      : in     vl_logic_vector(3 downto 0);
        count_trp       : in     vl_logic_vector(2 downto 0);
        count_tmrd      : in     vl_logic_vector(2 downto 0);
        count_trrd      : in     vl_logic_vector(2 downto 0);
        count_twr       : in     vl_logic_vector(2 downto 0);
        count_tras      : in     vl_logic_vector(3 downto 0);
        count_twtr      : in     vl_logic_vector(2 downto 0);
        count_trc       : in     vl_logic_vector(3 downto 0);
        cfg0_reg        : in     vl_logic_vector(6 downto 0);
        cfg2_reg        : in     vl_logic_vector(15 downto 0);
        init_done       : in     vl_logic;
        ism_state_0     : in     vl_logic_vector(3 downto 0);
        ism_state_1     : in     vl_logic_vector(3 downto 0);
        dataout_valid   : out    vl_logic;
        datain_valid    : out    vl_logic;
        busy            : out    vl_logic;
        busy_rep        : out    vl_logic;
        ddr_cke         : out    vl_logic;
        ddr_cs_n        : out    vl_logic_vector(7 downto 0);
        ddr_we_n        : out    vl_logic;
        ddr_cas_n       : out    vl_logic;
        ddr_ras_n       : out    vl_logic;
        ddr_ad          : out    vl_logic_vector(11 downto 0);
        ddr_ba          : out    vl_logic_vector(1 downto 0);
        write_enable    : out    vl_logic;
        update_cfg0     : out    vl_logic;
        cfg0_data       : out    vl_logic_vector(6 downto 0)
    );
end ddr_cmd_exe;
