// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================
//                         FILE DETAILS         
// Project          : DDR Controller 
// File             : ddr_ddefines.v
// Title            : ddr_ddefines
// Dependencies     : ddr_ddefines.v
// Description      : This module contains all the parameters used in the 
// DDR Controller design
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : Apr 03, 2001
// Changes Made     : Initial Creation
//
// =============================================================================
// ====================================================================
// START design configurable parameters 
// ====================================================================

//===================================================================== 
// User commands applied on the generic bus i/f thru cmd[3:0]
//===================================================================== 

`define USR_NOP                 3'h0            // User command Nop
`define USR_READ                3'h1            // User command Read
`define USR_WRITE               3'h2            // User command Write
`define USR_LOADCFG             3'h3            // User command Load Configuration Reg
`define USR_LOADMR              3'h4            // User command Load Mode Reg
`define USR_POWERDWN            3'h5            // User command Power Down
`define USR_SELFREFRESH         3'h6            // User command Selfrefresh

`define REFRESH                 3'h7            // Internal Refresh request command
                                                // NOT FOR THE USER
//=====================================================================
// FOR MSM state machine
//=====================================================================
`define INT_LOADMR              2'h0            // For Internal use
`define INT_POWERDWN            2'h1            // For Internal use
`define INT_SELFREFRESH         2'h2            // For Internal use
`define INT_REFRESH             2'h3            // For Internal use

// ====================================================================
// "ddr_cmdexeng.v" block Parameters
// ====================================================================

// Legal allowed RANKS are 1,2,4 or 8
// if RANK_SIZE_ZERO  RANK = 1 define RANK_SIZE = 0 
// if RANK_SIZE_ONE   RANK = 2 define RANK_SIZE = 1 
// if RANK_SIZE_TWO   RANK = 4 define RANK_SIZE = 2 
// if RANK_SIZE_THREE RANK = 8 define RANK_SIZE = 3 

`ifdef RANK_SIZE_ZERO
	`define RANK			1
	`define RANK_SIZE		0
`else
	`ifdef RANK_SIZE_ONE
		`define RANK		2
		`define RANK_SIZE	1
	`endif	
	`ifdef RANK_SIZE_TWO
		`define RANK		4
		`define RANK_SIZE	2
	`endif	
	`ifdef RANK_SIZE_THREE
		`define RANK		8
		`define RANK_SIZE	3
	`endif	
`endif


// DSIZE Definition based on the user requirements
`ifdef DATA_SIZE_32
	`define DSIZE			32
`else
	`ifdef DATA_SIZE_64
		`define DSIZE		64
	`endif	
	`ifdef DATA_SIZE_128
		`define DSIZE		128
	`endif	
`endif

	
//
// Address size on Generic Bus interface . ASIZE = RANK_SIZE+RSIZE+BSIZE+CSIZE
//
`define ASIZE 			`RANK_SIZE + `RSIZE + `BSIZE + `CSIZE         		      	

//
// Controller state machine STATES
//

//
// Command execution state machine
//
`define EXE_STATES_WIDTH     4

`define EXE_IDLE             4'd0
`define EXE_ACT              4'd1
`define EXE_PRE              4'd2
`define EXE_CMD              4'd3
`define EXE_S_DB             4'd4
`define EXE_S_SBDR           4'd5
`define EXE_S_SBSR           4'd6
`define EXE_M_WAIT           4'd7
`define EXE_NEW1             4'd8
`define EXE_NEW2             4'd9

`define MSM_IDLE             3'd0
`define MSM_PRE              3'd1
`define MSM_MR               3'd2
`define MSM_AR               3'd7
`define MSM_SELFREF          3'd3
`define MSM_PDOWN            3'd4
`define MSM_AUTOUP           3'd5
`define MSM_STAY             3'd6

// ====================================================================
// "ddr_initctrl.v" block Parameters
// ====================================================================

`define COUNT_LOCKDLL    	8'b11001000	//DLL Lock period ( DLL Lock period - tMRD-tRP- 2*tRFC) ~= 200 Clocks 

//
// Initialization state machine STATES
//

`define ISM_SIZE		4		// Width of the ism_state register
	   
`define ISM_IDLE		4'd0  //18'h 0_0001 	// Idle state
`define ISM_NOP			4'd1  //18'h 0_0002	// Nop state
`define ISM_PREALL		4'd2  //18'h 0_0004	// Precharge all banks state
`define ISM_TRP_WAIT		4'd3  //18'h 0_0008   	// tRP wait state
`define ISM_EMRS		4'd4  //18'h 0_0010   	// Extended mode register state
`define ISM_TMRD_WAIT		4'd5  //18'h 0_0020   	// tMRD wait state
`define ISM_MRS			4'd6  //18'h 0_0040   	// Mode register set
`define ISM_TMRD1_WAIT		4'd7  //18'h 0_0080   	// tMRD wait state
`define ISM_END_0		4'd8  //18'h 0_0080   	// END state
	   			
`define ISM_SIZE_1		4		// Width of the ism_state register

`define ISM_WAIT		4'd0  //18'h 0_0100   	// Wait for SM0 to complete 
`define ISM_PREALL1		4'd1  //18'h 0_0100   	// Precharge all banks state 
`define ISM_TRP1_WAIT		4'd2  //18'h 0_0200   	// tRP wait state
`define ISM_AR1			4'd3  //18'h 0_0400	// Autorefresh state
`define ISM_TRFC1_WAIT		4'd4  //18'h 0_0800	// tRFC wait state
`define ISM_AR2			4'd5  //18'h 0_1000	// Autorefresh state
`define ISM_TRFC2_WAIT		4'd6  //18'h 0_2000	// tRFC wait state
`define ISM_MRS1		4'd7  //18'h 0_4000	// Mode register state
`define ISM_TMRD2_WAIT		4'd8  //18'h 0_8000	// tMRD wait state
`define ISM_LOCKDLL		4'd9  //18'h 1_0000	// Lock dll wait state
`define ISM_READY		4'd10 //18'h 2_0000	// Ready state	   

// ====================================================================
// "ddr_genericif.v" block Parameters
// ====================================================================
`define CFG0    		2'b00		// CFG0 Address
`define CFG1    		2'b01		// CFG1 Address
`define CFG2    		2'b10		// CFG2 Address
`define CFG3    		2'b11		// CFG3 Address

`define CL_1_5  		3'b101		// CAS Latency 1.5
`define CL_2_0  		3'b010		// CAS Latency 2.0
`define CL_2_5  		3'b110		// CAS Latency 2.5
`define CL_3_0  		3'b011		// CAS Latency 3.0

`define BL2    			3'b001		// Burst Length 2 
`define BL4    			3'b010		// Burst Length 4
`define BL8 	   		3'b011		// Burst Length 8

`ifdef BL_TWO
	`define 	BL	3'b001
`else
	`ifdef	BL_FOUR
		`define	BL	3'b010
	`endif
	`ifdef	BL_EIGHT
		`define	BL	3'b011
	`endif
`endif

`ifdef CL_15
	`define 	CL	3'b101
`else
	`ifdef	CL_20
		`define	CL	3'b010
	`endif
	`ifdef	CL_25
		`define	CL	3'b110
	`endif
	`ifdef	CL_30
		`define	CL	3'b011
	`endif
`endif

// ====================================================================
// `DEFINES used by all  blocks
// ====================================================================
`define	L			1'b0
`define	H			1'b1

// DSIZE Definition based on the user requirements
`ifdef DATA_SIZE_32
	`define DSIZE2		16		// `DSIZE /2	
	`define DSIZE8		4		// `DSIZE /8
	`define DSIZE16		2		// `DSIZE /16
`else
	`ifdef DATA_SIZE_64
		`define DSIZE2	32		// `DSIZE /2	
		`define DSIZE8	8		// `DSIZE /8		
		`define DSIZE16	4		// `DSIZE /16	
	`endif	
	`ifdef DATA_SIZE_128
		`define DSIZE2	64		// `DSIZE /2	
		`define DSIZE8	16		// `DSIZE /8	
		`define DSIZE16	8		// `DSIZE /16
	`endif	
`endif

`define	ZEROS_DSIZE		`DSIZE'b0
`define	ZEROS_DSIZE2		`DSIZE2'b0
`define	ZEROS_DSIZE8		`DSIZE8'b0
`define	ZEROS_DSIZE16		`DSIZE16'b0
`define	ZEROS_ASIZE		`ASIZE'b0




// ====================================================================
// Enable or Disable testbench display of debug commands 
// to enable display set DEBUG to 1 and to disable display set DEBUG to 0
// ====================================================================
`define DEBUG		0	

// Comment the following if dumping of signals is not required
`define DUMP_SIGS	0	


//----------------------------------------------------------------------
// Following definations select the memory model being hooked up to the testbench
// Uncomment one of the following 
//----------------------------------------------------------------------
//  Uses a 128M Microm memory model with 16M x 8bit configuration RSIZE = 12 CSIZE = 10 DSIZE can be 32/64/128
//`define MEM_MICRON_46V16M8

//  Uses a 256 Samsung memory model with 64M x 4bit configuration RSIZE = 12 CSIZE = 11 DSIZE can only be 32
// `define MEM_SAMSUNG_64M4

// Define Samsung memory model parameters
//`ifdef MEM_SAMSUNG_64M4
//	`define M256	// 256 M memory size
//	`define SZ	// CL = 2
//	`define X4	// Data bus width = 4
//`endif


// ================================END=================================







