# Readme

# General Information

## Copyright Notice

Copyright 2000-2004 © Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.

# Contacting Lattice

Mail: | Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 U.S.A.
Telephone: | 1-800-Lattice (USA and Canada)
| 1-408-826-6000 (other locations)
Website: | http://www.latticesemi.com
E-mail: | techsupport@latticesemi.com

# IP Module Information

## About this Module

IP Name: | DDR SDRAM Controller Generic I/F (non-pipelined version)
IP Version: | ver1
IP Configuration Release Date: | January 2004
Configuration Description: | Configuration 8, 64-bit datawidth
Target Technology: | ORCA 4

## Software Requirements

Synthesis Tools Supported: | Synplify 7.3.3 version
| LeonardoSpectrum 2003b.35_OEM_Lattice version
Simulation Tools Supported: | ModelSim SE PLUS 5.6f and higher
Lattice Tool Supported: | ispLEVER 3.1 SP1 and higher

# ispLeverCORE IP Evaluation Tutorials

ispLeverCORE™ Evaluation Tutorials can be accessed on the Lattice website:

These tutorials show how to evaluate ispLeverCORE IP products using the ispLEVER software tools.

## Interactive Quick-Start Tutorial

An interactive HTML-based tutorial is available for this ispLeverCORE IP module. It links to the IP core's ReadMe file to provide a one-stop reference to all of the core's usage documentation.

To install the Interactive Quick-Start Tutorial:

1. Download and install an ispLeverCORE IP Evaluation Package onto your computer.

2. Download the Interactive Quick-Start Tutorial (ispLeverCORE tutorial.zip) from the Lattice website:

http://www.latticesemi.com/products/devtools/ip/eval_tutorial.cfm

3. Extract the contents of ispLeverCORE tutorial.zip into the /tutorial directory inside the installed ispLeverCORE IP core.

4. Run the ispLeverCORE IP Evaluation Tutorial. Click on this link and the Tutorial will be connected to the core's ReadMe.

# Installation Information

All Lattice IP Cores are available in the ZIP file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files.

## Files for Synthesis

A set of HDL files (Verilog) are provided for synthesis. These design files are provided such that this IP Core can be evaluated as a stand-alone device or as part of an application specific design. The files are located in: ddrct_np_o4_1_008/orca4/ver1/source.

· ddr_top.v - The top-level source file is divided into two sections. The I/O section and the Core section. The I/O section includes all I/O components (inferred during synthesis or instantiated technology elements). The Core section instantiates the Core as a black box within the design. The top-level source file can be used as the platform for an application specific design that includes/integrates this IP Core. Additional modules can simply be instantiated in the source file to implement the application specific design.

· ddrct_np_o4_1_008_params.v - The ddrct_np_o4_1_008_params.v contains parameters used to specify the configuration of this IP Core. This file must be compiled along with the top-level source file during synthesis.

NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP CORE MAY NOT RUN AT SPECIFICATION.

· ddr_ddefines.v – This file contains definitions used to specify the configuration of this IP Core. This file must be compiled along with the top-level source file during synthesis.

· ddrct_np_o4_1_008.v - This file contains the synthesis directives that allow the Core section to be treated as a "black box" during synthesis in Synplicity's Synplify and Leonardo Spectrum. This file represents the top-level of the Core Section.

· ddr_pll_orca.v - This file contains the instantiation of PLL. This file is present only if PLL is required by the IP core.

· hppll.v, bmz12.v – These file is needed when running synthesis using stand-alone LeonardoSpectrum for ORCA. These file contains the synthesis models for ORCA technology elements.

· ddr_top.sdc – This constraint file is required only when running synthesis using Synplify.

· orca4_synplify.v - This file is needed when running synthesis using stand alone Synplify for ORCA. This file contains the synthesis models for ORCA technology elements.

· edifmod.pl - This script file is needed to generate final EDIF netlist. This file inserts the IO types to the instances of the ports of EDIF netlist generated from LeonardoSpectrum synthesis tool.

# Information for Running Synthesis Using Synplify

## Adding Design Files

After Synplify is running, add these files in the following order:

~/source/ddrct_np_o4_1_008_params.v

~source/ddr_ddefines.v

~/source/orca4_synplify.v

~/source/ddr_pll_orca.v

~/source/ddrct_np_o4_1_008.v

~/source/ddr_top.v

~/source/ddr_top.sdc

## Setting Implementation Options

In the Options for Implementation dialog box, do the following:

· On the Device tab, select an Orca Series 4 Technology, 4E02 Part, -3 Speed Grade, and BM416 package.

· On the Device tab under Device Mapping Options, set Fanout Guide = 100

· On the Options tab, select FSM Compiler and Resource Sharing

· On the Constraints tab, set Frequency = 0.

# Information for Running Synthesis Using LeonardoSpectrum

## Adding Design Files

Open the specified files in the following order:

~/source/ddrct_np_o4_1_008_params.v

~/source/ddr_ddefines.v

~/source/hppll.v

~/source/bmz12.v

~/source/ddr_pll_orca.v

~/source/ddrct_np_o4_1_008.v

~/source/ddr_top.v

~/source/ddr_top.ctr

## Setting Implementation Options

Using the Quick Setup tab, do the following:

· Select the OR4E021BM416-DB Speed Grade 3 device.

· Under Constraints, set Clock Frequency = 0

## Steps of generating new EDIF netlist

1. Copy edifmod.pl file from source directory into the EDIF generated directory.
2. Open DOS shell and change the directory to the EDIF generated directory.
3. Type: perl edifmod.pl <EDIF netlist>
4. New EDIF netlist is generated with original EDIF name and the original EDIF file will be saved as <edifname>.edf.old

Note: user needs to have the Perl software installed before running step 3. To download the Perl software, please visit www.activeperl.com to download the latest version.

# Implementing the IP Module Using ispLEVER

## Setting the Target Device

In the Device Selector Dialog box, do the following:

· Family = or4e00

· Device = or4e02

· Speed Grade = -3

· Package Type = BM416

## Copying the Evaluation Files

Copy these evaluation database and constraint files:

· ~\par\ddrct_np_o4_1_008.ngo

· ~\par\ddrct_np_o4_1_008_synplify.prf (For Synplicity)

· ~\par\post_route_trace_synplify.prf (For Synplicity)

· ~\par\ddrct_np_o4_1_008_leonardo.prf (For LeonardoSpectrum)

· ~\par\post_route_trace_leonardo.prf (For LeonardoSpectrum)

· The top-level EDIF netlist generated from running synthesis

## Setting ORCA Place and Route Options

Choose Tools >Timing Checkpoint Options and select Continue for both Checkpoint Options

Set the Map Design properties:

Pack Logic BLock Util: 97

Leave all other options at Default.

Set the Place & Route Design properties:

Placement Effort Level: 5

Routing Passes: 10

Placement Iterations: 1

Placement Iteration Start Point: 88 (Synplify)

Placement Iteration Start Point: 39 (Exemplar)

Placement Save Best Run: 30

Routing Resource Optimization: 1

Routing Delay Reduction Passes: 7

## Generating Timing Report file

When the timing report is opened, it is possible that timing violations may be viewed due to over-constrainment of the design to achieve better performance results. To obtain a correct timing report, please do the following:

§ Place the corresponding post_route_trace.prf file for either Synplify or LeonardoSpectrum into your project directory depending on the synthesis tool used.

§ Open a DOS-shell and navigate to the Place & Route working directory.

§ For synplify flow type: trce (your project_name).ncd post_route_trace_synplify.prf -o post_route_trace.twr

§ For Exemplar flow type: trce (your project_name).ncd post_route_trace_exemplar.prf -o post_route_trace.twr

A new timing report is generated as post_route_trace.twr