library verilog;
use verilog.vl_types.all;
entity mt46v16m8 is
    generic(
        addr_bits       : integer := 12;
        data_bits       : integer := 8;
        col_bits        : integer := 10;
        mem_sizes       : integer := 4194303;
        tck             : real    := 7.500000;
        tmrd            : real    := 15.000000;
        tras            : real    := 40.000000;
        trc             : real    := 65.000000;
        trfc            : real    := 75.000000;
        trcd            : real    := 19.900000;
        trp             : real    := 20.000000;
        trrd            : real    := 15.000000;
        twr             : real    := 15.000000
    );
    port(
        dq              : inout  vl_logic_vector;
        dqs             : inout  vl_logic;
        addr            : in     vl_logic_vector;
        ba              : in     vl_logic_vector(1 downto 0);
        clk             : in     vl_logic;
        clk_n           : in     vl_logic;
        cke             : in     vl_logic;
        cs_n            : in     vl_logic;
        ras_n           : in     vl_logic;
        cas_n           : in     vl_logic;
        we_n            : in     vl_logic;
        dm              : in     vl_logic
    );
end mt46v16m8;
