library verilog;
use verilog.vl_types.all;
entity fd1p3dx is
    generic(
        disabled_gsr    : integer := 0
    );
    port(
        d               : in     vl_logic;
        sp              : in     vl_logic;
        ck              : in     vl_logic;
        cd              : in     vl_logic;
        q               : out    vl_logic;
        qn              : out    vl_logic
    );
end fd1p3dx;
