library verilog;
use verilog.vl_types.all;
entity ddr_bank_row is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        wren            : in     vl_logic;
        wraddr          : in     vl_logic_vector(4 downto 0);
        rdaddr          : in     vl_logic_vector(4 downto 0);
        rows_in         : in     vl_logic_vector(11 downto 0);
        rows_out        : out    vl_logic_vector(11 downto 0);
        banks_in        : in     vl_logic_vector(31 downto 0);
        banks_out       : out    vl_logic
    );
end ddr_bank_row;
