library verilog;
use verilog.vl_types.all;
entity ddrct_np_o4_1_008 is
    port(
        clk             : in     vl_logic;
        clk2x           : in     vl_logic;
        reset_n         : in     vl_logic;
        cmd             : in     vl_logic_vector(2 downto 0);
        dmsel           : in     vl_logic_vector(7 downto 0);
        addr            : in     vl_logic_vector(26 downto 0);
        datain          : in     vl_logic_vector(63 downto 0);
        ddr_dq_in       : in     vl_logic_vector(31 downto 0);
        dataout         : out    vl_logic_vector(63 downto 0);
        dataout_valid   : out    vl_logic;
        datain_valid    : out    vl_logic;
        busy            : out    vl_logic;
        ddr_cke         : out    vl_logic;
        ddr_cs_n        : out    vl_logic_vector(7 downto 0);
        ddr_we_n        : out    vl_logic;
        ddr_cas_n       : out    vl_logic;
        ddr_ras_n       : out    vl_logic;
        ddr_ad          : out    vl_logic_vector(11 downto 0);
        ddr_ba          : out    vl_logic_vector(1 downto 0);
        ddr_dqoe        : out    vl_logic_vector(31 downto 0);
        ddr_dq_out      : out    vl_logic_vector(31 downto 0);
        ddr_dqm         : out    vl_logic_vector(3 downto 0);
        ddr_dqsoe       : out    vl_logic_vector(3 downto 0);
        ddr_dqs_out     : out    vl_logic_vector(3 downto 0)
    );
end ddrct_np_o4_1_008;
