/* Verilog netlist generated by SCUBA ORCA Foundry 2001 Production (9.7.6) */
/* C:\Program Files\ORCA\bin\nt\scuba -w -lang verilog -n ddr_pll_orca -bus_exp 1 -bb -type pll -arch orca4 -fin 100. -mfreq 100. -nfreq 200. -pllmode delay -tap 0  */
/* Wed Apr 17 16:05:23 2002 */

`timescale 1 ns / 100 ps
module ddr_pll_orca (clk, mclk, nclk, fb, intfb, lock);
    input clk;
    input fb;
    input intfb;
    output mclk;
    output nclk;
    output lock;

    wire nclk_t;
    wire mclk_t;

    defparam ddr_pll_orca_0_0.VCOTAP = 0;
    defparam ddr_pll_orca_0_0.NCLKMODE = "DELAY";
    defparam ddr_pll_orca_0_0.MCLKMODE = "DELAY";
    defparam ddr_pll_orca_0_0.DIV3 = 1;
    defparam ddr_pll_orca_0_0.DIV2 = 2;
    defparam ddr_pll_orca_0_0.DIV1 = 2;
    defparam ddr_pll_orca_0_0.DIV0 = 1;
    HPPLL ddr_pll_orca_0_0 (.CLKIN(clk), .FB(fb), .MCLK(mclk_t), .NCLK(nclk_t), 
        .LOCK(lock), .INTFB());

    assign nclk = nclk_t;
    assign mclk = mclk_t;

endmodule
