// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================
//                         FILE DETAILS         
// Project          : DDR Controller 
// File             : ddr_top.v
// Title            : ddr_top
// Dependencies     : ddr_params.v
// Description      : This module contains the top most level of the DDR SDRAM 
// Controller which contains the "ddrct_np_o4_1_008" block the PLL and the  I/O pads.
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : Apr 03, 2001
// Changes Made     : Initial Creation
//
// =============================================================================

`timescale 100ps / 10ps

module  ddr_top(
        //-------INPUTS
        clk,                            // System clock
        reset_n,                        // Generic I/F Active low system reset
        cmd,                            // Generic I/F Command for controller
        dmsel,                          // Generic I/F Data mask inputs
        addr,                           // Generic I/F Address bus
        datain,                         // Generic I/F Data input bus

        //-------OUTPUTS
        dataout,                        // Generic I/F Data output bus
        dataout_valid,                  // Generic I/F indicates Dataout bus has a valid data
        datain_valid,                   // Generic I/F indicates controller has accepted a data from Datain bus 
        busy,                           // Generic I/F Busy signal 
        ddr_clk,                        // DDR SDRAM clock
        ddr_clk_n,                      // DDR SDRAM Inverted clock 
        ddr_cke,                        // DDR SDRAM I/F Clock enable
        ddr_cs_n,                       // DDR SDRAM I/F Chip select
        ddr_we_n,                       // DDR SDRAM I/F Write enable
        ddr_cas_n,                      // DDR SDRAM I/F Column address strobe
        ddr_ras_n,                      // DDR SDRAM I/F Row address strobe
        ddr_ad,                         // DDR SDRAM I/F Address bus
        ddr_ba,                         // DDR SDRAM I/F Bank bus
        ddr_dqm,                        // DDR SDRAM I/F Data mask lines
        ddr_dq,                         // DDR SDRAM I/F Data bus output 
        ddr_dqs                         // DDR SDRAM I/F Data strobe output 
        )/* synthesis syn_props=""IP_Version = Ver1_0"" */
         /* exemplar attribute ddr_top IP_Version Ver1_0 */;

// ====================================================================
// Define all inputs / outputs
// ====================================================================
//--------Inputs
input                           clk;            // System clock
input                           reset_n;        // Generic I/F Active low system reset
input   [2:0]                   cmd;            // Generic I/F Command for controller
input   [`DSIZE/8-1:0]          dmsel;          // Generic I/F Data mask select inputs
input   [`ASIZE-1:0]            addr;           // Generic I/F Address bus
input   [`DSIZE-1:0]            datain;         // Generic I/F Data input bus

        
//-------OUTPUTS
output                          ddr_clk;        // DDR SDRAM clock
output                          ddr_clk_n;      // DDR SDRAM Inverted clock 
output  [`DSIZE-1:0]            dataout;        // Generic I/F Data output bus
output                          dataout_valid;  // Generic I/F indicates Dataout bus has a valid data
output                          datain_valid;   // Generic I/F indicates controller has accepted a data from Datain bus 
output                          busy;           // Generic I/F Busy signal 
output                          ddr_cke;        // DDR SDRAM I/F Clock enable
output  [`RANK-1:0]             ddr_cs_n;       // DDR SDRAM I/F Chip select
output                          ddr_we_n;       // DDR SDRAM I/F Write enable
output                          ddr_cas_n;      // DDR SDRAM I/F Column address strobe
output                          ddr_ras_n;      // DDR SDRAM I/F Row address strobe
output  [`RSIZE-1:0]            ddr_ad;         // DDR SDRAM I/F Address bus
output  [`BSIZE-1:0]            ddr_ba;         // DDR SDRAM I/F Bank bus
output  [`DSIZE/16-1:0]         ddr_dqm;        // DDR SDRAM I/F Data mask lines
inout   [`DSIZE/2-1:0]          ddr_dq;         // DDR SDRAM I/F Data bus output 
//inout   [`DSIZE/16-1:0]         ddr_dqs;        // DDR SDRAM I/F Data strobe output 
output   [`DSIZE/16-1:0]         ddr_dqs;        // DDR SDRAM I/F Data strobe output 

// ====================================================================
// Internal signals
// ====================================================================
wire    [`DSIZE/2-1:0]          ddr_dq_in;      // DDR SDRAM I/F Data bus Input 
wire    [`DSIZE/2-1:0]          ddr_dq_out;     // DDR SDRAM I/F Data bus output
wire    [`DSIZE/16-1:0]         ddr_dqs_out;    // DDR SDRAM I/F Data bus strobe output 
wire    [`DSIZE-1:0]            dataout;        // Generic I/F Data output bus
wire    [`RSIZE-1:0]            sig_ddr_ad;     // DDR SDRAM I/F Address bus
wire    [`BSIZE-1:0]            sig_ddr_ba;     // DDR SDRAM I/F Bank bus
wire    [`DSIZE/16-1:0]         sig_ddr_dqm;    // DDR SDRAM I/F Data mask lines
wire                            sig_ddr_cke;    // DDR SDRAM I/F Clock enable
wire    [`RANK-1:0]             sig_ddr_cs_n;   // DDR SDRAM I/F Chip select
wire                            sig_ddr_we_n;   // DDR SDRAM I/F Write enable
wire                            sig_ddr_cas_n;  // DDR SDRAM I/F Column address strobe
wire                            sig_ddr_ras_n;  // DDR SDRAM I/F Row address strobe
wire                            pll_clk, pll_clk2x;
wire                            pll_mclk, pll_nclk;
wire    [`DSIZE/2-1:0]          ddr_dqoe;  
wire    [`DSIZE/16-1:0]         ddr_dqsoe;  
reg     [`DSIZE/2-1:0]          ddr_dq_i;       // DDR SDRAM I/F Data bus output 
reg     [`DSIZE/16-1:0]         ddr_dqs_i;      // DDR SDRAM I/F Data strobe output 

integer                         i,j;

// ====================================================================
// Instantiate the sub blocks  of the top level 
// ====================================================================

// ====================================================================
// DDR SDRAM Controller  
// ====================================================================
ddrct_np_o4_1_008 U1_ddrct_np_o4_1_008(
        //-------INPUTS
        .clk(pll_clk),                  // System clock
        .clk2x(pll_clk2x),              // 2x clock 
        .reset_n(reset_n),              // Generic I/F Active low system reset
        .cmd(cmd),                      // Generic I/F Command for controller
        .dmsel(dmsel),                  // Generic I/F Data mask inputs
        .addr(addr),                    // Generic I/F Address bus
        .datain(datain),                // Generic I/F Data input bus
        .ddr_dq_in(ddr_dq_in),          // DDR SDRAM I/F Data bus input 

        //-------OUTPUTS
        .dataout(dataout),              // Generic I/F Data output bus
        .dataout_valid(dataout_valid),  // Generic I/F indicates Dataout bus has a valid data
        .datain_valid(datain_valid),    // Generic I/F indicates controller has accepted a data from Datain bus 
        .busy(busy),                    // Generic I/F Busy signal 
        .ddr_cke(sig_ddr_cke),          // DDR SDRAM I/F Clock enable
        .ddr_cs_n(sig_ddr_cs_n),        // DDR SDRAM I/F Chip select
        .ddr_we_n(sig_ddr_we_n),        // DDR SDRAM I/F Write enable
        .ddr_cas_n(sig_ddr_cas_n),      // DDR SDRAM I/F Column address strobe
        .ddr_ras_n(sig_ddr_ras_n),      // DDR SDRAM I/F Row address strobe
        .ddr_ad(sig_ddr_ad),            // DDR SDRAM I/F Address bus
        .ddr_ba(sig_ddr_ba),            // DDR SDRAM I/F Bank bus
        .ddr_dqoe(ddr_dqoe),            // DDR SDRAM I/F Data bus output enable signal 
        .ddr_dq_out(ddr_dq_out),        // DDR SDRAM I/F Data bus output 
        .ddr_dqm(sig_ddr_dqm),          // DDR SDRAM I/F Data mask lines
        .ddr_dqsoe(ddr_dqsoe),          // DDR SDRAM I/F Data strobe output enable signal 
        .ddr_dqs_out(ddr_dqs_out)       // DDR SDRAM I/F Data strobe output 
        
        );



// ====================================================================
// PLL Block FOR ORCA4 
// ====================================================================
`ifdef ORCA4
   assign pll_clk   = pll_mclk;
   assign pll_clk2x = pll_nclk;

   //Clock generation
   ddr_pll_orca U2_ddr_pll_orca(
      .clk(clk),
      .fb(nclk_bidi_fb),
      .mclk(pll_mclk),
      .nclk(pll_nclk),
      .lock(),
      .intfb()
        )/* synthesis LOC="LLHPPLL" */ /* synthesis VCOTAP="0" */ /* synthesis FB_PDEL="DEL0" */;
 
 // feedback through bidirectional buffer
 BMZ12 bidi_fb (pll_nclk, 1'b0, nclk_bidi_fb, bidi)/* syn_black_box */ /* synthesis AMPSMODE="24" */ /* synthesis BUFMODE="FAST" */;
`endif

// ====================================================================
// I/O PADS (SSTL2 -II) 
// ====================================================================

// Apply o/p's after 0.9 ns delay for removing hold violations from 
// the DDR SDRAM timing model
// Later actual I/O pads will have this delay!.

// Inputs to DDR SDRAM
   assign  #0 ddr_clk                   = pll_clk;
   assign  #0 ddr_clk_n                 = ~pll_clk;

   assign #9 ddr_cke                    = sig_ddr_cke;
   assign #9 ddr_cs_n                   = sig_ddr_cs_n;
   assign #9 ddr_we_n                   = sig_ddr_we_n;
   assign #9 ddr_cas_n                  = sig_ddr_cas_n;
   assign #9 ddr_ras_n                  = sig_ddr_ras_n;
   assign #9 ddr_ad                     = sig_ddr_ad;
   assign #9 ddr_ba                     = sig_ddr_ba;
   assign #9 ddr_dqm                    = sig_ddr_dqm;

   `ifdef XPGA   //------------- XPGA ------------------
     always @ (ddr_dqoe or ddr_dq_out) begin
      for (i=0; i<(`DSIZE/2); i=i+1) 
          ddr_dq_i[i]     = ddr_dqoe[i] ? ddr_dq_out[i] : 1'bz;
     end
     assign #9 ddr_dq = ddr_dq_i;

     always @ (ddr_dqsoe or ddr_dqs_out) begin
      for (j=0; j<(`DSIZE/16); j=j+1) 
          ddr_dqs_i[j]    = ddr_dqsoe[j] ? ddr_dqs_out[j] : 1'bz;
     end
     assign #9 ddr_dqs = ddr_dqs_i;
   `endif

   `ifdef ORCA4   //------------- ORCA4------------------

     always @ (ddr_dqoe or ddr_dq_out) begin
      for (i=0; i<(`DSIZE/2); i=i+1) 
          ddr_dq_i[i]     = ddr_dqoe[i] ? 1'bz : ddr_dq_out[i] ;
     end
     assign #9 ddr_dq = ddr_dq_i;

     always @ (ddr_dqsoe or ddr_dqs_out) begin
      for (j=0; j<(`DSIZE/16); j=j+1) 
          ddr_dqs_i[j]    = ddr_dqsoe[j] ? 1'bz : ddr_dqs_out[j];
     end
     assign #9 ddr_dqs = ddr_dqs_i;

   `endif

// Outputs from DDR SDRAM
   assign  ddr_dq_in[`DSIZE/2-1:0]      = ddr_dq;                     

// =============================================================================
// Instantiate the GSR Component. Make forcegsr to NO in synplicity
// =============================================================================
`ifdef ORCA4
GSR u1_GSR
  (
   .GSR   (reset_n)
   );
`endif


//exemplar begin
//exemplar attribute ddr_clk orca_padtype OB12F
//exemplar attribute ddr_clk LEVELMODE SSTL2
//exemplar attribute ddr_clk_n orca_padtype OB12F
//exemplar attribute ddr_clk_n LEVELMODE SSTL2
//exemplar attribute ddr_cke orca_padtype OB12F
//exemplar attribute ddr_cke LEVELMODE SSTL2
//exemplar attribute ddr_cs_n orca_padtype OB12F
//exemplar attribute ddr_cs_n LEVELMODE SSTL2
//exemplar attribute ddr_we_n orca_padtype OB12F
//exemplar attribute ddr_we_n LEVELMODE SSTL2
//exemplar attribute ddr_cas_n orca_padtype OB12F
//exemplar attribute ddr_cas_n LEVELMODE SSTL2
//exemplar attribute ddr_ras_n orca_padtype OB12F
//exemplar attribute ddr_ras_n LEVELMODE SSTL2
//exemplar attribute ddr_ba orca_padtype OB12F
//exemplar attribute ddr_ba LEVELMODE SSTL2
//exemplar attribute ddr_ad orca_padtype OB12F
//exemplar attribute ddr_ad LEVELMODE SSTL2
//exemplar attribute ddr_dq orca_padtype BMZ12F
//exemplar attribute ddr_dq LEVELMODE SSTL2
//exemplar attribute ddr_dqs orca_padtype OBZ12F
//exemplar attribute ddr_dqs LEVELMODE SSTL2
//exemplar attribute ddr_dqm orca_padtype OB12F
//exemplar attribute ddr_dqm LEVELMODE SSTL2
//exemplar end                 

endmodule

