/* Verilog netlist generated by SCUBA ORCA Foundry 2001 Production (114) */
/* C:\Program Files\ORCA\bin\nt\scuba -w -lang verilog -n ddrahb_pll -synth synplify -bus_exp 1 -bb -type pll -arch orca4 -fin 100. -mfreq 100. -nfreq 200. -pllmode delay -tap 0  */
/* Tue Mar 19 15:30:28 2002 */

`timescale 1 ns / 100 ps
module ddr_pll_orca (clk, mclk, nclk, fb, intfb, lock);
    input clk;
    input fb;
    output mclk;
    output nclk;
    output lock;
    output intfb;

    wire nclk_t/*synthesis syn_keep=1 FREQUENCY = "280.000" */;
    wire mclk_t/*synthesis syn_keep=1 FREQUENCY = "140.000" */;

    //HPPLL ddr_pll_0_0 (.CLKIN(clk), .FB(fb), .MCLK(mclk_t), .NCLK(nclk_t), 
	HPPLL ddr_pll_0_0 (.CLKIN(clk), .FB(nclk_t), .MCLK(mclk_t), .NCLK(nclk_t), 
        .LOCK(lock), .INTFB(intfb)) 
        /* synthesis VCOTAP="0"       */ 
        /* synthesis NCLKMODE="DELAY" */ 
        /* synthesis MCLKMODE="DELAY" */
        /* synthesis DIV3="1"         */ 
        /* synthesis DIV2="2"         */ 
        /* synthesis DIV1="2"         */
        /* synthesis DIV0="1"         */;


    assign nclk = nclk_t;
    assign mclk = mclk_t;

// exemplar begin
// exemplar attribute ddr_pll_0_0 VCOTAP 0
// exemplar attribute ddr_pll_0_0 FB_PDEL DEL0
// exemplar attribute ddr_pll_0_0 LOC LLHPPLL
// exemplar attribute ddr_pll_0_0 NCLKMODE DELAY
// exemplar attribute ddr_pll_0_0 MCLKMODE DELAY
// exemplar attribute ddr_pll_0_0 DIV3 1
// exemplar attribute ddr_pll_0_0 DIV2 2
// exemplar attribute ddr_pll_0_0 DIV1 2
// exemplar attribute ddr_pll_0_0 DIV0 1
// exemplar attribute nclk_t noopt true
// exemplar attribute mclk_t noopt true 
// exemplar attribute nclk_t FREQUENCY 280.000
// exemplar attribute mclk_t FREQUENCY 140.000
// exemplar end

endmodule
