library verilog;
use verilog.vl_types.all;
entity ddr_sm is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        current_cmd_v   : in     vl_logic;
        other_cmd_v     : in     vl_logic;
        bank_activated  : in     vl_logic;
        row_opened      : in     vl_logic;
        same_bank       : in     vl_logic;
        exe_master_go   : in     vl_logic;
        same_bank_for_master: in     vl_logic;
        readcmd_i       : in     vl_logic;
        trrd_wait       : in     vl_logic;
        twr_wait1       : in     vl_logic;
        tras_wait       : in     vl_logic;
        trc_wait        : in     vl_logic;
        count_cl        : in     vl_logic_vector(1 downto 0);
        cl_bl_count     : in     vl_logic_vector(2 downto 0);
        wtr_bl_count    : in     vl_logic_vector(3 downto 0);
        count_trcd      : in     vl_logic_vector(2 downto 0);
        count_trp       : in     vl_logic_vector(2 downto 0);
        bl_8            : in     vl_logic;
        bl_2            : in     vl_logic;
        read_applied_i  : in     vl_logic;
        write_applied_i : in     vl_logic;
        cmd_applied     : out    vl_logic;
        pre_apply       : out    vl_logic;
        read_apply      : out    vl_logic;
        write_apply     : out    vl_logic;
        act_apply       : out    vl_logic;
        datain_valid    : out    vl_logic;
        datain_valid_rep: out    vl_logic;
        exe_state_idle  : out    vl_logic;
        read_applied_o  : out    vl_logic;
        write_applied_o : out    vl_logic;
        sm_ras          : out    vl_logic;
        sm_cas          : out    vl_logic;
        sm_we           : out    vl_logic
    );
end ddr_sm;
