library verilog;
use verilog.vl_types.all;
entity ddr_databusif is
    port(
        clk             : in     vl_logic;
        clk2x           : in     vl_logic;
        reset_n         : in     vl_logic;
        datain          : in     vl_logic_vector(63 downto 0);
        write_enable    : in     vl_logic;
        cl_half         : in     vl_logic;
        dmsel           : in     vl_logic_vector(7 downto 0);
        ddr_dq_in       : in     vl_logic_vector(31 downto 0);
        dataout         : out    vl_logic_vector(63 downto 0);
        ddr_dqm         : out    vl_logic_vector(3 downto 0);
        ddr_dq_out      : out    vl_logic_vector(31 downto 0);
        ddr_dqs_out     : out    vl_logic_vector(3 downto 0);
        ddr_dqoe        : out    vl_logic_vector(31 downto 0);
        ddr_dqsoe       : out    vl_logic_vector(3 downto 0)
    );
end ddr_databusif;
