library verilog;
use verilog.vl_types.all;
entity ddr_genericif is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        cmd             : in     vl_logic_vector(2 downto 0);
        addr            : in     vl_logic_vector(26 downto 0);
        busy            : in     vl_logic;
        init_done       : in     vl_logic;
        update_cfg0     : in     vl_logic;
        cfg0_data       : in     vl_logic_vector(6 downto 0);
        cfg0_reg        : out    vl_logic_vector(7 downto 0);
        count_bl        : out    vl_logic_vector(1 downto 0);
        count_cl        : out    vl_logic_vector(1 downto 0);
        cl_half         : out    vl_logic;
        count_trcd      : out    vl_logic_vector(2 downto 0);
        count_trrd      : out    vl_logic_vector(2 downto 0);
        count_trfc      : out    vl_logic_vector(3 downto 0);
        count_trp       : out    vl_logic_vector(2 downto 0);
        count_tmrd      : out    vl_logic_vector(2 downto 0);
        count_twr       : out    vl_logic_vector(2 downto 0);
        count_tras      : out    vl_logic_vector(3 downto 0);
        count_twtr      : out    vl_logic_vector(2 downto 0);
        count_trc       : out    vl_logic_vector(3 downto 0);
        cfg2_reg        : out    vl_logic_vector(15 downto 0);
        start_init      : out    vl_logic
    );
end ddr_genericif;
