Article Details

ID: 355
Case Type: faq
Category: Architecture
Related To: SERDES/PCS
Family: All FPGA

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What's the best, first step to debug  looped-back 16-bit data with 8b10b encoding  for SERDES/PCS applications in Lattice FPGA's?

For this type of SERDES application, the 8-bit comma character will always occur in the same 8-bit word location in the 16-bit RX data, as long as the transmitter never sends back-to-back commas or sends commas that are an odd number of cycles apart.


If the 16-bit boundary is identical to the TX data, then nothing needs to be corrected; the data is received as it was transmitted.


If the 16-bit boundary is off by one 8-bit word, then the alignment needs to be corrected.


For example, assume B4 is a K28.5 comma.  If the data transmitted is B0B1 B2B3 B4B5 B6B7 (where the even indexed bytes are the lower 8 bits of the 16-bit TX data) and the data received is the same, no correction is necessary.


On the other, If the data transmitted is B0B1 B2B3 B4B5 B6B7 but the data received is B1B2 B3B4 B5B6, then the 16-bit boundary is off by one 8-bit word and the alignment should be corrected. To correct the alignment, a simple piece of code can be written to replace the current cycle's upper 8-bit word with the current cycle's lower 8-bit word and to replace the current cycle's lower 8-bit word with the previous cycle's upper word. The data received will then look like the data transmitted.


Please refer to FAQ 354 for a Verilog source code implementation of the byte-shifting correction logic.

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