Guidance Systems

Meet mission requirements with low power and high reliability advantages of Lattice FPGAs

For over 25 years, , Lattice has enabled leading-edge guidance systems with a wide range of high reliability, SWAP-C optimized products that meet today’s security, longevity, and extreme environment challenges. Engineers at leading defense contractors rely on our deep system-level knowledge, collaborative spirit, local support, and design resources to meet the most stringent design requirements.

Lattice COTS FPGAs provide the flexibility to adapt to the requirements of next generation precision guided systems with low power actuator control, sensor fusion, and signal processing solutions. The latest Lattice Nexus platform features industry leading low power and high reliability to meet the challenging requirements of next generation guidance platforms.

Key Lattice FPGA Features & Benefits

  • Superior low power consumption and thermal performance compared to other FPGAs, enabling longer missions, and simplifying thermal management
  • Industry leading small form factor FPGAs, optimized for highest I/O density, connect to more sensors, creating a high-fidelity situational awareness
  • Lowest soft error rate (SER) in its class and highest latch-up immunity to maximize integrity of ground-based and airborne systems
  • Enables low latency, deterministic, instant-on start-up with initial I/O configuration in less than 3 ms and full device configuration in as little as 8 ms

Jump to

Example Applications

Actuator Control

  • Single-chip non-volatile FPGAs with 2ms bitstream verification, authentication and boot-up time
  • Embedded A/D converters for sensor fusion, feedback and sensing
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm

Trigger

  • Critical bitstream verification and safety compliance
  • ECDSA bitstream authentication, coupled with robust AES-256 encryption
  • Robust flash-based FPGAs ideal for sensor processing and control

Telemetry

  • Power efficient, highly reliable system control and monitoring
  • Optimum integration level with embedded MCU and ADCs
  • Utmost control and flexibility in sense and control of rea-time data

Reference Designs

SPI Slave 到 PWM 产生

Reference Design

SPI Slave 到 PWM 产生

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
SPI Slave 到 PWM 产生
简单的Σ-Δ ADC

Reference Design

简单的Σ-Δ ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
简单的Σ-Δ ADC
使用嵌入式功能块的I2C从外设

Reference Design

使用嵌入式功能块的I2C从外设

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
使用嵌入式功能块的I2C从外设
ADC 接口

Reference Design

ADC 接口

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
ADC 接口

IP Cores

UART 16550 IP核

IP Core

UART 16550 IP核

可配置的UART端口。与PC16550D兼容。7或8位数据宽度,Tx有1、1.5、2个停止位。多个奇偶校验和波特率选项。
UART 16550 IP核
PCI Express x1、x4 Root Complex Lite IP核

IP Core

PCI Express x1、x4 Root Complex Lite IP核

Provides a x1 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1、x4 Root Complex Lite IP核

Development Kits & Boards

ECP5 Versa开发套件

Board

ECP5 Versa开发套件

设计工程师可使用ECP5 Versa开发套件快速评估ECP5 FPGA关键的互连功能,包括PCI Express、千兆以太网、DDR3和通用SERDES的性能。
ECP5 Versa开发套件
ECP5-5G  Versa开发套件

Board

ECP5-5G Versa开发套件

评估PCI Express 2.0、千兆级以太网、DDR3和ECP5-5G SERDES的性能
ASC桥接板

Board

ASC桥接板

加速复杂电源管理任务的开发和原型设计
ASC桥接板
L-ASC10分线板

Board

L-ASC10分线板

L-ASC10(ASC)分线板是一款通用的硬件平台,适用于L-ASC10器件的评估和开发。本分线板须与Platform Manager 2开发套件一起使用。
L-ASC10分线板
POWR1014A分线板(Breakout Board)

Board

POWR1014A分线板(Breakout Board)

POWR1014A是一款低成本的分线板,可提供到Power Manager II (POWR1014A)、LED、实验区域的完整I/O访问,可通过USB供电和进行编程,同时莱迪思提供可下载的演示。
POWR1014A分线板(Breakout Board)

Demos

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
标题 编号 版本 日期 格式 文件大小
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.0 9/30/2020 PDF 651.2 KB
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