This example places an ispMACH 4000ZE CPLD in a 4x4 mm, 0.4 mm pitch, 64-ball ucBGA package (LC4064ZE-UMN64) in an 6-layer stack up with 100% I/O utilization. This example demonstrates a modified dogbone fanout technique to access all pins yet minimize layers and via schedules. Layer setup uses reference planes for high-speed signals.
Note: This is a sample design and is not intended to be used for any particular application. Before applying any technique, confirm that your PCB fabrication service will support the dimensions specified.
| Specification | mm | mils |
|---|---|---|
| Trace Width/Space | 0.10/0.10 | 4/4 |
| Ball Pad | 0.18 | 7 |
| Ball Mask | 0.28 | 11 |
| Escape Via Pads | 0.25/0.40 | 10/16 |
| Escape Via Drills | 0.10/0.15 | 4/6 |
| Escape Via Mask | NA | |
| Plane Antipad Space | 0.48 | 19 |
| Thermal Relief | NA | |
For mechanical dimension details on packages, see the Lattice Semiconductor Package Diagrams, Data Sheet Package Diagrams.
Layer 1 Primary |
Layer 2 GND |
Layer 3 Signal |
Layer 4 Signal |
Layer 5 Power |
Layer 6 Secondary |
© Lattice Semiconductor Corporation 2013
