This BGA breakout and routing example places a MachXO PLD in a 14x14 mm, 0.8 mm pitch, 256-ball caBGA package (LCMXO2280-B256/BN256) into two fabrication scenarios. One for a 6-layer stack up with 100% I/O utilization and a 4-layer with 15% fewer I/Os. The 6-layer design (Example #1), demonstrates the best use of mechanically drilled blind vias to place caps near power pins to minimize layers.
Note: This is a sample design and is not intended to be used for any particular application. Before applying any technique, confirm that your PCB fabrication service will support the dimensions specified.
| Specification | mm | mils |
|---|---|---|
| Trace Width/Space | 0.10/0.10 | 4/4 |
| Ball Pad | 0.35 | 14 |
| Ball Mask | 0.50 | 20 |
| Escape Via Pad | 0.40 | 16 |
| Escape Via Drill | 0.15 | 6 |
| Escape Via Mask | NA | |
| Plane Antipad Space | 0.50 | 20 |
| Thermal Relief | 0.60 | 24 |
Layer 1 Primary |
Layer 2 Signal |
Layer 3 GND |
Layer 4 Power |
Layer 5 Signal |
Layer 6 Secondary |
| Specification | mm | mils |
|---|---|---|
| Trace Width/Space | 0.10/0.10 | 4/4 |
| Ball Pad | 0.35 | 14 |
| Ball Mask | 0.50 | 20 |
| Escape Via Pad | 0.40/0.45 | 16/18 |
| Escape Via Drill | 0.125/0.2 | 5/8 |
| Escape Via Mask | NA | |
| Plane Antipad Space | 0.50 | 20 |
| Thermal Relief | 0.60 | 24 |
1. Heat reliefs are suppressed on microvias.
Layer 1 Primary |
Layer 2 GND |
Layer 3 Power |
Layer 4 Secondary |
© Lattice Semiconductor Corporation 2013
