sysIO Design Resources

The following information is a summary of available resources to help you with all aspects of working with sysIO for Lattice programmable products.

The following documents are available on the Lattice website.

Subject	Product Family	Title
SysIO	LatticeECP3	TN1177 LatticeECP3 sysIO Usage Guide
	LatticeXP2	TN1136 LatticeXP2 sysIO Usage Guide
	LatticeECP2/M	TN1102 LatticeECP2/M sysIO Usage Guide
	MachXO2	TN1202 MachXO2 sysIO Usage Guide
	MachXO	TN1091 MachXO sysIO Usage Guide
	LatticeSC/M	TN1088 LatticeSC PURESPEED I/O Usage Guide

IBIS Models

IBIS models provide a standardized way of representing electrical characteristics of an I/O Buffer without revealing the underlying circuit or process information. All Lattice’s IBIS models pass the standard IBIS Golden parser (latest version) are successfully loaded in Mentor’s Hyperlynx , Mentor’s ICX and HSpice simulation tools . A customer can generate an IBIS model customized for their design through the Lattice Diamond software by running:

Process -> Export Files -> IBIS

Customers can also download a generic IBIS file from the Lattice Website: IBIS Models by Product

IBIS Related FAQs

• Is there an IBIS model for PowR605?
• Does Lattice provide IBIS model for SERDES inouts of LatticeECP3?
• How can I generate a much smaller IBIS model file that only includes the IO types defined in my project?
• Which IBIS models should I use for the MachXO2 JTAG signal pins?
• How do I properly simulate a LVPECL differential IO when only a single ended IBIS IO model is provided?
• The IBIS model file is text, how can I view the output IO waveform?
• Do Lattice’s IBIS models include the RLC data for each pin?
   

Hot Socket / Power-up

Hot socketing refers to the ability to safely connect an unpowered device to the circuit board when the circuit board is powered up. During hot socketing we can guarantee the leakage current (IDK) specified in the device datasheet. We cannot guarantee the state of the pin or voltage on the pin; user needs to be within absolute maximum rating in the datasheet

Hot Socket / Power-up Related FAQs

• What are the Hot Socket capabilities of LatticeECP2M, LatticeECP3, and LatticeSC/M SERDES I/O?
• Are all IOs of LatticeECP3 in high-impedance state when VCC, VCCIO and other power supplies do not have power applied?
• What is the IO state when VCC, VCCAUX reach the datasheet recommended levels but VCCIO has not? 
• I want to use the output of one Lattice MachXO2 I/O bank to control power on the board to the remaining VCCIO banks. Is this possible assuming that I will first power up the MachXO2 using only VCC core and one VCCIO bank?
• For the MachXO's Idk (hot socketing leakage spec), what factors control whether the Idk is sourced or sunk? 
• What is the default configuration of the I/O pins in a blank MachXO2 device? 
• Do I need to power up unused banks?
   

Hot Socket / Power-up Related Blogs

• I/O Initialization: Beware of Shark Fins!

Termination

Termination on IOs is required to reduce or eliminate reflection by matching the transmission line impedance.

Termination Related FAQs

• Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
• Is AC-Coupling OK to use in my application?
• Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
• What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?
• What are the limitations of thevenin terminations for LatticeSC/M devices?
   

IO Standards

Emulated differential output will run slower than the true differential buffer. Facts about true and emulated differential outputs support of our devices, for instance, 50% of IOs on left and right sides in ECP3/MachXO2, 50% of IOs on all sides on ECP4 are true differential outputs please refer to datasheet and tech note.

There are no “emulated differential inputs”, all differential inputs are true differential buffer. Input termination is required based on differential standard specification and board SI simulation

IO Standard Related FAQs

• What can I do to maximize the emulated LVDS data rate?
• Should pullups be enabled or disabled for PCI outputs for PCI33?
• Can I still drive sub-LVDS input with XP2 even XP2 doesn’t have sub-LVDS output type? 
• I don't see Differential 3.3v CMOS inputs (LVCMOS33D) input characteristics in the MachXO2 Data Sheet. What are its specifications?
• Can the MachXO2 device support PCI-compliant signaling on any GPIO? 
• Does the ECP2/M differential input support on-chip termination?
• Which I/O type should I use between LVTTL or LVTTL_5V for 75 5V inputs to an ispMACH4000 device?
• Can LatticeECP3 device support sub-LVDS IO?
• What are the available options for LVDS IO in the LatticeECP3?
• Why does the Lattice software pick VCCIO bank voltages smaller than 3.3V when all my design IO buffers are of the 3.3V type?
• How can I specify a LVPECL differential I/O in my RTL source code?
• How do I interface an LVPECL clock source to a Lattice SERDES reference clock (which is a CML input)?
• Does the MachXO device family support true LVDS buffers?
• Does MachXO2 support mixed voltage for LVCMOS and LVTTL IO type?
   

IO Tolerance

An I/O can usually endure the current surge caused by the short-circuit to ground as long as the combined output current does not exceed n*8mA between two GNDs. A shorted output pin won't cause permanent physical damage to the device instantly. But extended use may cause long-term reliability issue.

The absolute maximum ratings for all I/Os are in the datasheet - 3.75 is the absolute max for most of our devices. The recommanded max voltage would depend on the I/O standard, spec is under DC electrical Characteristics. The JTAG pins will follow LVCMOS recommended values. The LVCMOS standard used would depend on VCCJ value or for some devices it will depend on the VCCIO of the bank in which they are located.

IO Tolerance Related FAQs

• Why is there a limit on the number of 5V tolerant IOs in the ispMACH 4000 device?
• Are there any pins that can’t be used when the SERDES is being used?
• What is the maximum rise/fall time for inputs on I/O or clock pins? 
• Can I connect JTAGENB pin of MachXO2 device directly to the VCC or GND?
• Can I use the input buffers of LatticeECP3 device to receive LVPECL33 signals?
• Can LatticeECP3 LVDS25 be driven by an LVDS18 output of a transmitter device?  

SSN (Simultaneous Switching Noise)

When many outputs switch simultaneously, they can momentarily cause the device GND to rise or VCC to drop with respect to the system GND (Ground Bounce) or system VCC (VCC Bounce). If the bounce is higher than the input threshold of the receiving device, it may incorrectly cause a trigger. SSN is related to the total inductance and sum of instantaneous current changes V_BOUNCE = L_TOTAL x di/dt

Some ways to prevent SSN:

• Do not use the higher drive strengths or slew rates if not required
• Distribute simultaneously switching outputs across multiple GND pins
• We require not drawing more than “n*8ma” between 2 GND pins, n is the number of I/Os between bank GNDs or between last GND in the bank and the end of a bank
• Pay attention to PCB layout
  • Add Decoupling caps on all VCC/GND
  • Proper Termination of all interfaces
• Use of pseudo VCCIO or GND pads next to switching pins
• For DDR3 interface, follow all the pin out guidelines and recommendations listed in technote tn1180

Use Diamond SSO calculator to estimate SSO for the pin assignments

SSN (simultaneous Switching Noise) Related FAQs

• Can I use the available spare IOs to help lower SSO noise?
• How can I estimate the BLVDS SSO?
• What is your recommendation to reduce or eliminate SSO noise related issues for DDR3 interface implementation using a LatticeECP3 device?
• How do I determine Simultaneous Switching Noise (SSN) from within Lattice Diamond tools?
• How do I place DDR3 interface pins to minimize SSO impact?
   

Pin Migration

Pin Migration files (.csv) are available on the website to switch designs to a bigger or smaller density device with the same package.
Some common problems during pin migration:

• Pins bonded out in larger density devices may not be bonded out on the smaller density device
• Pins that are of type “I/O” (input/output) may now be “I” Input only or vice versa
• Pins that support True LVDS may no longer be True LVDS pins
• A given DQS group may not exist on smaller devices 
• Pins within a DQS group may not be bonded out resulting in fewer DQ pins in the DQS group
   

Pin Migration Related FAQs

• We would like to use a higher density device, but a DQ output becomes a PLL input on the larger device, is there a work around for this?