The following information is a summary of available resources to help you with all aspects of working with sysIO for Lattice programmable products.
The following documents are available on the Lattice website.
|SysIO||LatticeECP3||TN1177 LatticeECP3 sysIO Usage Guide|
|LatticeXP2||TN1136 LatticeXP2 sysIO Usage Guide|
|LatticeECP2/M||TN1102 LatticeECP2/M sysIO Usage Guide|
|MachXO2||TN1202 MachXO2 sysIO Usage Guide|
|MachXO||TN1091 MachXO sysIO Usage Guide|
|LatticeSC/M||TN1088 LatticeSC PURESPEED I/O Usage Guide|
IBIS models provide a standardized way of representing electrical characteristics of an I/O Buffer without revealing the underlying circuit or process information. All Lattice’s IBIS models pass the standard IBIS Golden parser (latest version) are successfully loaded in Mentor’s Hyperlynx , Mentor’s ICX and HSpice simulation tools . A customer can generate an IBIS model customized for their design through the Lattice Diamond software by running:
Process -> Export Files -> IBIS
Customers can also download a generic IBIS file from the Lattice Website: IBIS Models by Product
Hot socketing refers to the ability to safely connect an unpowered device to the circuit board when the circuit board is powered up. During hot socketing we can guarantee the leakage current (IDK) specified in the device datasheet. We cannot guarantee the state of the pin or voltage on the pin; user needs to be within absolute maximum rating in the datasheet
Termination on IOs is required to reduce or eliminate reflection by matching the transmission line impedance.
Emulated differential output will run slower than the true differential buffer. Facts about true and emulated differential outputs support of our devices, for instance, 50% of IOs on left and right sides in ECP3/MachXO2, 50% of IOs on all sides on ECP4 are true differential outputs please refer to datasheet and tech note.
There are no “emulated differential inputs”, all differential inputs are true differential buffer. Input termination is required based on differential standard specification and board SI simulation
An I/O can usually endure the current surge caused by the short-circuit to ground as long as the combined output current does not exceed n*8mA between two GNDs. A shorted output pin won't cause permanent physical damage to the device instantly. But extended use may cause long-term reliability issue.
The absolute maximum ratings for all I/Os are in the datasheet - 3.75 is the absolute max for most of our devices. The recommanded max voltage would depend on the I/O standard, spec is under DC electrical Characteristics. The JTAG pins will follow LVCMOS recommended values. The LVCMOS standard used would depend on VCCJ value or for some devices it will depend on the VCCIO of the bank in which they are located.
When many outputs switch simultaneously, they can momentarily cause the device GND to rise or VCC to drop with respect to the system GND (Ground Bounce) or system VCC (VCC Bounce). If the bounce is higher than the input threshold of the receiving device, it may incorrectly cause a trigger. SSN is related to the total inductance and sum of instantaneous current changes VBOUNCE = LTOTAL x di/dt
Some ways to prevent SSN:
Use Diamond SSO calculator to estimate SSO for the pin assignments
Pin Migration files (.csv) are available on the website to switch designs to a bigger or smaller density device with the same package.
Some common problems during pin migration: