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|Question||ID||Family||Case Type||Case Category||Related To|
|Why does my FPGA not work after power up using my own CPU embedded program code?
||3124||All FPGA||Hardware||Device Programming||Embedded Programming|
|On devices with XRES pin, what effect does noise on adjacent pins to the device function?||3120||All FPGA||Hardware||Architecture||IO|
|Why sometimes I cannot mix MachXO2 inputs with different voltages in one bank for LVCMOS and LVTTL I/O Types in Lattice Diamond ?
|When should I custom one SPI Flash with Lattice Diamond Programmer, if the sector format is mixed with 4K-byte and 64K-byte, how can I do it?
||3053||All FPGA||Hardware||Device Programming||Diamond Programmer|
|Why can I not program the 2032A PLD with ispVM?
||3045||All CPLD||Software||Device Programming||ispVM System|
|Is BT656 format a valid input format for De-interlacer IP?||3041||Other FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Interleaver/De-interleaver|
|What is PPLVDS? What is the difference between LVDS and PPLVDS? Can Lattice ECP3 devices support this interface?||3032||LatticeECP3||Hardware||Architecture||IO|
Do Lattice ispVM support the programming via Channel A and Channel B of FT2232H for Lattice MachXO2 devices?
|3031||MachXO2||Hardware||Device Programming||ispVM System|
|Why does it show a license error when I use Remote Desktop to 'log into' and run the design at the workstation?
||3027||All Devices||Software||Licensing||Lattice Diamond|
|How to connect the terminations for address, control and data lines for DDR2?
||3026||LatticeECP3||Hardware||Customer Board Design||Schematic Review|
|Why can two registers with the same clock/clock enable/reset signals not be packed into one slice after MAP?||3017||All Devices||Hardware||Architecture||General Logic|
|If the device is not yet programmed, it will be booted in Default Mode Feature Row. Will the INITn pin automatically be used as an input? And can I (accidently) block the configuration of the FPGA by pulling INITn low?||2994||MachXO2||Hardware||Architecture||Configuration/Programming|
|What's the relation between Logic Replication and Fanout?||2986||All Devices||Software||Implementation||Synthesis|
|How to solve library dependencies when installing Diamond on 64 bit Linux machine?||2985||All Devices||Software||Installation||Linux|
|Can Power/Platform Manager devices be programmed using Lattice Diamond Programmer?||2975||All Power Management||Software||Device Programming||Diamond Programmer|
In the PAC designer software is the number of "Outputs" used in a program related with the usage of macrocells in the Power Manager device ?
|2973||Power Manager II||Software||PAC-Designer||Compile/Fit|
|How can I view the "DC-DC Library Manager" Launch Button on my PAC-Designer software toolbar ?||2972||Power Manager II||Software||PAC-Designer||TRIM Usage|
|While calculating resistors for TRIM network do we need to consider VMON comparator input impedance for POWR1220AT8 ?||2965||Power Manager II||Software||PAC-Designer||TRIM Usage|
Will the "PRIVATE" instructions in BSDL file have any impact on my BSCAN test? Do I need them to perform a BSCAN test?
|2944||All Devices||Hardware||Device Modeling||BSDL|
|What is the value of the I/O internal pull-up resistor present during device programming?||2940||MachXO||Hardware||Architecture||IO|
For the POWR1220AT8 device can we switch between I2C and Closed Loop Trim modes dynamically without re-programming the device?
|2891||Power Manager II||Software||PAC-Designer||TRIM Usage|
|Which mode of AES operation is used in Lattice ECP3 Device?||2890||All Devices||Software||Device Programming||Configuration/Programming|
|Can the weak pull-up and pull-down resistor in IO be completely shut off with PULLMODE set to NONE?||2882||MachXO2||Hardware||Architecture||IO|
|Are all pins defined as NC really not connected to anything? So, if a breakout was going to route through NC pins, there would not be an issue?||2879||MachXO2||Hardware||Architecture||IO|
What is the recommended connection for the VCCIO pads on an unused LatticeECP3-EA bank, connected to a known state or left unconnected?
|How do I assign delays to my modules without getting synthesis error?
|How do I read the resources numbers shown in "Hierarchy" tab after I perform "Generate Hierarchy"?
||2856||All Devices||Software||Implementation||HDL Explorer|
Do I need to connect a 100 ohm series resistor between monitored voltages and VMON pins on the POWR1220AT8 device?
|2855||Power Manager II||Hardware||Customer Board Design||Schematic Review|
What is the behavior of the Programn, Initn, and Done Pins when disabled on the MachXO2 in SDM Mode?
|Does Lattice Diamond Design Software installation files contain Bloodhound.Sonar.9 virus?
|My SPI Flash device is not listed in Diamond Programmer. How can I use this SPI Flash with Lattice FPGAs and program them using Diamond Programmer?||2821||All FPGA||Software||Device Programming||Diamond Programmer|
|Can I use the TRIM output to drive the input of an opamp buffer by writing DAC register values via I2C on the POWR1220AT8?||2819||Power Manager II||Hardware||Architecture||TRIM|
|FLEXnet License Finder utility included in Lattice Diamond 2.0 does not register the license when using 64-bit Diamond 2.0 on 64-bit Windows 7.||2809||All FPGA||Software||Licensing||Lattice Diamond|
Why don't I see the IP core from the core list in the IPexpress main GUI after the core has been successfully installed?
|How can I fit Picopower Demo Source of ispMACH 4000ZE Pico Development Kit in ispLEVER Classic 1.6 ?
||2804||ispMACH 4000||Hardware||Lattice Evaluation Board||ispMACH 4000ZE Pico Dev Kit|
What are the rules when locking DQ-DQS grouping pins?
How do I create a new Reveal Analyzer file without deleting an existing .rva file in my Lattice Diamond project directory?
What's the propagation delay inside LUTs of Lattice ECP3?
Can we short the inputs of two VMON comparators ( i.e. VMON1 and VMON2) of the Power Manager Device externally on the board for monitoring a supply rail ?
|2790||Power Manager II||Hardware||Customer Board Design||Schematic|
Why do I get the message "ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible" on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?
|2781||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|How can I add a net that directly connects with an input signal and an output signal in Diamond Schematic Editor ?
|Can I create a LogiBuilder state machine with more than 127 steps in PAC-Designer?||2772||Power Manager II||Software||PAC-Designer||LogiBuilder|
What is the behavior of the MachXO2 oscillator when transitioning between configuration and user mode?
How does slow slew rate on TCK input affect Lattice FPGA device programming?
|2756||All FPGA||Hardware||Device Programming||Configuration/Programming|
Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?
|Why is Reveal Hardware Debugger not working when my LatticeEC Standard Evaluation Board is inserted into my PC's PCI slot?||2743||LatticeEC||Hardware||Lattice Evaluation Board||ECP/EC-Standard|
|Why do I get error messages when running ispVME?||2732||All Devices||Software||Device Programming||ispVM Embedded|
|Can I have both 32-bit and 64-bit versions of Lattice Diamond Design Software in my Windows7 PC?
||2730||All FPGA||Software||Installation||Win 7|
|Why is that in a mixed language designs, the top level signals are listed as nets not as ports in Reveal Hardware Debugger Inserter?
Why does my ispVM System software not properly recognize Platform Manager?
|2725||Platform Manager||Hardware||Device Programming||ispVM System|
|Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS inTX-to-RX Serial Loopback Mode?||2722||LatticeECP3||Hardware||Architecture||SERDES/PCS|
Can Power Manager II Device support Hot Socketing?
|2721||Power Manager II||Hardware||Architecture||IO|
|Do I need to power up unused IO banks?||2717||All Devices||Hardware||Architecture||IO|
What does the "potential loop circuits" section of the Place and Route TRACE report mean?
|2715||All FPGA||Software||Implementation||Timing Analysis|
|What are the programming modes available in Lattice iCE40 device?||2714||ICE40||Hardware||Device Programming||Configuration/Programming|
|What are the hardware and software requirements to program the NVCM (Non Volatile configuration Memory)of an iCE40 device?||2713||ICE40||Hardware||Device Programming||Configuration/Programming|
Do Lattice's IBIS models include the RLC data for each pin?
|2709||All Devices||Hardware||Device Modeling||IBIS|
The Lattice HDR-60 layout file is in Allegro .brd format, can Lattice translate the file to other formats?
|2699||LatticeECP3||Hardware||Customer Board Design||Layout|
|My MCS file translated from JED file by "Universal File Writer" doesn't match with the JED file we read back from the device. Is it supposed to match?
||2696||MachXO2||Software||Device Programming||ispVM System|
|Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?||2695||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||2.5Gb Ethernet MAC|
|How do I get further detail for the "Failed to read design" error message in Reveal Inserter?
|Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?
||2691||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
What is best practice for the MachXO2 Slave SPI Chip Select (SN)?
|Why do I have two top-level wrappers inside a DDR3 IP core package genarated from IPexpress? Which one should I use for my design?||2684||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|Are there any issues if power is lost to the MachXO2 while being programmed using I2C?||2682||MachXO2||Hardware||Architecture||Configuration/Programming|
What happens to the MachXO2 internal oscillator during background flash programming?
|Can output controlling be used for 7:1 LVDS design on LatticeECP3 devices?
In the PAC Designer Trim Configuration Options what does "Open External Resistors(s) Threshold" impliy?
|2674||Power Manager II||Hardware||Customer Board Design||Schematic Review|
MachXO2 datasheet states that LVDS33 is supported but I cannot select this IO Type in the software and an error is generated if it is added manually to the .lpf file.
|Are the registers in MachXO2 initialized to a known value after a re-configuration operation?
||2665||MachXO2||Hardware||Device Programming||Embedded Programming|
|How can I Disable/Enable the Slave SPI/I2C configuration interface without editing it in the spreadsheet view and re-implementing the design?||2664||MachXO2||Hardware||Device Programming||Configuration/Programming|
|Why do I observe the JTAG ID Code of the device in bit reversed format when I transmit read ID instruction in Slave SPI Mode?
||2663||LatticeECP3||Software||Device Programming||Embedded Programming|
|Can I program the External SPI Flash using Slave SPI Interface in LatticeECP3 device?||2662||LatticeECP3||Software||Device Programming||Configuration/Programming|
|In Lattice Diamond 2.0 or later versions, how can I resolve the error message "Reference to undefined module" in schematic design created in Lattice Diamond 1.4 or earlier versions ?||2659||All FPGA||Software||Implementation||Schematic|
|Why do I get a netsanitycheck PAR error when a MUX drives the clock of a IDDR/ODDR component?||2657||LatticeECP3||Software||Implementation||PAR|
Why does an SVF file for LatticeXP2-17 Erase/Program/Verify operation take a longer time to perform the operations compared to the time of Diamond Programmer or ispVM?
|2656||All Devices||Software||Device Programming||Diamond Programmer|
Is there a low cost way to power the ProcessorPM-POWR605 off of a 5V rail?
|2655||Power Manager II||Hardware||Architecture||Power|
What are DELPHI Compact Thermal Models, how can these be used and what is their scope?
|2652||All FPGA||Hardware||Device Modeling||DELPHI|
What programming support is available for LatticeXO2 SSPI and I2C with the download cable?
|I changed my design and now it works for a breif amount of time and then begins to fail, what can cause this?||2646||All FPGA||Hardware||Customer Board Design||Board Debug|
How does the Clock Data Recovery (CDR) Loss of Lock pin on the LatticeECP3 behave when the reference clock is stopped?
How do I restore the LatticeECP3 IO Protocol evaluation board back to the original factory programming?
|2642||LatticeECP3||Hardware||Lattice Evaluation Board||ECP3-I/O Protocol|
|In the Lattice IBIS files, the series resistance code of all IO type is 'a', which mean "off". I want to know in simlation, what resistance value should I set for output?||2641||All Devices||Hardware||Device Modeling||IBIS|
|We were attempting to reprogram the MachXO2 device via I2C interface from the processor. We've messed something up in the software download. Now, via the JTAG interface we get the failure: "Failed to verify the ID"
How can we recover the device?
|2640||MachXO2||Hardware||Device Programming||Embedded Programming|
|I have a question about the clock stretching feature of EFB's I2C block: TN1205 indicates clock stretching will be done automatically when CKSDIS=0. What are the specific conditions when clock stretching is used by the EFB I2C core in slave mode?||2639||MachXO2||Hardware||Architecture||Embedded Functional Block (EFB)|
|How can I implement the global clock and global output enable in Lattice CPLD ?
|Why can't I fit my design again after back annotating the pins?||2635||ispMACH 4000||Software||Implementation||Fitter|
How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains?
|2633||All Devices||Software||Implementation||Timing Analysis|
What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?
|How do I double check whether my LatticeCORE IP is licensed or not?||2628||All Devices||Software||Licensing||IP|
Is there a limit to the number of state machines implemented in the POWR1220AT8 in PAC-Designer?
|2625||Power Manager II||Software||PAC-Designer||LogiBuilder|
|What will happen if the HVOUT driver current setting in PAC-Designer is less than the actual requirement of the MOSFET?||2624||Power Manager II||Hardware||Architecture||HVOUT|
How can I calculate the power consumption in a Platform Manager device?
|I am worried about high temperatures in a particular Lattice development/evaluation board. My application cannot afford these temperatures, can Lattice help me ?||2619||All Devices||Hardware||Architecture||Power|
|In the Platform Manager Fault Logging Demo design; is there any timing restriction after ready and before SN?||2618||Platform Manager||Hardware||Architecture||Power|
|Why is some logic in a sub-module not packed into the group after PAR when this sub-module is grouped with the HGROUP attribute in the source code?
The generated DDR3 IP core includes a DDR3 DIMM (dual in-line memory module) instantiation module (ddr3_dimm_32.v) in the testbench when the selected memory type is On-board Memory. How can I instantiate the DDR3 device memory model in my testbench for simulation?
|2604||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|How long can I evaluate the DDR3 IP core on the hardware system using the bitstream generated in the evaluation mode without a license? Can I continue my evaluation when the evaluation timer expires?||2603||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?
What does "potential circuit loops found in timing analysis" in trace report mean?
|How can I determine the exact number of hot-socketable I/O on a LatticeECP3 device?||2588||LatticeECP3||Hardware||Architecture||IO|
What are the neccesary configurations for using the ispClock5600A with single ended input clocks?
|2587||ispClock 5600A||Hardware||Customer Board Design||Schematic|
In the PAC-Designer TRIM block, why does the Vbpz value sometimes change when the EIA Resistor Standard is changed in the options menu?
|2586||All Power Management||Software||PAC-Designer||TRIM Usage|
Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?
|2583||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
How can I connect the Platform Manager trim profile selection to Profile 0 in hardware?
|2582||Platform Manager||Software||PAC-Designer||TRIM Usage|
|How can I compile Lattice libraries for simulation with Modelsim?||2579||All Devices||Software||Simulation||MTI|
When using the File->Import command in PAC-Designer, what information is imported from the JEDEC file?
|2578||All Mixed Signal||Software||PAC-Designer||Schematic|
|How does the accuracy of the VID IP for Platform Manager compare to the closed loop trim feature of the POWR1220?
||2577||Platform Manager||IP/Reference Designs||Lattice IP/Reference Designs||Closed-loop Trim/Fault Logger|
Is it possible to manually assign TRIM DAC output voltages to Power Manager II Devices, rather than using the trim configuration calculator?
|2574||Power Manager II||Software||PAC-Designer||TRIM Usage|
How does the DC-DC Converter library work with the TRIM resistor calculation in PAC-Designer when a project is opened but does not have access to the original DC-DC Converter library?
|2573||Power Manager II||Software||PAC-Designer||TRIM Usage|
What are the recommendations for a flex cable that connects a sensor to the Lattice HDR-60?
|2567||LatticeECP3||Hardware||Lattice Evaluation Board||HDR-60 Eval Board|
|When interfacing with the MachXO2 EFB's SPI IP core, how do I avoid data over-flow and under-flow conditions?||2565||MachXO2||Hardware||Architecture||Embedded Functional Block (EFB)|
Why can the total number of I/O pins not be used for the MachXO2 device?
|How is the input register implemented in the ispMACH 4000 V/B/C/Z/ZE family?||2562||ispMACH 4000||Software||Implementation||Constraint-Pref Editor|
|Why does the signal values turn RED in the structure tab of Design browser of Aldec Active HDL, while running simulation.||2553||All Devices||Software||Simulation||Aldec|
|What is Timing Simulation and what files does Lattice Diamond design generate to facilitate timing simulation.||2552||All Devices||Software||Simulation||Aldec|
Where can I find information about the package thermal resistance of the ispPAC-POWR1014/A device?
|2547||Power Manager II||Hardware||Architecture||Packaging|
Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?
|2545||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SGMII and Gb Ethernet PCS|
Does MACHXO2 support mixed voltage for LVCMOS and LVTTL I/O type?
|What is the correct orientation of Lattice FPGA programming bit streams?||2539||All FPGA||Hardware||Device Programming||Customer Board|
|How do I enable Slave SPI mode and I2C mode for device access/programming in user mode (when the device has been configured)?||2538||MachXO2||Software||Device Programming||Configuration/Programming|
|How can I access the full rate recovered clock to sample the receive data in a Lattice X1 Native PCIe IP targeting either LatticeECP2M or LatticeECP3 devices?||2533||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Why is the bit count for a Serial Vector Format Verify operation greater than my BIT file?||2531||All FPGA||Hardware||Device Programming||ispVM System|
Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?
|2527||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Where can I find the process technology information for the Power Manager II products?
|2521||Power Manager II||Hardware||Reliability and Materials||Device Materials|
|What is the meaning of "I/O Tristate Voltage Applied" and "Dedicated Input Voltage Applied" specified in the Absolute Maximum Ratings section of MachXO data sheet?||2516||MachXO||Hardware||Architecture||IO|
|What is the best way to program a Lattice MachXO2 device in the field with minimum disruption?||2514||MachXO2||Hardware||Device Programming||Configuration/Programming|
|Can LatticeECP3 LVDS25 be driven by an LVDS18 output of a transmitter device? How about the other way around?||2513||LatticeECP3||Hardware||Architecture||IO|
|Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?
||2511||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|How can I configure Lattice devices using a micro-controller in embedded systems?||2510||All Devices||Software||Device Programming||Embedded Programming|
|Which tool generates embedded files for embedded programming & configuration with the latest versions of Lattice Diamond Software?||2509||All Devices||Software||Device Programming||Embedded Programming|
|In the Power Manager device, is the output impedence of HVOUT port (in open drain mode) equal to that of the OUT port?||2507||All Power Management||Hardware||Architecture||IO|
Can I use same JEDEC file or bit file to program different speed rating parts?
|2504||All Devices||Software||Device Programming||Configuration/Programming|
When running Reveal Analyzer what files are needed and where do I get the files?
What is the programming time for XO2 device, when use I2C bus to programm the chip?
|2494||MachXO2||Hardware||Device Programming||Embedded Programming|
|Can my task for CPU embedded programming of FPGA be interrupted on the CPU during programming?
||2493||All FPGA||Software||Device Programming||ispVM Embedded|
|Is the PLL Lock time, Tlock, measured from power ramp up?
||2491||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|How can I create a hierarchical schematic design ?
|What are difference between I/O symbols and I/O ports in Schematic Editor
How to cross trigger between multiple cores with Reveal?
|Which limitations we must pay attention to when setting trace and trigger signals?||2485||All Devices||Software||Debugging||Reveal|
|Which actions we should take when facing "failed to connect with jtagserver" with Reveal Analyzer?||2483||All Devices||Software||Debugging||Reveal|
Why do I get EDIF translation Errors when my EDIF file contains a Reveal Core?
|What should we do when seeing a message "failed to connect with jtagserver" by Reveal Analyzer with parallel cable?||2479||All Devices||Software||Debugging||Reveal|
|How to view or print waveform with Modelsim using the VCD file generated by Reveal Analyzer?||2477||All Devices||Software||Debugging||Reveal|
|Why must I use a Primary Clock Input for a clock instead of a general purpose pin?||2475||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?
|2474||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|Why does the PLL simulation model act differently than hardware?
|Can I select the type of HDL files generated, verilog or VHDL, for my schematic project?||2466||All FPGA||Software||Implementation||Schematic|
|How can I generate a block symbol from a schematic ?
|How can I generate a schematic symbol to represent my HDL module?
|How can I convert a schematic design from one device to another device ?
What is the current sink capability of the LOCK pin in the ispClock 5600A?
|2459||ispClock 5600A||Hardware||Customer Board Design||Schematic|
Which Lattice parts are recommended for new designs in place of the POWR1208P1?
|2455||All Power Management||Hardware||Architecture||Power Sequence|
What is the allowed voltage at the VMON pins when the POWR607 is unpowered (hot socket scenario)?
|2454||Power Manager II||Hardware||Customer Board Design||Schematic|
|What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?
|Is there a reference design availble for the HDR-60 Development Kit?||2452||LatticeECP3||Hardware||Lattice Evaluation Board||HDR-60 Eval Board|
During Trim configuration in PAC-Designer, I receive an error when calculating DAC settings for my target profiles. What can cause this?
|2449||Power Manager II||Software||PAC-Designer||TRIM Usage|
Why do I see the EMI change when adding or removing an unprogrammed Lattice device to our parallel bus design?
|2439||All FPGA||Hardware||Customer Board Design||Board Debug|
|What is the XO2 Primary port I2C address "yyyxxxxx11" for, and how is it used?
What methods are available to initiate configuration for the LatticeXP2?
Why does multiple Place and Route report a syntax error and abort?
Which version of the HDMI specification does the LatticeECP3 HDMI/DVI Interface reference design support and does it pass HDMI compliance tests?
|2431||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||HDMI/DVI Interface|
I got a static timing result, fMAX=300MHz, for a generic DDR X1 mode while the LatticeECP3 datasheet fMAX_GDDR(max)=250MHz. Can I safely use 300MHz for the generic DDR 1X interface?
I cannot assign the DDR3 memory clock (CK) pads to Bank 1 during the DDR3 core generation when the left side of a LatticeECP3 device is selected for a DDR3 interface running at 300MHz. How can I use the pins in Bank 1 for CK?
|2427||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
In the ispClock5400D family, how are the USER0-USER3 pins configured prior to programming?
|2423||ispClock 5400D||Hardware||Device Programming||Configuration/Programming|
Is it possible to use the PowerManager_1220_I2C_Utility.exe in Windows 7? I see a message stating "Error: Kernel Mode Driver is not loaded in memory" when I try to launch it.
|2418||Power Manager II||Software||PAC-Designer||Design Utilities|
|The EFB WISHBONE interface Read and Write transactions do not appear to simulate correctly. Is there a problem with 'wb_ack_o'?
What happens to MachXO2 configuration ports (JTAG/I2C/SSPI) when power is removed when reprogramming the Configuration Flash or User Flash memory?
|Can I switch between multiple PLL input frequencies that have the same divider settings?
||2406||All Devices||Hardware||Architecture||PLL/DLL/Clock Routing|
Lattice Diamond Programmer isn't listing a new SPI Flash device I would like to use, is there a work around?
|2404||All FPGA||Software||Device Programming||Diamond Programmer|
|Why doesn't my FPGA configure correctly from Slave SPI Embedded when using Deployment Tool to generate the data and algorithm files?||2403||All FPGA||Software||Device Programming||Diamond Programmer|
|What is the PLL Delay Multiplier "Dynamic Mode" and why is a "Programmable Delay Unit" a range in the datasheet ?
|When do I need a custom mask file to verify a device with ispVM or Diamond Programmer?||2401||All FPGA||Hardware||Device Programming||Configuration/Programming|
Does the FPGA section of the Platform Manager have an SPI or I2C interface? Where are the registers defined for these interfaces?
|2396||Platform Manager||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|What is the requirement for SCLK and DQCLK to make ODDRX2 work?
|Can Lattice's reference design "HDMI/DVI Interface" support audio function?
||2393||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||HDMI/DVI Interface|
|Can Lattice's reference design "HDMI/DVI Interface" support all resolutions defined in HDMI/DVI specification?
||2392||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||HDMI/DVI Interface|
|Please provide pre-emphasis characteristics data for LatticeECP3 SERDES.
|Can all Tx PLL clocks of SERDES drive the primary clock routing directly?
|Do BLOCK constraints limit the maximum coverage % reported in the timing report that can be achieved (<100%)?||2389||All Devices||Software||Implementation||Trace|
Can I run a DDR3 interface at frequencies as low as 100MHz using LatticeECP3?
|2386||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
After executing the orc_cmpl.bat ModelSim VHDL library compilation script, why do I get errors about unexpanded library elements when I compile my design?
Does the reference design "Fault Logging and Monitoring Using Platform Manager Devices", support SPI or I2C interface to the FPGA from a master Microcontroller?
|2383||Platform Manager||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|How do I implement an external reference clock for SERDES?
|In Lattice Diamond, what is the difference between a Pin Layout File and a Pin Out file?
||2378||All FPGA||Software||Implementation||Design Planner|
What are the allowed input currents for the Power Manager II VMON and digital inputs? Is there a specific recommendation for protecting those inputs?
|2377||Power Manager II||Hardware||Customer Board Design||Schematic Review|
|Using a PCLK pin I get a warning in PAR that my secondary clock will use general routing, why?
The bitstream download time can vary for Lattice MachXO device programing mode. Does "debug" mode increase the download time?
LatticeECP3 device has a low power family. Can the bitstream used for the regular device be programmed in the low power device?
|2372||LatticeECP3||Software||Device Programming||Diamond Programmer|
How does the RX loss of signal detection circuitry in the LatticeECP3 PCS/SERDES react to constant value or a drop in signal condition on the SERDES serial inputs?
What kind of models can I use to simulate Lattice IO packages parasitics?
|2365||All FPGA||Hardware||Device Modeling||IBIS|
|Why does my design fail to compile with a Warning 1211: Generate NAF file failed ?
||2363||Power Manager II||Software||PAC-Designer||Compile/Fit|
An output pin in my PAC-Designer project is now assigned as a node. Why did it change and how can I change it back to an output?
|2358||All Power Management||Software||PAC-Designer||Compile/Fit|
|How can I guarantee that the state machine will return to the known state from any invalid state?||2357||All Devices||Software||Implementation||Synplicity|
|Can I lock the dual-link 7:1 LVDS pins to the left and right sides of a LatticeECP3-17EA device?
|How do I add delay to a net in my design?||2354||All FPGA||Software||Implementation||Other|
|What is the function of the Synplify Pro's option "Fix Generated Clocks"?||2353||All FPGA||Software||Implementation||Synplicity|
|Does Lattice Diamond support a parameterized module other than the fixed parameter module generated by IPexpress?||2352||All FPGA||Software||Implementation||IPExpress|
|How do I check the timing of the paths across two clock domains in the trace report?||2351||All FPGA||Software||Implementation||Timing Analysis|
|I have successfully run Place & Route Design with the commercial device. How can I generate a trace report for the same device with Industrial grade and 85C but without rerunning the synthesis and MPAR?||2350||All FPGA||Software||Implementation||Trace|
|Why is the shift register in my design implemented with the distributed RAM instead of register resources?||2348||All FPGA||Software||Implementation||Synthesis|
Why does the Lattice software pick VCCIO bank voltages smaller than 3.3V when all my design IO buffers are of the 3.3V type?
|In a Mico System Builder(MSB) project, can the characters transmitted through the UART be displayed on the Simulator console||2345||All Devices||Software||Implementation||Mico32(MSB)|
|Why are most components not available for Lattice Mico8 in the Mico System Builder?||2342||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
What is the maximum size of the SSPI Embedded SEA/SED data files?
|2340||All FPGA||Software||Device Programming||ispVM System|
|What is the starting address for an external SPI Flash connected to the MachXO2 device in Dual Boot mode and when the configuration preference is set to External?||2339||MachXO2||Hardware||Device Programming||Configuration/Programming|
|Why do I get an error complaining of the RELEASE pin when I'm compiling the library module CLKDIVB with Modelsim 10.0B?||2334||LatticeXP2||Software||Simulation||MTI|
Can LatticeECP3 devices support sub-LVDS IO?
|Why does my encrypted bitstream have an ASCII header, and will it cause problems with programming the FPGA?||2329||All FPGA||Software||Device Programming||Configuration/Programming|
|How do I create a Serial Vector Format (SVF) file that does not include the Lattice proprietary LOOP instructions?||2328||All FPGA||Hardware||Device Programming||ispVM System|
|In Aldec Active-HDL, how do I save & reload the format changes I have made to the waveforms?||2326||All FPGA||Software||Simulation||Aldec|
Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?
|2324||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|In LatticeECP3, can I use the receiver for 2.97Gbps HDMI and the transmitter for 3G SDI(or HD_SDI) in a same channel?||2321||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|Why do my BSCAN2 outputs change state randomly?||2320||All Devices||Hardware||Device Programming||Configuration/Programming|
|Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?||2319||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|Where can I find documentation which details command line operations for device programming?||2318||All FPGA||Software||Device Programming||Configuration/Programming|
Is it possible to program the LatticeXP2 SRAM directly using slave SPI mode?
|Why does my POWR1014A design fail to compile but not give an error message?||2310||Power Manager II||Software||PAC-Designer||Compile/Fit|
|Why does Aldec Active-HDL report the size of my design has exceeded the maximum capacity of the Lattice Web Edition?
|How can you convert from XO2 JEDEC (text file) to binary data in order to program the JEDEC into configuration flash memory from external CPU through SSPI?||2302||MachXO2||Hardware||Device Programming||ispVM System|
What are the differences between the specific SPI Flash devices listed in the Lattice programming software tool?
|2301||All FPGA||Hardware||Device Programming||ispVM System|
|What are the different programming and configuration modes available in LatticeXP2 devices?||2297||LatticeXP2||Hardware||Device Programming||Configuration/Programming|
How can I resolve the Reveal error: core0 incorrect signature (RVL: 154782948 != Device: 0)
What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?
|2294||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Why is there a Timing Rule Check violation in the trace report on a ODDRX4B element for timing between the SCLK & ECLK inside this element?
|How can I generate VME with Turbo mode in command line ?
||2290||All FPGA||Software||Device Programming||Embedded Programming|
|How can I set power-up reset and preset for ispMach4000 flip-flops ?
||2271||ispMACH 4000||Software||Implementation||Constraint-Pref Editor|
|What is the procedure to program a generic JTAG device using SVF Files and Model 300 Programmer?||2264||All Devices||Software||Device Programming||Model 300 Programer|
|What is the proper use of termination resistors and internal coupling with the Lattice Serdes?||2263||LatticeECP3||Hardware||Architecture||SERDES/PCS|
What is the latency between absence of SERDES input data and Loss of Lock signal for Lattice ECP2M/ECP3 devices?
|Which specifications values are used for "LVCMOS25/LVCMOS33" inputs on the ispPAC-CLK5610AV devices?||2260||ispClock 5600A||Literature||Inquiries||Datasheet|
|I have a DCS feeding a PLL and when it switches in simulation my pll loses lock.
Why can I only assign 7 SECONDARY clocks in a clock region instead of 8 SECONDARY clocks?
|When using Global Set/Reset (GSR), what is the reset to out delay value?
I migrated my design from DDR2 to DDR3 and noticed that there are two more edges on DQS during the write operation. Why does the DDR3 controller IP core behave like this?
|2246||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Is it OK to loop XAUI data from the RX XGMII to the TX XGMII if the IPG is always between 5 and 8 bytes long?
|2245||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||XAUI 10Gb Ethernet AUI|
I need to use four chip select signals while the Lattice DDR3 controller IP core supports only up to two. Can I extend the number of chip select from the core?
|2244||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|How can I get around the error "trace: Mangled ncd file before signal read"?
|Why does my XO2 EFB SPI / I2C Interface Lock Up when operating as a slave?
||2240||MachXO2||Hardware||Architecture||Embedded Functional Block (EFB)|
|LatticeMico System provides an option to clone a platform. When should I use this feature?||2238||All Devices||Software||Implementation||Mico32(MSB)|
We would like to use a higher density device, but a DQ output becomes a PLL input on the larger device, is there a work around for this?
|The Power Manager Datasheet specifies Vol value of open drain outputs only at a particular current. Can I estimate Vol at different currents?||2230||All Power Management||Hardware||Architecture||IO|
|When using an ABEL design can I change the timer value by changing the XLAT_STIMER count value?||2228||Power Manager II||Software||PAC-Designer||ABEL|
|Can the Lattice Mico System Builder(MSB) Mico8 support devices other than MachXO2?||2221||All Devices||Software||Implementation||Mico32(MSB)|
|What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region text is full (C_code.elf section .text)" mean?||2220||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region data is full (C_code.elf section .irq_stack)" mean?||2219||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
I am using DDR3 controller IP core v1.3 in my design. Why does the simulation result fail while the design works well without a failure on the board?
|2218||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Why do I get an error stating "FTDI port is busy", when ispVM System opens?
|2217||All Devices||Software||Device Programming||ispVM System|
|Is there a way to show the exact path to the DC-DC Library Folder? My path is very long does not display the whole path.||2215||Power Manager II||Software||PAC-Designer||TRIM Usage|
|What is the procedure to prevent unused IO logic from getting optimized out during Synthesis and MAP in Lattice Diamond, while using GUI or Active-HDL batch mode?||2214||All Devices||Software||Implementation||Attributes/Directives|
Where can I find the related documentation ans source code to program my Lattice Device using the JTAG interface in an embedded system?
|2213||All Devices||Software||Device Programming||ispVM System|
|Is there a way to actively select the configuration bitstream the LatticeECP3 loads from the attached SPI memory?||2212||LatticeECP3||Hardware||Device Programming||Configuration/Programming|
|Does VCCD and VCCA need to be above 3.0V when programming the device since the data sheet shows that VCCPROG should between 3.0V to 3.6V?||2209||Power Manager II||Hardware||Architecture||Power|
|Can ispEditor be used to modify the contents of Embedded Block RAM stored in the configuration bitstream file?||2208||All FPGA||Software||Device Programming||Configuration/Programming|
|Why does the USB ispDOWNLOAD cable raise the VCCJ voltage when I connect it to my low power board design?||2205||All Devices||Hardware||Device Programming||Cables|
|Why can't I compile my design when I get a message that states "your design has changed would you like to recompile"?||2202||Power Manager II||Software||PAC-Designer||LogiBuilder|
|What are my options with IPs that can no longer be downloaded in Lattice Diamond IPexpress?
|What are the factors affecting the CCLK frequency setting for Lattice ECP2M SPI Flash configuration?
|The ECP3 sysCONFIG technical note (TN1169) says encrypted bitstreams sent to the Slave SPI port must be sent continuously. What do I need to do to send the data continously?||2199||LatticeECP3||Software||Device Programming||ispVM Embedded|
|If two PAC-Designer exception commands trigger at the same time which one has priority?||2196||All Power Management||Software||PAC-Designer||LogiBuilder|
|Why does Diamond take so long to launch, and how can it be fixed?||2195||All Devices||Software||Installation||Win-All|
Why do I get "Unknown Object" errors from the Spreadsheet View tool when I integrate a DDR3 IP core into my project?
|2193||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?
|2191||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
|Can a "blank check" be performed on Lattice devices to ensure they are blank?||2188||All Devices||Hardware||Device Programming||Configuration/Programming|
How to generate an input port on the schematic in Lattice Diamond Schematic Editor?
|For the MachXO's Idk (hot socketing leakage spec), what factors control whether the Idk is sourced or sunk?||2185||MachXO||Hardware||Architecture||IO|
|Does the Lattice DL2A Parallel Port download cable use an off-the-shelf RJ45 cable?
||2183||All Devices||Software||Device Programming||Cables|
|Will POR signal be generated when only VCCINP is present and VCCD/VCCA are unavailable, causing a defined state at the OUTx pins?||2182||Power Manager II||Hardware||Architecture||IO|
How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?
|2174||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|What are the steps to compile/elaborate a SERDES based design in NC-Verilog?
Will the LatticeECP3's read datavalid generation circuit work properly when I remove the VTT termination from the DQS pad?
|2157||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
|How can you determine if the MachXO2 has booted from the internal flash or SPI flash using dual boot?||2155||MachXO2||Hardware||Device Programming||ispVM System|
|Why is an error generated when I migrate my schematic based design from ispLEVER to Lattice Diamond?||2153||All FPGA||Software||Entry||Schematic|
|What is the procedure to create a Parallel Flash PROM file for Lattice FPGA devices with Lattice software tools?||2152||All FPGA||Hardware||Device Programming||3rd Party|
|Does MachXO2 EFB I2C support frequencies other than the 50, 100, and 400 KHz options available in IPexpress?||2151||MachXO2||Hardware||Architecture||Embedded Functional Block (EFB)|
|Where can I find MSL (Moisture Sensitivity Level) for various packages of Lattice devices?||2143||All Devices||Hardware||Architecture||Packaging|
What is the reason behind high supply transients during startup for the ispMACH 4000 device?
|2142||ispMACH 4000||Hardware||Architecture||Power Sequence|
What are the main differences between Flash Programming Mode and Flash Background Mode?
|2141||All Devices||Software||Device Programming||ispVM System|
|What is the difference between the Standard and Window modes for the VMON trip points?||2139||All Power Management||Hardware||Architecture||VMONs|
Why does the XO2 IBIS model show lower edge rate difference (fast vs. slow) than the ECP3 IBIS model?
|Why are the constraint coverage numbers different between the setup and hold analysis sections of Trace report with the MAXDELAY NET preference?
|Does the warning "@W:MT246 Blackbox EHXPLLJ is missing a user supplied timing model" have any negative effect on the timing analysis and optimization or the Quality of Results?||2128||All Devices||Software||Implementation||Synthesis|
|Should pullups be enabled or disabled for PCI outputs for PCI33?
|What is the device programming time of a Lattice FPGA?||2125||All FPGA||Hardware||Device Programming||Configuration/Programming|
|Can Diamond Programmer 1.3 be used to program an Intel Hex file (.mcs) created by ispVM System?||2120||All Devices||Software||Device Programming||Configuration/Programming|
|How can I use Test Access Port (TAP) Instructions for a Power Manager Device ?||2119||All Power Management||Hardware||Device Programming||ispVM System|
Can I connect an external LVDS25 clock output to a LatticeECP3 DDR3 bank which is 1.5V VCCIO bank?
|2118||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
Can I connect JTAGENB pin of MachXO2 device directly to the VCC or GND?
The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?
|2116||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
|Why do I get "Version not supported" when I run SSPI Embedded?||2112||All Devices||Software||Device Programming||ispVM Embedded|
|How can I select between 2 clocks and avoid gating it using fabric resources?
||2111||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
Why do I have a netsanitycheck error when I make a dynamic clock selector drive DDR primitive components in my LatticeECP3 design?
|How can I reprogram a MachXO2 when both the JTAGENb and PROGRAMn inputs are reconfigured as general purpose input/output?||2108||MachXO2||Hardware||Device Programming||Configuration/Programming|
My LatticeXP2 bitstream loads an initial TAG memory content. When I re-configure the TAG memory, how can I preserve it so it is not overwritten with the initial content the next time I re-load my original bitstream.
|Can LatticeECP3 support the 1.35V operation mode of the 1.35V DDR3 SDRAM?||2102||LatticeECP3||Hardware||Architecture||DDR/DDR2/DDR3|
|What is the status of GSR (Global Set/Reset) during Configuration Mode?
||2101||All FPGA||Hardware||Device Programming||Configuration/Programming|
|Can I bypass the PCS 8B10B encoding/decoding function and still use the CTC FIFO?||2099||All FPGA||Hardware||Architecture||SERDES/PCS|
|Do the different number of preambles (5 or 6) on the SGMII IP receive side match the SGMII protocol?
||2097||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||SGMII|
How does the Big/Little Endian switch effect the functionality of the FIFO_DC in IPExpress?
|2095||All FPGA||Hardware||Architecture||Memory EBR/Distributed|
Can I read a 1.0 Volt signal from the ADC with attenuator setting 1 (divide by 3) on a PWR6AT6 device?
|2093||Power Manager II||Hardware||Architecture||I2C|
|What size SPI flash devices are required to be used with LatticeECP3 devices?||2092||LatticeECP3||Hardware||Device Programming||Configuration/Programming|
|Can LatticeECP3 device bit streams be compressed?||2090||LatticeECP3||Software||Device Programming||Configuration/Programming|
|Do Lattice devices contain any Rare Earth materials as mandated by the US Department of Commerce National Security Assessment?||2089||All Devices||Hardware||Reliability and Materials||Device Materials|
How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?
|2087||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|What is the behavior of the Platform Manager Analog inputs? Is the voltage comparator output a logic \u20181' when the voltage is above UV and OV signal type?
|How to check the un-constrained connections in Lattice Diamond?||2084||All FPGA||Software||Implementation||Timing Closure|
How do I check the coverage of my timing constraints?
|2083||All FPGA||Software||Implementation||Timing Closure|
|How to effectively use secondary region clock in LatticeECP3 devices?||2082||LatticeECP3||Software||Implementation||Timing Closure|
|Where can I find the driver for Lattice USB programming cable in Lattice Diamond 1.3?
||2081||All FPGA||Hardware||Device Programming||Cables|
|Can a 156.25MHz reference clock be used for PCIe?||2079||LatticeECP3||Hardware||Architecture||SERDES/PCS|
Can the default BSDL file provided on the Lattice web site be used to test a programmed LatticeECP3 device after reinitialization?
|Should I run gate level simulation for the PCIe Basic Demo from the Lattice PCIe Development kit?
||2076||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Is there a limitation to the name that I can give for my project directory?
||2073||All Devices||Software||Implementation||Project Navigator|
What is the optimum PCB solder mask opening and pad diameter for a Lattice package?
|2072||All Devices||Hardware||Customer Board Design||Layout|
What is the POR state of I2C controlled input and output pins in POWR1014A?
|2070||Power Manager II||Hardware||Architecture||IO|
|What is the WB_CTI_I signal in the Lattice PCI Express Scatter Gather DMA Demo design?||2069||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Why is the error "Unable to locate valid JED file" generated when compiling in PAC-Designer?||2064||Platform Manager||Software||PAC-Designer||Compile/Fit|
How do I get a DDR3 simulation result based on my mode register program values? I generated a DDR3 IP core with my mode register initialization values, but the evaluation simulation provides the results with different mode register settings.
|2059||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
Why does my regenerated DDR3 IP core have different CL and CWL values from the original LPC file that has CL=7 and CWL=6 at 400MHz?
|2058||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|What type of download cables do different Lattice programming/debugging software support under different operating systems?||2056||All Devices||Software||Device Programming||Configuration/Programming|
Is there a way to implement a 4-bit DDR3 memory controller using the Lattice DDR3 controller IP core?
|2054||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|How many HDL sub modules can I import in a Platform Manager design using PAC software ?||2050||Platform Manager||Software||PAC-Designer||LogiBuilder|
|Does ispVM Embedded support TAG memory operations with the XP2?||2049||LatticeXP2||Hardware||Device Programming||ispVM Embedded|
|I have 75 5V inputs to an ispMACH4000 device. Which I/O type should I use between LVTTL or LVTTL_5V?||2045||ispMACH 4000||Hardware||Architecture||IO|
Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
How do I place DDR3 interface pins to minimize SSO impact?
|2041||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|Can the POWR1220AT8 be used to monitor negative voltages?||2040||Power Manager II||Hardware||Architecture||IO|
|Why does the Fitter report show some Flip flops as TFF and others as DFF for my design?||2039||Power Manager II||Software||PAC-Designer||Compile/Fit|
|How much undershoot on the SDA pin can a POWR1220AT8 device endure without causing damaging?||2038||Power Manager II||Hardware||Architecture||I2C|
|What are the last four characters in the JEDEC file of a Lattice CPLD ?||2037||All CPLD||Software||Device Programming||Configuration/Programming|
|Using the command line, is there a command to directly convert .JED to .VME?
||2034||All Devices||Software||Device Programming||ispVM System|
|Is it possible to determine what functions an ispVME data file performs?||2031||All FPGA||Software||Device Programming||ispVM Embedded|
|How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE Report?||2024||LatticeECP3||Hardware||Architecture||PLL/DLL/Clock Routing|
|Do the Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae?||2022||All FPGA||Hardware||Architecture||SERDES/PCS|
|Will open drain and HVOUT outputs have defined state when VCCD/VCCA are unavailable and VCCINP is supplied?||2020||Power Manager II||Literature||Inquiries||Datasheet|
|When executing multiple Place and Route (PAR) Jobs in parallel, what is the maximum number that can be executed at one time?||2011||All FPGA||Software||Implementation||PAR|
Which IBIS models should I use for the MachXO JTAG signal pins?
Which IBIS models should I use for the MachXO2 JTAG signal pins?
How do I select between the two Vol Max values 0.4V, or 0.2V documented in the LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics?
We are seeing the primary clock delay to multiple IO Logic elements are the same in the LatticeECP3 device, is this correct?
Why does the I/O vector editor in the Device Information window "Expand Option" not generate the I/O vector file (*.iov file), when I click "Apply" instead of "Save As"?
|2002||All Devices||Software||Device Programming||ispVM System|
|What is the buffer type for the POWR1220AT8 JTAG TDO pin and what voltage should the pull-up resistor be tied to for this pin?
||1997||Power Manager II||Hardware||Architecture||JTAG|
Why doesn't the delay time unit change when I change the skew setting from fine to coarse for an ispPAC-CLK56xx device?
|Why does the place and route tool not fix hold violation for my design despite Auto Hold-Time Correction being set to "On"?
||1993||All FPGA||Software||Implementation||Timing Closure|
How many idle ordered sets will the SGMII and Gb Ethernet PCS IP Core Clock Tolerance Compensation logic insert or delete during an Inter packet Gap period?
|1991||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SGMII and Gb Ethernet PCS|
|Should I add a ferrite bead to the VCC core voltage supply?||1983||All FPGA||Hardware||Customer Board Design||Schematic|
|Why is Lattice freezing ispLEVER after the release of version 8.2?||1982||All Devices||Software||Licensing||ispLEVER|
|Is it possible to generate gate level netlist in Lattice Diamond/ispLEVER for evaluating the IP core?||1981||All FPGA||Software||Implementation||Simulation Files|
What types of JTAG multi chain designs does the Lattice ispVM System software support?
|1978||All Devices||Hardware||Device Programming||Customer Board|
|Do I need to purchase "28-pin converter" to program a Lattice Device with my Model 300 Programmer?||1977||All Devices||Hardware||Device Programming||Adapters|
|Windows device manager displays "Code 10: The device cannot start" and unable to install driver making ispVM System unable to communicate||1976||All Devices||Software||Device Programming||ispVM System|
|Why are padding bits required for every LatticeXP2 FPGA except the LatticeXP2-40 when it is programmed in Slave SPI mode?||1974||LatticeXP2||Hardware||Device Programming||ispVM Embedded|
|What is the difference between -M and the device speed grade HOLD analysis?
||1972||All FPGA||Software||Implementation||Timing Analysis|
|Does Lattice provide any test data for MachXO2 device subjected to atmospheric neutrons ?||1969||MachXO2||Hardware||Reliability and Materials||Reliability|
|What do users need to consider when using the LatticeECP2/M Dynamic Clock Select (DCS)?
|How do I disable irrelevant clock domain crossings during the device implementation?
||1964||All FPGA||Software||Implementation||Timing Analysis|
What is the delay value on each step for the MachXO2 input data delay DELAYE module?
Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?
|How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?
|Is there a method to partition a PRIMARY clock network?||1957||LatticeECP3||Hardware||Architecture||PLL/DLL/Clock Routing|
|Why am I getting a "0 items scored" result in my trace report on a MAXDELAY preference?
||1954||All Devices||Software||Implementation||Timing Analysis|
|How should tx_req be implemented on the Lattice PCIe core user interface for better transmit throughput?||1947||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Are there hardware resources that helps me to achieve my input HOLD requirements?||1946||All FPGA||Hardware||Architecture||IO|
|With no DONE bit, how can I use JTAG to see if the SRAM download from flash is finished in the MachXO device?||1943||MachXO||Hardware||Device Programming||Configuration/Programming|
|What causes a design to fail to compile with the error f38009? It also says invalid p38031.
||1930||Power Manager II||Software||PAC-Designer||Compile/Fit|
Do the I2C inputs on the ispPAC-POWR1014 have hysteresis?
|1928||Power Manager II||Hardware||Architecture||I2C|
|How do I know the mandatory Lattice Diamond files to save so that I can re-generate the bitstream at a later time?||1927||All FPGA||Software||Implementation||Project Navigator|
|Can Lattice Diamond be run remotely on a client PC machine?||1924||All Devices||Software||Installation||Win-All|
|Should I generate the positive and negative sides for a differential signal in design and then directly assign them to two pads in a pair ?||1920||All FPGA||Software||Implementation||Constraint-Pref Editor|
|What can I do when I get "par: Failed to dump design to file" message?
How can I generate a much smaller IBIS model file that only includes the IO types defined in my project?
|1911||All FPGA||Hardware||Device Modeling||IBIS|
|Can I Run Multiple Place and Route (PAR) in Parallel?
Are ispClock products suitable for ITU-T G.8262 applications?
|How do I keep clock net names unchanged, with and without having a reveal file active?
Why am I unable to view the simulation waveform window in PAC-Designer ?
|1896||All Power Management||Software||PAC-Designer||Simulation|
|How do I change the I2C Address of the ISPPAC1014A device using the I2C Utility within PAC-Designer?
||1895||Power Manager II||Software||PAC-Designer||Design Utilities|
|Why can't I see the deployment icons in the LatticeMico System Builder (MSB) Software Deployment Tools dialog?
Lattice SERDES based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?
|I want to use the output of one Lattice MachXO2 I/O bank to control power on the board to the remaining VCCIO banks. Is this possible assuming that I will first power up the MachXO2 using only VCC core and one VCCIO bank?
|When the LatticeFPGA PLL input clock is Spread Spectrum Clock(SSC), does thise SSC pass thru the PLL or is it filtered by the PLL?||1882||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
Is FIFO bridge in the PCS used in the low latency CPRI IP core?
|How do I write my own programming utility using that uses Lattice download cables?
||1872||All Devices||Hardware||Device Programming||Cables|
|Can the PROGRAMn and DONE pins on the LatticeXP2 be used as general purpose input/output?
How do you reset the I2C interface on Power Manager II devices?
|1869||Power Manager II||Hardware||Architecture||I2C|
What would happen to the Delay Control bus (DCNTL) output of the DLL when the LatticeSC DLL looses lock?
|Can I instantiate three "Single-color Plane" 2D Scaler IP cores, and output the three color planes in parallel?||1865||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||2D Scaler|
|In Self-Download Mode, how does the DONE signal behave?
|For the open drain outputs, how much leakage current can be expected?||1862||Power Manager II||Hardware||Architecture||Power|
I have given clock constraint in my constraint file (LPF), then why am I getting a warning in synthesis that the clock is not constrained?
Why are the D filp flop nodes are being assigned to IO pins and causing my ispGAL design not to fit.
|When running PAC-Designer, what does the error message "The application has failed to start because the application configuration is incorrect. Reinstalling the application may fix this problem" mean?||1853||All Mixed Signal||Software||PAC-Designer||LogiBuilder|
Does the PAC-Designer I2C utility work with the Lattice USB Download cable?
|1850||Power Manager II||Software||PAC-Designer||Design Utilities|
I recently started seeing the Warranty Warning shown below whenever I start the ispLEVER software. Does this mean my license is invalid or that I would no longer have access to certain tools?
|Why does my timing report show a negative edge clock being used but I did not use one in my design?||1840||All Devices||Software||Implementation||Timing Analysis|
|What is the SAFE attribute in Synplify ?||1839||All Devices||Software||Entry||Synopsys|
What is the meaning of this warning in Active-HDL:
Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line breakpoints, code coverage, and assertion debug will not be available.
|When using MachXO2 devices in Dual-Boot configuration mode, at what address should the 'Golden' bitstream image (.bit file) be stored in the external Slave-SPI device?
|I am using Generic 8b10B protocol with LatticeECP3 device. Is there an example of the 16-bit word alignment verilog code? If not, is there a way to generate the code in the Lattice Diamond software tools?
|How does multiple Place and Route assign jobs on Linux?
Can LatticeECP3 FPGA device's multiple I/Os be connected in parallel to produce higher combined output I/O current exceeding that of a single I/O?
Will I see a difference in duty cycle when I use IO set to FAST slew rate versus the SLOW slew rate?
|Should the LatticeECP2/M SERDES Reset Sequence in Technical Note 1124 (TN1124) be used instead of the 4 ms delay for PCI Express design?
||1824||LatticeECP2/M||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Why does my PMI FIFO get a simulation error, "Error! Fifo depth can only be power of 2!"?||1822||LatticeECP3||Software||Simulation||Aldec|
|How can I encrypt my design using the Free version of Lattice Diamond?
||1816||All FPGA||Software||Device Programming||Configuration/Programming|
|Are clock domains from the SERDES non-related for the Lattice PCIe IP?
||1814||All FPGA||Software||Implementation||Timing Analysis|
|Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?
||1813||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|How does Lattice Diamond know which IP cores were installed?
|Can the insertion of header and comments in a Serial Vector Format (SVF) data file be controlled?
||1810||All Devices||Software||Device Programming||ispVM Embedded|
|We are getting compilation errors for a schematic design in the Lattice Diamond software. The software doesn't recognize custom made symbols.||1809||All Devices||Software||Entry||Schematic|
|How much weight can the Lattice lead free BGA package tolerate (for heat sink mounting)?
|Are programming and configuring a Programmable Logic Device two different processes?||1806||All Devices||Literature||Inquiries||Appnote/Technote|
Can I make post Place and Route (PAR) changes to my design without having to run through the entire Lattice Diamond design flow?
|I have a design that shows my timing preferences are met in my Trace Report, and I have all of my clocks covered by a frequency preference, however the design fails to operate properly in hardware. What could be the problem?
How do I uninstall ispDev driver or prevent ispDEV from disabling the hibernate mode on the PC?
|1801||All FPGA||Software||Installation||ispVM System-Win XP|
|How do I determine Simultaneous Switching Noise (SSN) from within Lattice Diamond tools?||1800||All FPGA||Software||Implementation||SSO Analysis|
|Why does it take so long to program the parallel flash for AN8077, MachXO FPGA parallel flash loader design?
|How does the Lattice ispMACH 4000ZE PICO Development Kit which uses the FT2232H for programming, connect TDO from the CPLD which is 1.8V (Vcc) to the FT2232H which is at 3.3V?
||1794||ispMACH 4000||Hardware||Lattice Evaluation Board||ispMACH 4000ZE Pico Dev Kit|
Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?
|1792||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
|What is the IO state when VCC, VCCAUX reach the datasheet recommended levels but VCCIO has not?||1782||MachXO||Hardware||Architecture||Power Sequence|
|Does ispVM System support programming a Lattice MachXO2 via its Slave SPI port?
What are the differences of using syn_keep, syn_preserve, syn_noprune, NOCLIP and NOMERGE source constraints in an FPGA design?
Does Lattice provide IBIS model for SERDES inouts of LatticeECP3?
|Can I really use the MachXO2 PROGRAMN pin for user i/o without disrupting the ability to program a blank device in-system?
|Why does version 5.0 of the PCIe IPCore, have a lower throughput (~350MB) than expected for DMA applications with back to back packets of 128 Byte?||1775||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
How I can use the DELAYB cell to add delay to a input port when a single register exists between the input and output ports?
|In MachXO, are the charge pumps and oscillators working after configuration?||1771||All FPGA||Hardware||Architecture||Oscillator|
Are there any special considerations to interface the LatticeECP3 SERDES to standard SFP transceiver modules?
|Is the LatticeECP3 SCM(Serial Configuration Mode) similar to LatticeECP2 slave serial programming mode?||1766||LatticeECP3||Hardware||Device Programming||Configuration/Programming|
|Can I connect the SSPIA primitive such that both the JTAG interface and the user logic in the FPGA fabric can access the SSPI Port?
|How do I disable to SPI configuration interface so that an external device can use the SPI pins to talk to the FPGA fabric?
When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?
|1759||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||HDMI/DVI Interface|
Can the MachXO2 device support PCI-compliant signaling on any GPIO?
|What IBIS models are needed to simulate the LatticeECP3 SERDES?"
|How fast can the LatticeXP2 dynamic phase ports be changed and will this cause glitches?
How do I design a PCB land pattern for Power Manager to meet UL standards?
|1749||Power Manager II||Hardware||Customer Board Design||Layout|
Do I need to use a clock cleaner when using CPRI IP core with Lattice SERDES based FPGA?
|1748||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||CPRI|
What are the mechanical positions of the mounting holes and J58 pin A1 on the LatticeECP3 IO Protocol Evaluation Board?
|1747||LatticeECP3||Hardware||Lattice Evaluation Board||ECP3-I/O Protocol|
|I don't see Differential 3.3v CMOS inputs (LVCMOS33D) input characteristics in the MachXO2 Data Sheet. What are its specifications?
What are the functions of LatticeECP3 register bits tdrv_drvcur_set and tdrv_amp_boost?
|What is your recommendation to reduce or eliminate SSO noise related issues for DDR3 interface implementation using a LatticeECP3 device?||1736||LatticeECP3||Hardware||Architecture||SSO|
|How can we instantiate the TraceID for Lattice MachXO2 in my VHDL RTL?||1735||MachXO2||Hardware||Architecture||Embedded Functional Block (EFB)|
When running my LatticeECP3 DDR design through software PAR, it fails with a "netsanity check" error like:
"ERROR - par: netsanitycheck: the clock buf_clk on comp Inst4_DLLDELB port CLKI is driven by general routing through comp clk. Please use the appropriate constraints when using general routing for clocks"
Can Lattice CPRI IP core support auto-negotiation?
|1723||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||CPRI|
How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?
|1719||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|Why do I need to have external VTT termination only on the DDR2/3 data signals at the Lattice FPGA side but not for the address, command and control signals?||1716||LatticeECP3||Hardware||Architecture||DDR/DDR2/DDR3|
When using the FREQUENCY preference, when would I want to use the HOLD_MARGIN keyword?
|1713||All FPGA||Software||Implementation||Constraint-Pref Editor|
|How Can I get estimated timing of my design before running place and route?||1712||All FPGA||Software||Implementation||Timing Closure|
|I want to build the FT2232H into my design. How can I get the FT2232H driver source code?||1711||LatticeXP2||Software||Device Programming||ispVM System|
|How do I implement multiple DDR2/3 memory interfaces in one side of ECP3 when there is only one DQSDLL available per side?||1710||LatticeECP3||Hardware||Architecture||DDR/DDR2/DDR3|
|I have instantiated a primitive (e.g. MUX21) in my design. How do I know for sure that the MUX21 won't be merged into other logic by the software?||1709||All Devices||Software||Implementation||Synthesis|
What is the start point of "input operation" and the start point of "output operation" after TransFR command in "Leave Alone" I/O State?
|1705||All FPGA||Hardware||Device Programming||ispVM System|
|Which pin should be used for the EFB SPI clock in a MachXO2 design using the hardened SPI core?
How do I use the ispPAC-POWR1220's on-board ADC through the I2C port?
|1700||Power Manager II||Hardware||Architecture||I2C|
|Does the LatticeECP3 CPRI demo reference design work in the Lattice Diamond software?||1699||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||CPRI|
|What limitations exist in ispVM Slim Embedded as compared to ispVM Embedded?||1698||All FPGA||Software||Device Programming||ispVM Embedded|
Why do I have an error during the mapping of a DDR3 IP-based design, saying "Error: Output buffer drives output buffer: each IO pad requires one and only one buffer..."?
|1697||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||DDR3 SDRAM Controller|
When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?
Can I use the clock tolerance compensation (CTC) function of LatticeECP3 family SERDES/PCS in 10BSER mode?
Can LatticeECP3 support OC3/OC12/OC48 SONET/SDH framer or mapper applications?
What are minimum and maximum voltage levels of LatticeECP3 SERDES inputs?
Where can I find more information regarding the FPGA Loader reference design?
|1688||Other FPGA||Hardware||Device Programming||Configuration/Programming|
When implementing PCIe designs with Lattice devices that support SERDES, what should be done with the unused channels?
|1687||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?
|1686||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|What happens if the PROGRAMN pin is toggled on the MachXO2 device before device configuration is completed when in SPI configuration mode?||1681||MachXO2||Hardware||Device Programming||Configuration/Programming|
Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?
Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?
What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?
Can I use the RESETb pin on a POWR1014 or POWR1220 to reset other parts of my circuit?
|1666||Power Manager II||Hardware||Customer Board Design||Schematic|
|Ran a design with a self generated black box. Got an error about no SLIC (TBUF) support.||1664||All Devices||Software||Implementation||MAP|
|How can I force the MachXO2 to boot from the "golden boot" image in the external SPI Flash when using the dual boot feature?||1663||MachXO2||Hardware||Device Programming||Configuration/Programming|
|How do I route a DLL input from the PCLK pin and have a consistent, small delay?||1661||LatticeSC/M||Hardware||Architecture||PLL/DLL/Clock Routing|
Does the LatticeECP3 PLL require a reset after making changes to the Dynamic Phase and Dynamic Duty Cycle Adjustment features?
|What tools and IP are available for the HDR-60 evaluation board and are they free?||1652||LatticeECP3||Hardware||Lattice Evaluation Board||HDR-60 Eval Board|
Can the CLKP/CLKN outputs of the DDR3 memory controller be placed on the top side of the LatticeECP3 device?
|Should the LatticeECP2/M SERDES PLL band be manually set to band 2 for PCI Express application?
||1649||LatticeECP2/M||IP/Reference Designs||PLD Applications||XpressLite PCIe x1 Controller|
In PAC-Designer, what is error F38190?
Error reports>> Signal not found in either the #$PINS or #$NODES list.
|1648||Power Manager II||Software||PAC-Designer||Compile/Fit|
|How do I dynamically control input data delay for a dynamic phase alignment solution using the LatticeSC/M?||1647||LatticeSC/M||Hardware||Architecture||IO|
|Can we program the internal SRAM of the LatticeXP2 via SSPI port?
Where can I find more information about other manufacturer's new devices on the Lattice evaluation board?
|1645||LatticeECP3||Hardware||Lattice Evaluation Board||HDR-60 Eval Board|
|Can an output of PAC-POWR be used to drive a softstart pin of a DC/DC?||1643||Power Manager||Hardware||Customer Board Design||Schematic|
Can the POWR1014A device support a Soft-Start/Enable pin on a DC/DC converter power supply?
|1640||Power Manager II||Hardware||Architecture||IO|
How can I specify a LVPECL differential I/O in my RTL source code?
|What is the recommended specifications to connect between Lattice Devices to Aptina HiSPi interface chip?
||1636||LatticeECP3||Hardware||Lattice Evaluation Board||HDR-60 Eval Board|
How to implement two cascading PLLs in a FPGA ?
|1634||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|How do I set the SGMII and GbE PCS IP in GbE mode and disable autonegotiation, and what logic condition shoud I use to declare linkup in this mode?||1633||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SGMII and Gb Ethernet PCS|
|Does Orcastra support the Windows 7 operating system?||1632||All FPGA||Software||Debugging||ORCAstra|
|What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?||1631||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||XAUI 10Gb Ethernet AUI|
|How can I obtain a Lattice IP Core pre-compiled simulation library that targets my HDL simulation tool of choice?||1630||All FPGA||Software||Implementation||Simulation Files|
When using the trim functions of a POWR6AT6, or POWR1220 what happens if I separately disable the LDO or DC-to-DC converter being controlled?
|1628||Power Manager II||Hardware||Customer Board Design||Schematic Review|
|My new Linux license does not work with lmgrd reporting an "unrecognized command option" error. My previous license works.
||1627||All Devices||Software||Licensing||Lattice Diamond|
|What affect does device family, part density, speed grade, or package selection have on how IPexpress generates a Lattice IP Core?||1623||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Tri-Speed Ethernet MAC|
|How to do an UFM READ for a XO2-1200ES or a XO2-1200R1 device?
||1622||MachXO2||Hardware||Architecture||User Flash Memory (UFM)|
How do I measure the common mode voltage of LatticeECP3 SERDES current-mode logic (CML) signaling ?
|Why do I get error 32512 when I create a JEDEC file for a MachXO (or other Lattice FPGA) with the Linux version of Diamond?||1614||All FPGA||Software||Implementation||Project Navigator|
Where can I find detailed information about the Lattice evaluation boards?
|1613||All FPGA||Hardware||Lattice Evaluation Board||ECP3-Serial Protocol|
What should I do when I receive "Unexpected Error - Quitting" when running Orcastra in Windows 7, 64 bit mode?
|What is the depth of Serdes down/up-sampling FIFOs?||1607||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|Does default IO behavior change from device family to device family?
|Where can I find the information on how to generate an SVF file from a JEDEC file?
||1604||All Devices||Software||Device Programming||ispVM System|
|We are emulated LVDS outputs with the external resistor network shown in the datasheert and look at the saved oscilloscope image at the LVDS receiver with the 100om termination. The oscilloscope image shows that the output differential voltage measured at LVDS input is little bit more than 650mV. Now, in the datasheet, the VOD Output Differential Voltage is listed at 350mV. Why do we have an output differential voltage that is double compared to the spec value?||1603||LatticeECP3||Hardware||Architecture||IO|
In LatticeECP2M SerDes, I use continuous K character, BC as the training pattern in G8B10B mode. The received data is good but the ls_sync singal never goes high. What am doing wrong?
What are the ESD Voltage ratings with PCI Clamp "ON" in IOBUF Attributes?
|1599||All FPGA||Hardware||Reliability and Materials||Reliability|
|Can I configure LatticeMico32 to run my application after the FPGA is configured, and still have access to LatticeMico32 debug features?
||1597||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
How much duty cycle variation will a clock signal have at an output IO?
|1592||All Devices||Hardware||Customer Board Design||Board Debug|
|What is the guideline to use a general routing based clock for the LatticeECP3 device?
Why do post-fit equations differ from my design equations using PAC-Designer?
|1590||Power Manager II||Software||PAC-Designer||Compile/Fit|
How or where can I learn to use ORCAstra in my ECP3 design?
What are the different factors that affect device speed, temperature and voltage selection during software timing analysis?
|1587||All FPGA||Software||Implementation||Timing Analysis|
|How do I run post-route simulations for multiple devices?||1579||All Devices||Software||Implementation||Simulation Files|
|For a DDR2 memory controller countinous read, is a new read pulse required per Burst (4 clock cycles) or only when the read sequence has been interrupted by other commands?||1578||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
What is the recommended setting for PLL_LOL_SET?
|How do MachXO2 dual-function output pins behave during configuration mode?
In LatticeECP3, is it possible to change the serdes mode from 8b/10b to 10b serdes mode via the SCI on the fly when the data rates are same for both mode?
|How can I implement the tri-status buffer driven by the output of ODDRXD1 in ECP3 ?
Why are the LatticeECP3 LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?
Are all IOs of LatticeECP3 in high-impedance state when VCC, VCCIO and other power supplies do not have power applied?
|Where can I find Quality and Reliability report for a Lattice device ?||1545||All Devices||Hardware||Reliability and Materials||Reliability|
|Where can I find information about package thermal resistance of any Lattice device?||1544||All Devices||Hardware||Architecture||Packaging|
|Why won't Diamond generate a hierarchy or correctly synthesize my RTL?
||1542||All Devices||Software||Implementation||Project Navigator|
|Why doesn't my Aldec ActiveHDL license server work after migrating from Solaris to a Microsoft Windows or Linux based license server?
||1541||All Devices||Software||Licensing||Lattice Diamond|
|Why are there two JTAG interfaces in the Platform Manager?||1535||Platform Manager||Hardware||Architecture||JTAG|
|When implementing the Linear Feedback Shift Register (LFSR) Arithmetic Module in IPexpress, How do I set the "Feedback Polynomial"?||1534||All FPGA||Software||Implementation||IPExpress|
|What is the default configuration of the I/O pins in a blank MachXO2 device ?||1528||MachXO2||Hardware||Architecture||IO|
|Where is the reference design for SGMII to (G)MII bridge specified in IPUG60 ?||1524||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||SGMII|
|Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC framer and processor core?||1515||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||CPRI|
|What effect does a PCS local/remote fault signal to the 10 Gb+ Ethernet MAC have on the MAC TX and RX logic?||1514||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||10Gb+ Ethernet MAC|
|Why does it take 4 minutes to program the XP2 FPGA device with the svf file generated by ispVM System software?||1501||LatticeXP2||Software||Device Programming||Configuration/Programming|
Are drivers available for the LCD-Pro USB interface that are compatible with Windows7 64-bit operating system?
Which HDL entry methods are available for Lattice Platform Manager devices?
|1496||Platform Manager||Software||Entry||Mixed Language|
Are "Boundary Scan Descriptive Language ", ( BSDL ) files available for Lattice Power Manager devices?
|1495||All Mixed Signal||Hardware||Device Modeling||BSDL|
|Does the LatticeMico8 Microcontroller Support Interrupts?||1493||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|How do I prevent the Synplify synthesis tool from removing an unused input pin from my design?||1492||All FPGA||Software||Implementation||Synplicity|
|How do PAC-Designer's project archiving functions work?||1490||All Mixed Signal||Software||PAC-Designer||LogiBuilder|
|What is the .ELF file that is generated by the LatticeMico32/LatticeMico8 Software Project Enviroment C/C++ compiler?||1489||All FPGA||Software||Implementation||Mico32(MSB)|
|What is the command line to export CSV file using ispLEVER on Linux?||1488||All Devices||Software||Implementation||Design Planner|
|What is the power guard feature in MachXO2 devices?||1483||MachXO2||Hardware||Architecture||Power|
|What is the structure of internal oscillator in MachXO2 devices?
|Why am I getting the error message "Failed to verify ID" during Full Scan using DL3A/B/C cable?||1479||All Devices||Hardware||Device Programming||ispVM System|
|Can I use an ispPAC-POWR1220 for -48V hot-swap control?||1476||Power Manager II||Hardware||Customer Board Design||Schematic|
|How do I estimate PLL jitter for the ispClock-5600 for my operating conditions?||1475||ispClock 5600V||Hardware||Customer Board Design||Schematic|
|What is status of HVOUT pins at power-on reset,in the power manager POWR1220AT8 device?||1472||Power Manager II||Hardware||Architecture||Power|
|What happens if the Power goes down during FLASH Programming?||1471||All Devices||Hardware||Device Programming||ispVM System|
|Are there two JTAG ports in the Platform Manager?||1470||Platform Manager||Hardware||Architecture||JTAG|
|How can I set up the simulation time in PAC Designer ?||1467||All Mixed Signal||Software||PAC-Designer||Simulation|
|What are the features of the hardened I2C block in MachXO2?
|How do you include the heat sink information for power calculation in Lattice Diamond?
||1461||All Devices||Software||Implementation||Power Calculator|
|What is a SYN File?
||1460||All Devices||Literature||Inquiries||Ref. Design|
What are the different synthesis options available for Lattice Diamond?
|1459||All Devices||Software||Entry||LSE (Lattice Synthesis Engine)|
|What is the default routing resource utilization value in estimation mode in the Power Calculator?
||1458||All Devices||Software||Implementation||Power Calculator|
|How do I activate the retiming feature in Synplify synthesis flow ?
|How can I load a Value Change Dump (VCD) file into Power Calculator?||1456||All Devices||Software||Implementation||Power Calculator|
|What should be the settings of the comparator when the VMON analog inputs are not used?||1452||All Power Management||Software||PAC-Designer||VMON Usage|
|Can I program Hercules Demo Board using the USB cable provided with the kit?||1449||Power Manager II||Hardware||Lattice Evaluation Board||Hercules-Standard|
|In PAC Designer software what does NODEx mean in Pin Definitions?||1446||All Power Management||Software||PAC-Designer||LogiBuilder|
|Is there a I2C hardware verification utility available in PAC-Designer?||1445||All Mixed Signal||Software||PAC-Designer||Design Utilities|
|How do I generate LatticeMico8 executable ".mem" file?||1443||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|Are there any limitations to be aware of when using the LatticeMico8 C compiler?||1442||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|Upon starting LatticeMico8 compiler why do I receive error message "Cannot find Cygwin.dll file" ?||1441||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|How can I access the internal ADC registers in Platform Manager?||1438||Platform Manager||Hardware||Architecture||General Logic|
|What does the PAC Designer error message "Error ID 8: At least one output instruction is required with one write" mean?||1437||All Power Management||Software||PAC-Designer||Compile/Fit|
|Does Power Manager or Platform Manager devices have power down mode for reducing power consumption ?||1436||All Power Management||Hardware||Architecture||Power|
|While Implementing state machine Sequencer Instruction in LogiBuilder, I want to create an Exception condition in Step 0 and an error message pops up. What does that mean?||1435||All Power Management||Software||PAC-Designer||LogiBuilder|
|While using PAC-Designer can I simulate or analyze analog signals?||1434||All Power Management||Software||PAC-Designer||Simulation|
|How do I protect VMON input pins of the Platform Manager and Power Manager devices from noise or accidental spikes?||1433||All Power Management||Hardware||Customer Board Design||Schematic|
I tryed to generate a PLL module with the IPExpress tool of the Lattice Diamond but the generate button was grayed out. How can I generate a PLL in the IPExpress?
|How should I partition logic between the CPLD and FPGA blocks when using Platform Manager?||1430||Platform Manager||Hardware||Customer Board Design||Schematic|
|Can you power up an ispPAC-POWR1014 or ispPAC-POWR1220 through the ESD protection diodes?||1429||Power Manager II||Hardware||Architecture||Power|
|How should the RESETb pin be used on the ispPAC-POWR1014/1220?||1427||Power Manager II||Hardware||Architecture||Power Sequence|
|What is the function of the MachXO2 FPGA's Edge Clock Bridge?
|How much time does the MACHXO2 devices take to perform an SRAM CRC Error Detection?
|What's the difference between the TraceID and the USERCODE for MACHXO2 device?
|Can I access the on-chip Flash memory use the Master SPI Mode(MSPI) for MACHXO2 device?
|Can I configure the configuration SRAM memory with the Slave SPI Mode(SSPI)?
|How do I trigger the Dual Boot function for MACHXO2 device?
|How do I specify how the POWR1014A is packaged; tube, tape and reel or tray?||1419||Power Manager II||Hardware||Reliability and Materials||Device Materials|
On a Platform Manager, what do I need to do to un-used pins?
|1417||Platform Manager||Hardware||Customer Board Design||Layout|
Why can't I get the Aldec Active HDL simulator to start properly after upgrading to the latest version of the Lattice Diamond software?
|Can I implement Error Check Codes in the Embedded Block Ram (EBR) based memory modules?
|How do I connect the signal "clk_s" in the GDDRX2(X4)_RX(TX).ECLK module for MACHXO2 device?
|How can I access the User Flash Memory(UFM) of MACHXO2 device?
||1409||MachXO2||Hardware||Architecture||User Flash Memory (UFM)|
|What's the difference between the Primary I2C IP core and the Secondary I2C IP core?
|What's the function of the Bandgap of MACHXO2 device family?
|How can I implement multiple Power Manager II devices on a board?||1406||All Power Management||Hardware||Architecture||Power Sequence|
|5V will be supplied to a Power Manager VMON input before Vccd and Vcca are powered up. Is there any problem?||1403||Power Manager II||Hardware||Architecture||IO|
|Do you have any examples of logging power supply faults?||1402||All Power Management||IP/Reference Designs||Lattice IP/Reference Designs||Closed-loop Trim/Fault Logger|
|How can the Platform Manager be used to implement a digitally controlled power supply?||1401||Platform Manager||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|What is Hot Swap? And how does a Power Manager device do it?||1400||Power Manager II||IP/Reference Designs||Lattice IP/Reference Designs||5V/3.3V Hot Swap Controller|
|How does the POWR1220AT8 control a 12V hot swap MOSFET when the maximum HVOUT voltage is 12V?||1399||Power Manager II||Hardware||Lattice Evaluation Board||Hercules-Standard|
|Is there an evaluation board for the POWR6AT6?||1398||Power Manager II||Hardware||Lattice Evaluation Board||Processor PM Dev Kit|
|How can the POWR1220AT8 be used to implement a digitally controlled power supply?||1397||Power Manager II||Hardware||Lattice Evaluation Board||Hercules-Standard|
|How do I reprogram the Platform Manager evaluation board with the original demo design?||1396||Platform Manager||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|If I connect the POWR6AT6 Trim-DAC output to the feedback node, won't that cause the DC-to-DC converter to become unstable?||1395||Power Manager II||Hardware||Architecture||IO|
|Is there an evaluation board for the Platform Manager device?||1394||Platform Manager||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|Why does ispVM System show an unknown part and a MachXO 640 when scanning the Platform Manager evaluation?||1393||Platform Manager||Software||Device Programming||ispVM System|
|I get errors in ispVM when I connect the Platform Manager evaluation board to my computer and try to scan the chain. What is wrong?||1391||Platform Manager||Software||Device Programming||ispVM System|
|If I connect the Platform Manager Trim-DAC output to the feedback node, won't that cause the DC-to-DC converter to become unstable?||1389||Platform Manager||Hardware||Architecture||IO|
|What speeds do the I2C port of MachXO2 device family support?
|How many times can Lattice devices withstand reflow oven or wave soldering ?||1385||All Devices||Hardware||Reliability and Materials||Reliability|
|How can I find weight to size ratio of your devices?
||1384||All Devices||Hardware||Reliability and Materials||Device Materials|
|How can the VID lookup table in the Closed-loop Trim/Fault Logger IP be used for power supplies with different outputs?||1379||Platform Manager||IP/Reference Designs||Lattice IP/Reference Designs||Closed-loop Trim/Fault Logger|
In LatticeECP2/M and LatticeECP3 device families,
what are the states of HDOUT pins during power down mode and power up mode?
Do the Platform Manager products contain more than one silicon die?
|1372||Platform Manager||Hardware||Architecture||General Logic|
|Is it possible to use a ispPAC-POWR1014 or ispPAC-POWR1220 for -48V hot-swap applications?||1368||All Power Management||Hardware||Customer Board Design||Schematic|
|How do I calculate the power consumption of a Power Manager device?||1366||All Power Management||Hardware||Architecture||Power|
When using revision control in Diamond software, how to archive project files with minimum hard disk space usage?
|1365||Other FPGA||Software||Implementation||Project Navigator|
How do I wire up VMONGS lines for the Power Manager II?
|1360||Power Manager II||Hardware||Customer Board Design||Layout|
|Does the Platform Manager have internal flash memory I can access to store voltage readings, faults or other data?||1358||Platform Manager||IP/Reference Designs||Lattice IP/Reference Designs||SPI4.2|
Does the Platform Manager support I2C?
|What are the UES bits used for in the Platform Manager?||1354||Platform Manager||Hardware||Device Programming||ispVM System|
Are the clocks in Platform Manager connected internally?
|1353||Platform Manager||Hardware||Architecture||PLL/DLL/Clock Routing|
|What is the difference between CTimer and the FTimer in the Platform Manager device family?||1352||Platform Manager||Hardware||Architecture||PLL/DLL/Clock Routing|
How many timers can I build in a Platform Manager LPTM10-12107?
|1346||Platform Manager||Hardware||Architecture||Power Sequence|
|What are the differences between the ispPAC-CLK5610V-01T48I and the ispPAC-CLK5610AV-01TN48I?||1343||ispClock 5600A||Hardware||Architecture||PLL/DLL/Clock Routing|
|How does the clock input for an ispPAC- POWR1014/1220 appear electrically when the device is unpowered?||1342||Power Manager II||Hardware||Architecture||Power Sequence|
|Does the Analog-Digital Converter (ADC) feature on a Power Manager have an internal averaging or filtering circuit?||1341||All Power Management||Hardware||Architecture||Power Sequence|
|How does VMON threshold accuracy for Power Manager Devices vary over temperature?||1340||All Power Management||Hardware||Architecture||Power|
|What is the maximum junction temperature for the ISPPAC-POWR1014?||1339||Power Manager II||Hardware||Reliability and Materials||Reliability|
|Is it okay to use the ISPPAC-POWR607's PWRDN input for a logic input if I am not using the device's power down features?||1338||Power Manager II||Hardware||Architecture||Power|
|Using Lattice Diamond software, how do you LOCATE a PCS/SERDES QUAD?||1337||All FPGA||Software||Implementation||Design Planner|
|Can LatticeECP3 FPGA PLLs accept Spread Spectrum Input clock?
|Can the PLL's LOCK output be used to detect when the PLL's input clock CLKI stops?
||1331||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|How is the Clock Injection Delay removal function of the DLL supported for simulation?
|Is it possible to implement two full X4 PCIe endpoints in one device?
I am interested in a non transparent bridge application...
|If I select the re-loadable coefficient option for FIR IP, would I be able to change the number of coefficient for each load?
||1325||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||FIR Filter Generator|
|Is there an input signal that will tell the Viterbi decoder that a new input sample is available on the bus?
||1324||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Block Viterbi Decoder|
|Is PROGRAMN pin independent of JTAG programming operations?
|For the LatticeXP2 device, which supply should the CFG and TOE pins be pulled up to?
|What is the "Repetitive Download" tool in ispVM System software used for?
||1319||All Devices||Software||Device Programming||ispVM System|
|Why does the boundary scan device give LOOP 100 syntax error with an SVF file ?||1307||All Devices||Software||Device Programming||ispVM System|
|Why does ispVM fail on DIRECT_FLASH_ERASE?||1305||All Devices||Hardware||Device Programming||Configuration/Programming|
|How can I get ispVM to recognize the USB cable?||1304||All Devices||Hardware||Device Programming||ispVM System|
|What input buffer preference settings should be used for PCIe Reference Clock termination?
||1303||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|What Transaction Layer Packets (TLPs) header format is used for 64 bit addressing?||1301||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|What is the throughput of the PCIe SGDMA reference design?
||1300||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Can I access PCIe Extended Capability registers via a Windows driver?
||1298||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Can I access PCIe Extended Capability registers via a Linux driver?
||1297||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?
||1296||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Does Lattice provide TCP/IP network stack support for the TSMAC and Mico32?||1295||All FPGA||Software||Implementation||Mico32(MSB)|
|What link rates are supported by the Lattice Serial RapidIO (SRIO) IP core in LatticeECP3?||1294||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||Serial RapidIO|
|How can I see what addresses my functions/variables have been mapped to? How can I get a memory map report?
How can I use Reveal along with Mico32 MSB to debug my system?
Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?
Why do I have only 5 or 6preamble bytes coming out of my Gigabit Ethernet(GbE) IP core, which assertsthe RX_ER signals in the SGMII MAC core, even though I \u2018m sending in 7 preamblebytes?
|1285||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||SGMII and Gb Ethernet PCS|
|What is the maximum potential skew between the transmit data bus bits on the SC/M in a SPI4.2 IP core?
||1282||LatticeSC/M||IP/Reference Designs||Lattice IP/Reference Designs||SPI4.2|
|Why do I receive the error message "Could not connect to JTAGServer" from TCP2JTAGVC2?||1277||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|What is the project pre-loaded in the LatticeMico32 ECP2 or ECP Evaluation Board?||1276||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Can the LatticeMico32 System Builder software be installed without installing ispLever or Lattice Diamond?||1275||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Do the LatticeMico32 System Builder tools run in Microsoft Windows Vista?||1274||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|How can I generate an Intel Hex, or an SREC file from the LatticeMico32 ELF file?||1273||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|How do I reestablish access to the LatticeMico32 debugger without rebooting?||1272||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|How do I determine why CFIFlashProgrammer fails to program my parallel flash memory?||1271||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|What are the mechanical dimensions of the LatticeMico32 Evalution Board expansion header?
||1268||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Is there any non-volatile setting provided by the LatticeECP2/M to set permanent pull-up resistors on the I/O pins before the device is programmed?||1265||LatticeECP2/M||Hardware||Architecture||Configuration/Programming|
|Can the PROGRAMN pin be held low for a period of time on power-up to prevent the FPGA from configuring?
||1263||All FPGA||Hardware||Device Programming||Configuration/Programming|
|Is the LatticeECP3 configuration bitstream for SPI flash fixed size regardless the design?
|What can I do to reduce the VME file size if the flash is too small?||1260||All Devices||Hardware||Device Programming||ispVM Embedded|
|How many times FLASHBAK can be done in the LatticeXP2 without causing reliability issue?||1259||LatticeXP2||Hardware||Device Programming||Configuration/Programming|
|I updated my LatticeMico32 project after installing ispLEVER 8.1SP1 and now it doesn't work. What happened to my platform and how do I get it to work again?
||1258||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Does the LatticeSC PLL require a reset if the PLL lost lock?
|Can Reveal analyzer tool run standalone after setting the trigger and disconnecting it with the Analyzer software, and if a trigger occurs later, then reconnect it to the Analyzer software to download the captured data for further analysis?
|How to locate DCS in preference file for FPGA?||1255||All FPGA||Software||Implementation||Block Modular Design|
|How to define different VCCIO voltage in different IO bank for FPGA such as SC/ECP2/ECP2M/ECP3 devices? Why is it necessary?
|Why don't ORCAstra modules generated by IPExpress contain JTAG I/O ports?||1253||All Devices||Hardware||Architecture||JTAG|
|Can I use paralllel port interface or other older interface with the ORCAstra module generated from the IPexpress?
||1252||All Devices||Hardware||Device Programming||Configuration/Programming|
|What do I do if my design with multiple clocks and clock domain transfer does not meet timing anymore?
||1250||All Devices||Software||Implementation||Timing Closure|
|How do I initialize ORCALUT via Synthesis?
|Why doesn't Synthesis retain proper hierarchy/instance names in the EDIF netlist?
|My current design under simulation is in VHDL which uses a Verilog module (Lattice Tri-speed MAC) in which a ipExpress generated PLL (another Verilog module) is used.
The ipExpress generated Verilog module contains several defparam specifications to set the EHXPLLA parameters.
Using Active-HDL (ispLever 7.1) the Verilog compiles without problems.
But during elaboration before the simulation starts I get a fatal error:
ELAB2: Fatal Error: ELAB2_0093 The defparam statement from module "rxmac_clk_pll" in "/TSMAC/U1_rxmac_clk_pll" points to variable "SMI_OFFSET" in a non-Verilog design region "/TSMAC/U1_rxmac_clk_pll/rxmac_clk_pll_0_0".
What is wrong here, and how can this be fixed?
|How do I use Active-HDL Lattice Edition in GUI Mode?||1244||All Devices||Software||Simulation||Aldec|
|How do I use Active-HDL Lattice Edition in batch mode?||1243||All Devices||Software||Simulation||Aldec|
What does "Fatal : Obsolete library format for design unit" Modelsim error mean?
|Why doesn't my waveform refresh automatically in Active-HDL GUI?
|Why doesn't my Active-HDL Aldec license server start automatically at boot time?||1240||All Devices||Software||Simulation||Aldec|
|Why do I get "invalid hex parity digit" errors with ispLever / Diamond bitgen?
||1239||All FPGA||Software||Implementation||Bitstream/JEDEC Generation|
|Why can't I launch Design Planner?||1238||All Devices||Software||Implementation||Design Planner|
|Why does ispLever issue warning for a design with EBR in ASYNC Reset mode?
|How fast can the LatticeSCM SPI4.2 MACO core run in a given speed grade?
||1232||LatticeSC/M||Hardware||Architecture||ASIC Block (MACO)|
|In my SPI4.2 MACO core, the rxs4err error randomly asserts during operation but my packets are fine. What could be the problem?
||1231||LatticeSC/M||Hardware||Architecture||ASIC Block (MACO)|
|Why is the uML used in the SCM PCIe solution?||1230||LatticeSC/M||Hardware||Architecture||ASIC Block (MACO)|
|Are there any reference designs customers can look at to get a quick start on their PCIe designs?
||1229||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Does the SPI4.2 interface support Hot-Socketing?
||1228||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SPI4.2|
|Can the PWRSAVE feature be used with LVDS I/O?
|I get an ispVM "JTAG-NOP" error with ispVM. What could be the cause?
||1226||All Devices||Hardware||Device Programming||ispVM System|
|Does the LatticeSCM device support Read/Write (R/W) access to the Embedded Block RAMs (EBRs) from the system bus?
|How can I suppress ActiveHDL False Alarm regarding "Undefined Library Modules"?
|Why does Modelsim fail with the error message:"# ** Error: (vsim-3170) Could not find './work.StimModule_Unknown'."?
|Why do I get the following Aldec Active-HDL error?: "# ELAB2: Fatal Error: ELAB2_0036 Unresolved hierarchical reference to...". It also refers to a PUR_INST in the error message.
|Why can't I run FPGA simulations after installing ActiveHDL Lattice Web Edition?
|How can I compile Lattice primitive libs for simulation?||1201||All Devices||Software||Simulation||NC-Verilog|
|How can I recompile my testbench without restarting ActiveHDL from ispLEVER tool?
|What ActiveHDL commands can I issue from the command line?
|Why can't ActiveHDL find the PCS *.txt file after a restart? ECP2M simulations doesn't work after the initial simulation.
|How to show signal hierarchy in the ActiveHDL Waveform Editor?
(I want to see the design hierarchy of a given signal.)
|How can I make the Aldec ActiveHDL Waveform Viewer zoom in enough to see the details of my simulation?||1195||All Devices||Software||Simulation||Aldec|
|How to resolve Aldec Node-Locked License Issue ?||1194||All Devices||Software||Licensing||ispLEVER|
|Where can I look up known ispLEVER software issues?||1192||All Devices||Software||Installation||Win-All|
|What on-chip debug tools are available for Lattice FPGA's?||1191||All Devices||Software||Debugging||Reveal|
|Why won't IPexpress connect to the Lattice IP Server?
It spins for a while then stops with "Connection Failed" dialog box.
|Does the XAUI LSM in the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS constantly monitor the 10-bit word alignment? Does it self correct if the link goes down momentarily?
Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?
|While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?||1180||All FPGA||Hardware||Architecture||SERDES/PCS|
|When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?||1179||All FPGA||Hardware||Architecture||SERDES/PCS|
|Can I create an 8-lane XAUI bus using 2 LatticeSC/M flexiPCS in XAUI mode?
|In Fiber Channel mode, is the LatticeSC/M flexiPCS compliant to all ANSI FC standard ordered sets? not just IDLEs for rate matching?||1174||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|Can I change the LatticeSC/M flexiPCS to support both 10 GbE or 4 x 1 GbE using the PCS register set?||1173||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|For the LaticeSC/M flexiPCS, when are lsm_status_[0-3] signals and Quad Interface Register (QIR) h84 (Link Status bits) Valid?||1172||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|Is it possible to reverse SERDES XAUI lanes on a LatticeSC/M flexiPCS?
|Is there a signal or indicator in the LatticeSC/M flexiPCS, that can be used to know if the XAUI PCS has completed configuration and is ready for passing traffic?
|With the LatticeSC/M flexiPCS in XAUI mode, why is the mca_aligned=0 when lsm_status_[0-3]="1111"?
|In the LatticeSC/M flexiPCS, what leads to mca_aligned going high (proper muli-channel alignment achieved)?
|What are the FPGA Interface clock frequencies for a LatticeSC/M flexiPCS in 1GbE mode with a 125 MHZ reference clock?||1166||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|With the LatticeSC/M flexiPCS in generic 8b10b mode, why do some far end loopbacks not work when I connect the SERDES HDIN* to a Smartbits 1 GbE data generator?
|In LatticeSC/M flexiPCS, is there a signal to indicate when Commas (K28.5) are received?
|Why do I see (rxd_[3:0]=hFE,rxc_[3:0]=1) or (rxd_0=h9C,rxc_0=1) on the LatticeSC/M flexiPCS RX data in XAUI mode?||1163||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|Upon a CDR Loss of Lock event on the LatticeSC/M flexiPCS in 8b10b mode, do I need to monitor both mca_aligned* and lsm_status* to issue an rx_rst?||1162||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
|In a LatticeSC/M flexiPCS, which resets should be used? When can I use the quad_rst and serdes_rst signals?
|Does the Linux version of ispVM System support the Lattice USB Download cable?||1160||All Devices||Software||Device Programming||Cables|
|Can ispVM System program ispClock or ispPAC-POWR products?||1159||All Mixed Signal||Software||Device Programming||Configuration/Programming|
|Can I receive LVDS signals in I/O bank whose VCCIO is assigned to 3.3 volts?
||1158||All FPGA||Hardware||Customer Board Design||Schematic|
|How many PLLs can use the PLLCAP on the LatticeECP2M FPGA?
|How can I specify what type of PLL is used for a LatticeECP2/M FPGA?
|Why won't the second PLL in a cascaded PLL design achieve lock during simulation?||1155||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?
|1154||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|Will Lattice FPGA's allow me to drive primary clock signal also drive on the edge clock?||1152||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
What is the best way to divide a clock by 2 in Lattice devices?
|1151||All Devices||Hardware||Architecture||PLL/DLL/Clock Routing|
|What does the M or Minimum Speed grade mean in a Lattice I/O timing report?
||1150||All Devices||Software||Implementation||Timing Analysis|
|Why do I get warnings in the automake.log file regarding "Combinational Loops found"?
|Why can't I run mixed language synthesis in ispLEVER 7.1 SP1 or 8.0 or 8.0 SP1?
|Why does Lattice ispLEVER not recognize that ALDEC Active-HDL is installed?||1147||All Devices||Software||Simulation||Aldec|
|What causes the ispLEVER message: "ERROR: Can not read design entry type from Context" ?
||1146||All Devices||Software||Installation||Win Vista|
|Why do I get the error "license file checkout fails" when I start ispLEVER?
|How do I convert a raw *.rbt file to bit *.bit file or vice versa?
||1144||All Devices||Software||Device Programming||Configuration/Programming|
|How to generate a LatticeXP and LatticeXP2 device bit file for EPROM programming?||1142||LatticeXP2||Software||Device Programming||Configuration/Programming|
|Can I use dummy bits in the ECP3 bitstream header for custom data such as rev ID?
|How to find the weight of a device, such as a SC 1152 pin package?
|How to compile and link the Mico32 executable code to be either position-independent or relocatable?
||1138||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
When replacing an expired ispLEVER license file, how do I clear the FlexLM licensing environment variable in Windows registry?
|How many additional clocks are required after the bitstream is sent in the slave configuration modes?||1129||All Devices||Hardware||Device Programming||Configuration/Programming|
|Some Lattice device datasheets list a specification for "Additional Master Wakeup Clocks". Is this also a requirement for slave configuration modes?
||1127||All Devices||Software||Device Programming||Configuration/Programming|
Why will a bitstream encrypted LatticeECP2/M "S" device configure using JTAG, but not by other methods of programming?
|There are some Flash devices listed in ispVM System as 'Beta'. What does this mean?
||1123||All Devices||Software||Device Programming||ispVM System|
|What is a VME file?||1121||All Devices||Software||Device Programming||ispVM Embedded|
|What needs to be modified in ispVM Embedded to target my embedded system?
||1120||All Devices||Software||Device Programming||ispVM Embedded|
|What is the maximum rise/fall time for inputs on I/O or clock pins?
|Some Lattice datasheets list I/O specifications that include a VOL/VOH entry as +/-0.1mA (100uA). What does this mean?
|Why does TRACE timing analysis report against frequency preference when I haven't specified one?
||1113||All Devices||Software||Implementation||Timing Analysis|
|During functional simulation, why does the LatticeMachXO TSALL component not tristate all outputs?
|Why can I run only Project Navigator in the Linux or Unix versions of ispLEVER from the command-line? Why will no other commands work from the command line?||1110||All Devices||Software||Installation||ispVM System-Linux|
|What is an .lpc file?||1109||All Devices||Software||Implementation||IPExpress|
|License checkout failed, but I entered everything correctly. What's wrong?||1108||All Devices||Software||Licensing||Lattice Diamond|
|My obsolete device is not supported by ispLEVER Classic. What can I do?||1107||All CPLD||Software||Licensing||ispDesignEXPERT|
|Where can I find the moisture sensitivity level (MSL) of a given device?
||1105||All Devices||Hardware||Reliability and Materials||Reliability|
|Lattice SERDES pins and PCIe lanes||1102||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Why do some PCIe slots run slower than others?
||1101||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|How can I use the complimentary outputs in Lattice FPGAs?
|How to create a FPGA pinout that will work on the board?
||1099||All FPGA||Software||Implementation||IO Assistant|
|What is the differences between the DOUT and QOUT pins used with LatticeSC/M daisy-chaining.||1098||LatticeSC/M||Hardware||Device Programming||Configuration/Programming|
|What are the limitations of thevenin terminations for LatticeSC/M devices?||1091||LatticeSC/M||Hardware||Architecture||IO|
|What are the Hot Socket capabilities of LatticeECP2M, LatticeECP3, and LatticeSC/M SERDES I/O?
|What is a best practice for looking at SERDES CML outputs?||1088||All FPGA||Hardware||Architecture||SERDES/PCS|
|Is ac-coupling ok to use in your application?
|What considerations must be taken with VCCIO Bank power supply connections in LatticeSC/M?||1084||LatticeSC/M||Hardware||Customer Board Design||Board Debug|
|What should VTT pins on the LatticeSC/M devices be connected to if the design is NOT using HSTL/SSTL type I/O?||1083||LatticeSC/M||Hardware||Customer Board Design||Schematic|
|What are the power supply requirements for LVDS inputs for LatticeSC/M devices?
||1079||LatticeSC/M||Hardware||Customer Board Design||Schematic|
|What is required Solder reflow condition for DIP packages? TN1076 only discusses surface mount packages.||1072||All Devices||Hardware||Reliability and Materials||Device Materials|
|Does XP2 support encrypted bitstreams?||1069||LatticeXP2||Software||Device Programming||Configuration/Programming|
|How can I configure the MCCLK_FREQ for the LatticeXP2 family in the software?||1068||LatticeXP2||Software||Implementation||Design Planner|
|What are the hardware default settings of the ECP2/M sysCONFIG ports?||1066||LatticeECP2/M||Hardware||Architecture||Configuration/Programming|
|How many seondary clocks are supported per region of ECP2/XP2 devices?||1063||LatticeECP2||Hardware||Architecture||PLL/DLL/Clock Routing|
How to set LatticeECP3 FPGA IO in temporary tri-state when another partner device in line card doesn't support hot swap?
|Why does my simulation show the output clock phase constantly shifting with respect to the input clock in a PLL?
|How do I change the type of memory resources Synplify uses when using inferred memory in HDL code?
|How do I instantiate multiple Reveal cores into a design?
|What is the "BLOCK INTERCLOCKDOMAIN PATH" preference used for?
||1046||All Devices||Software||Implementation||Constraint-Pref Editor|
|Where can I find the change log and a list of new features in a new software release?
||1044||All Devices||Literature||Inquiries||Help Files|
|How do I manually update ispLEVER and Diamond software?
|Can I use a USB to parallel port adapter with my parallel port ispDOWNLOAD cable?||1040||All Devices||Hardware||Device Programming||Cables|
|Are there any limitations with ispLEVER Starter and service packs?||1039||All Devices||Software||Licensing||ispLEVER|
|Why does my LatticeMico32 debug session fail to launch?||1037||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Why can't I open EPIC on a design that uses an IPCore that was downloaded from Lattice's website?
|Can I run ispLEVER in 64-bit Windows 7 or 64-bit Windows Vista?
||1031||All Devices||Software||Installation||ispVM System-Win 7|
|How can I run ispLEVER tools on Windows 7 32-bit versions?||1030||All Devices||Software||Installation||Win 7|
|How do I use LatticeMico32 System Builder with multiple Cygwin installations?||1029||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|When I launch LatticeMico32 System Builder I'm asked to provide a location for the workspace. What is the workspace and how do I use it in Mico System Builder?||1027||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|What do I need to do to migrate from LatticeMico8 V2.4 to V3.1?||1024||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|How do I use the .data directive in the LatticeMico8 assembler?||1023||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|What is the LatticeMico32 Interrupt Latency?||1022||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|How do I install the driver for the Lattice Semiconductor USB cable under Windows Vista?||1017||All Devices||Software||Installation||ispVM System-Win Vista|
|Does the PCS0 in the main window of ORCAstra represent PCSA?
|Will all speed grades of the LatticeECP2/M and LatticeECP3 support the SerDes at 3.125 Gbps?
|Does each quadrant of the device have equal logic resources?||1011||All FPGA||Hardware||Architecture||SERDES/PCS|
|When will a new feature or function be implemented in LatticeMico32?||1009||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Can I bypass the FPGA Bridge FIFO in the LatticeECP2/M PCS block?||1008||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|How can I set tx-to-rx serial internal loopback without using ORCAstra in ECP2M PCS?
How to prevent the HDOUTP/N from sending out the pattern when ffc_quad_rst is asserted?
|In TN1176, it says VCCA of unused quad should be powered up. What is the reason to power up unused quad? Can I save power by leave the VCCA floating?||1005||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|In LatticeECP3 SerDes/PCS, there are 4 txfullclks in a quad. Can I use just one txfullclk for all 4 channels in FPGA core?||1004||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|What is the clock frequency of the rx_full_clk_ch# from the SERDES PCS when there is no valid data being received?||1003||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|How do I lock the serdes pins on device? There is no pin-lock capability in designer planner. The pins are grayed out.||1001||All FPGA||Hardware||Architecture||SERDES/PCS|
|How can I implement multiple protocols within a PCS quad (Protocol A RX, Protocol B, TX, etc) on ECP2M and ECP3?||1000||All FPGA||Hardware||Architecture||SERDES/PCS|
|Where do I find pin function and placement information for my programmable device package?||999||All Devices||Literature||Inquiries||Datasheet|
|I need to connect an optical module to LatticeECP2/M SERDES. Can you provide an example interface circuit?||998||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?||991||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|Are there any pins that can't be used when the SERDES is being used?
|What are the possible delay variations expected with the transmit and receive SERDES?
|How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML input)?
|What's the typical rise time for the LatticeSC SERDES reference clock(external CML input pin)?||987||LatticeSC/M||Hardware||Architecture||SERDES/PCS|
Can a SERDES recover clk(such as rxa_pclk or rxb_pclk or rx#_sclk in LatticeSC) be used to drive general purpose FPGA logic?
|What is the SERDES channel to channel transmit skew for the LatticeSC?
|The Lattice SC/M data sheet (DS1005) refers Fibre Channel users to the XAUI section of the data sheet. What is the relationship between Fibre Channel and XAUI modes of operation in the Lattice SC/M devices?
Why does the GbE PCS link state machine status signal regularly pulse low eventhough the SERDES/PCS receives valid 8b10b encoded characters?
|Can I manually modify a LatticeECP2M PCS autoconfig file instead of going through the IPexpress PCS generation flow?
|Can I set the rate mode (half or full) differently between TX and RX on the same LatticeECP2M SERDES/PCS QUAD channel?
|In LatticeSC/M IPexpress GUI for System Bus, why is the usr_clk input absent when MPI is enabled?
|For LatticeSC/M, when do I select "User Master Sync to Systembus Clock" in the System Bus IPexpress User_Master tab?
|What is the state of Flip Flop outputs at power-up? The reset pins of my design registers are tied to neither GSR nor LSR
||975||All FPGA||Hardware||Architecture||General Logic|
|Can the ispVM tool control the TCK duty cycle and/or frequency?
||974||All FPGA||Hardware||Device Programming||ispVM System|
|Does ispVM Embedded support the Lattice device I am using?
||973||All FPGA||Hardware||Device Programming||ispVM Embedded|
|How is the FIXEDDELAY attribute used and implemented in Single Data Rate (SDR) mode in a LatticeECP3 device?||972||LatticeECP3||Hardware||Architecture||IO|
|How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device?
|Does the LatticeSC/M Ethernet FlexiMAC IP report CRC errors on a frame after it removes data padding?||969||LatticeSC/M||IP/Reference Designs||Lattice MACO Cores||Ethernet 1/10 Gigabit FlexiMAC|
|Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?
|Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?
||967||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SGMII and Gb Ethernet PCS|
|What happens to the existing packet whent the TX Etherne Fleximac underruns?
||966||LatticeSC/M||IP/Reference Designs||Lattice MACO Cores||Ethernet 1/10 Gigabit FlexiMAC|
|How does the TSMAC handle a VLAN Q-in-Q (IEEE 802.1ad Double-Tagged) frame?
||964||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Tri-Speed Ethernet MAC|
|How does the Ethernet flexiMAC deal with a Length/Type field that is smaller than Data payload size?
||963||LatticeSC/M||IP/Reference Designs||Lattice MACO Cores||Ethernet 1/10 Gigabit FlexiMAC|
|In the existing reference design for LatticeSC/M 10 GbE flexiMAC IP, can I simulate the core and EBRs without flexiPCS?||962||LatticeSC/M||IP/Reference Designs||Lattice MACO Cores||Ethernet 1/10 Gigabit FlexiMAC|
|In IPUG48 (LatticeSCM Ethernet FLexiMAC USER GUIDE) what does the rb_flt_stt bus mean exactly?||961||LatticeSC/M||IP/Reference Designs||Lattice MACO Cores||Ethernet 1/10 Gigabit FlexiMAC|
|Can I generate the MICO32 source code in VHDL?
||959||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Why can't I deploy LatticeMico32 code to a non-volatile memory with the JTAG UART active?
||958||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|How do I modify the memory CAS latency value when using LatticeMico32 with a DDR SDRAM memory controller IP?
||957||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||LatticeMico32|
|Why do I get Synopsys VCS simulator errors related to GSR/PUR ?||956||All Devices||Software||Simulation||Synopsys (VCS)|
|Why won't Lattice software recognize "ES" type devices in a Project File?||954||All Devices||Software||Implementation||Project Navigator|
Why does Map report errors about inputs connecting to both PAD and non PAD loads?
|What is the difference between a .bit file and a .jed file?||952||All Devices||Software||Device Programming||Configuration/Programming|
|Can a non encrypted Bit file be programmed into the LatticeECP2/M S series devices with a encryption key?||951||LatticeECP2/M||Software||Device Programming||Configuration/Programming|
|What is the detailed power up sequence for a MachXO device?
|What is the difference between an ispGAL and a GAL device?
|Where can I find old versions of ispVM System?||948||All Devices||Software||Device Programming||ispVM System|
|Can I emulate open drain IOs in simulations?||947||All Devices||Software||Simulation||Aldec|
|How do I use the ispMach4000 global clocks?||943||ispMACH 4000||Hardware||Architecture||PLL/DLL/Clock Routing|
|Why does the hold analysis use a different speed grade?||941||All FPGA||Software||Implementation||Timing Analysis|
|Why are there two trace reports in the Lattice software?
||940||All Devices||Software||Implementation||Timing Analysis|
|What is the I/O Timing Report?
||938||All Devices||Software||Implementation||Timing Analysis|
|Where can I find RTL coding examples?
|How do I define the skew of a registered bus to IOs?
||931||All Devices||Software||Implementation||Timing Analysis|
|I am an experienced FPGA designer but new to Lattice. Is there any documentation to get me started?
||930||All Devices||Literature||Inquiries||Help Files|
|What is Auto hold-time correction setting in PAR?
|How can I determine what clock resources are being used?||928||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|What is the origin of my device?
||926||All Devices||Hardware||Reliability and Materials||Device Materials|
|How can I determine if I have an authentic Lattice device?||924||All Devices||Hardware||Reliability and Materials||Reliability|
|Where can I find the mechanical drawing for a device?||923||All Devices||Hardware||Customer Board Design||Layout|
|What is the pin composition?
||922||All Devices||Hardware||Reliability and Materials||Device Materials|
|How can I determine if there is a lead free package option for a device?||921||All Devices||Hardware||Reliability and Materials||Device Materials|
|How can I confirm a device part number?
|What is the FIT rate for a device?
||918||All Devices||Hardware||Reliability and Materials||Reliability|
|How can I find out if the device I am currently using is still in production?||916||All Devices||Hardware||Reliability and Materials||Lifetime|
|Why is there a limit on the number of 5V tolerant IOs in the ispMACH 4000 devices?
|How many generic routing signals can be used as primary clocks in a LatticeECP2/M device?
|How is the configuration file (.txt) generated by IPexpress being used?
|How can I create a schematic symbol for a bus in an ABEL module?
|What's the best way to place and route a very congested design?
|Where can I get an example HDL module that sets up the SERDES?||898||LatticeECP2/M||Literature||Inquiries||Appnote/Technote|
|Can a ECP2 dual boot application be set up to load the golden bitstream rather than the primary?
|Can the LatticeXP2 UES be accessed using IOs instead of the JTAG port?||896||LatticeXP2||Literature||Inquiries||Appnote/Technote|
|What is the unprogrammed state of an IO?||895||All Devices||Literature||Inquiries||Datasheet|
|Can ispVM be run on the Vista64 or XP64 O/S?||894||All Devices||Software||Device Programming||ispVM System|
|ispVM offers device part number selections with "AS" or "ES" suffixes, what do the suffixes mean?
||892||All Devices||Software||Device Programming||ispVM System|
|Should I connect all the JTAG signals on the ispDOWNLOAD cable to my evaluation board?||891||All Devices||Hardware||Device Programming||Cables|
|Will my design need to supply power to the JTAG VCC connection on the download cable?
||890||All Devices||Hardware||Device Programming||Cables|
|Why doesn't ispVM verify another vendor's STAPL programming file?||889||All Devices||Software||Device Programming||ispVM System|
|Is there an easy way to compare two BIT or JED files?
||888||All Devices||Software||Device Programming||ispVM System|
|What does an output IO look like electrically?
|What is the typical pullup or pulldown resistance value for an IO?||886||All Devices||Literature||Inquiries||Datasheet|
|How do I set up the VREF pins for use with the IOs using ispLever?
||885||All Devices||Software||Implementation||Design Planner|
|Can I change the emulated LVDS resistor network to get other output voltage levels?||883||All FPGA||Literature||Inquiries||Datasheet|
|How can I estimate the BLVDS SSO?||882||All FPGA||Software||Implementation||SSO Analysis|
|The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2?
Do I need a heat sink on the Lattice device and if so, what size?
|Once I set up my PLL dividers to a specific frequency, can I change the input frequency and still achieve lock?||875||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|My device doesn't have a PLL, or enough PLLs, what are my options?||874||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|What types of issues could cause the PLL to lose lock?||873||All Devices||Hardware||Architecture||PLL/DLL/Clock Routing|
|When should I specify primary clock, secondary clock, or edge clock rather than use general routing?
|Why are the number of EBR blocks used more than I calculate for a True DPRAM?
|Does ispLever use lock files on Linux?||863||All FPGA||Literature||Inquiries||Appnote/Technote|
|Why does ispLever licensing fail with a MAC ID of 00-53-45-00-00-00 ?||862||All FPGA||Software||Licensing||ispLEVER|
|My PC died, can I get a replacement license for my new PC?
|I have older Lattice design software, can I install it on my new PC?
|Can I use the available spare IOs to help lower SSO noise?||854||All Devices||Hardware||Customer Board Design||Schematic|
|Should I isolate the chassis GND connections on my high speed connectors from the PCB GND?||849||All Devices||Literature||Inquiries||Appnote/Technote|
|Do I need to add a large value capacitor to the load side of a ferrite bead?
||847||All Devices||Hardware||Customer Board Design||Schematic|
|My application requires rad hard packaging, what are my options?
|My design includes mature devices, how long will they be available?||845||All Devices||Literature||Inquiries||PCN|
|What can I do to maximize the emulated LVDS data rate?
|Does Lattice do Machine Model ESD testing?
|What technology type is used for a specific Lattice device?||838||All Devices||Hardware||Reliability and Materials||Reliability|
|Can the Lattice Applications group review our schematics and layout designs before we fabricate the PCBs?
||837||All Devices||Hardware||Customer Board Design||Schematic Review|
How can I control the location of an LatticeECP2M PCS block?
|How can I implement multiple POWR1220AT8 Power Manager devices on a board?||832||Power Manager II||Hardware||Customer Board Design||Schematic|
|How do I convert my Logi-Builder design code to ABEL?||831||All Power Management||Software||PAC-Designer||ABEL|
|What is the best way to get started on using Lattice PAC-Designer Mixed Signal Software?||830||All Power Management||Software||PAC-Designer||LogiBuilder|
|How many I2C loads can I put on an I2C chain with Power Manager devices?
||829||All Power Management||Hardware||Architecture||I2C|
|Can I buy factory programmed parts? Can the Power Managers be programmed by the factory, what other options are there?
||827||All Power Management||Hardware||Device Programming||Engineering Kits|
|What is different about the ProcessorPM-POWR605 relative to the other Power Manager devices from Lattice?
||826||All Power Management||Hardware||Architecture||Power Sequence|
|How do I design the code for a PM605?||825||All Power Management||Hardware||Device Programming||PAC-Designer|
|What can the user do with the I2C interface on the Power Manager II devices?||820||All Power Management||Hardware||Architecture||I2C|
|How can I create a 10 second timer in an ispPAC-POWR1220AT8 device?||819||Power Manager II||Hardware||Architecture||General Logic|
|Why doesn't PAC-Designer show Frequencies for PLL-Bypass mode?||818||ispClock 5600A||Software||PAC-Designer||Schematic|
|Why are some of the ispClock5600A outputs occasionally 180 degrees out of phase from the reference input clock?||817||ispClock 5600A||Hardware||Architecture||IO|
|How can I get an Evaluation Board for the ispClock5620A and ispClock5610A?
||816||ispClock 5600A||Hardware||Lattice Evaluation Board||ispClock 5620A|
|Which members of the ispClock5300S family are available on an evaluation board?
||815||All ispClock||Hardware||Lattice Evaluation Board||ispClock 5312S|
|When should I bypass M & N in the ispClock5620A or ispClock5610A and why ?||814||ispClock 5600A||Hardware||Architecture||PLL/DLL/Clock Routing|
|How can I use a low-cost CMOS oscillator with ispClock 5400D devices?
||813||All ispClock||Hardware||Customer Board Design||Schematic|
|What is the significance of Power-Off Detection in a Power Manager device?
||806||All Power Management||Hardware||Architecture||Power Sequence|
|If I connect the POWR1220AT8 Trim-DAC output to the feedback node, won't that cause the DC-to-DC converter to become unstable?||805||Power Manager II||Hardware||Architecture||IO|
|Can I read the value of NODES in the PAC-POWR1220AT8 via I2C?
||804||Power Manager II||Hardware||Customer Board Design||Schematic|
|What are the GP_OUTPUT I2C registers in the POWR1220AT8 used for?
||803||Power Manager II||Hardware||Architecture||I2C|
|What is the Peak Reflow Temperature for the ProcessorPM or POWR605?||801||Power Manager II||Hardware||Reliability and Materials||Device Materials|
|What is the maximum junction temperature Tj for the POWR1220AT8?||800||Power Manager II||Hardware||Reliability and Materials||Device Materials|
|Does the Power Manager I2C port implement clock stretching?||799||All Power Management||Hardware||Architecture||I2C|
|What's the best way to learn how to use Lattice's PAC-Designer?||797||All Power Management||Literature||Inquiries||User Guides|
|When I measure the Power Manager HVOUT pin the voltage is low. Why?||795||Power Manager II||Hardware||Architecture||IO|
|The Power Manager data sheets only list the Output Low Voltage value with a Max at 20mA. What is the level at 5mA?||794||All Power Management||Hardware||Architecture||IO|
If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?
|What type of pull ups are needed on the JTAG signals?
||791||All ispClock||Hardware||Device Programming||Cables|
|What software is available to program (or download) to the ispCLOCK devices?||790||All ispClock||Software||Device Programming||ispVM System|
Why doesn't the Lattice version of Synplify Pro allow me to run the Synplify.exe or Synplify_pro.exe programs from the command line?
|How do I setup my favorite synthesis and simulation tools in Diamond?||775||All FPGA||Software||Installation||Third Party Tools|
|Can SERDES use different configurations and different reference clock frequencies to support the same data rate?||768||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|SERDES can run at either full-data-rate mode or half-data-rate mode What is the difference between the two?||766||All FPGA||Hardware||Architecture||SERDES/PCS|
|What does the "Information in file ispsys.ini does not match the system" error mean?||757||All Devices||Software||Installation||ispVM System - Win ALL|
|How can I run simulation in the Lattice Diamond software?||753||All FPGA||Software||Simulation||Aldec|
|What are the meanings of the abbreviations in the JEDEC header?||752||All CPLD||Software||Device Programming||Configuration/Programming|
|How can I find the ispLSI2000 device in the ispLEVER if I need to modify my old design?||750||ispLSI2000||Software||Implementation||Project Navigator|
|How can I create the smallest file size for the VME file?||748||All FPGA||Software||Device Programming||ispVM Embedded|
|Can Turbo mode be used together with background programming or TransFR?||747||All Devices||Software||Device Programming||ispVM System|
|Why is my Aldec simulator slow to launch?||746||All FPGA||Software||Licensing||ispLEVER|
|What is the I/O Timing Report?||740||All Devices||Software||Implementation||Timing Analysis|
|What is the default I/O state in a blank MachXO device?||739||MachXO||Hardware||Architecture||Configuration/Programming|
|Do the unused I/O pins need to be grounded in a device?||738||All Devices||Hardware||Customer Board Design||Schematic|
|Where can I find coding examples?||737||All Devices||Software||Entry||Examples|
|How do I use Synplify PRO to view a schematic representation of the RTL in my project?||736||All Devices||Software||Implementation||Synplicity|
|How can I make Synplify infer registers instead of RAM?||735||All CPLD||Software||Implementation||Synthesis|
|How can pins be assigned for GAL devices?||734||GAL/ispGAL||Software||Implementation||Constraint-Pref Editor|
|Does Lattice offer any software that is free?||733||All Devices||Software||Implementation||Project Navigator|
|What is the purpose of the .lpc file generated by IPExpress ?||732||All Devices||Software||Implementation||IPExpress|
|How do I set up the VREF pins for use with the IOs?||731||All Devices||Software||Implementation||Design Planner|
|Is an external pull up required on the MachXO SleepN pin?||730||MachXO||Hardware||Customer Board Design||Schematic|
|How do I find the output resistance of an I/O?||729||All Devices||Hardware||Device Modeling||IBIS|
|How can I find out what process technology is used for a specific Lattice device?||726||All Devices||Hardware||Reliability and Materials||Reliability|
|Does the MachXO device family support true LVDS buffers?
|My design includes mature Lattice devices. How long will they be available?||724||All Devices||Hardware||Customer Board Design||Schematic Review|
|What's the best way to place and route a congested design?||723||All Devices||Software||Implementation||PAR|
|How can I determine what clock resources are being used in my design?||722||All Devices||Software||Implementation||PAR|
|My PC died! How can I get a replacement license for my new PC?||721||All Devices||Software||Licensing||Other|
|Where can I get a license for Lattice software?||720||All Devices||Software||Licensing||Other|
How long does the ispLEVER Classic licenses last?
|Does Lattice Mico8 support the .data directive?||717||All CPLD||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|How would I migrate from LatticeMico8 v2.4 to v3.0?||716||All CPLD||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|Why does ispVM System not recognize the USB programming cable?||715||All Devices||Hardware||Device Programming||Cables|
|Is there an easy way to compare two BIT or JED files?||713||All CPLD||Software||Device Programming||ispVM System|
|What are some things that can prevent ispLEVER Starter from installing correctly?||712||All CPLD||Software||Installation||Win-All|
|What are the constraint files used by ispLEVER Classic?||711||All CPLD||Software||Implementation||Constraint-Pref Editor|
|How do I convert an old PAL JEDEC file for use in a newer GAL device?||710||All CPLD||Software||Device Programming||Configuration/Programming|
|Why do I2C transactions fail with intermittent NACKs? I am using the I2C Slave Peripheral IP RD1054.
||702||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||I2C Slave Peripheral|
|Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?||697||All FPGA||Hardware||Architecture||SERDES/PCS|
|The Place and Route TRACE report displays up to 4096 worst case timing paths per timing preference. Does that mean that the Lattice timing analysis tool will not analyze all the timing paths in my design if they exceed 4096 paths?||692||All FPGA||Software||Implementation||Timing Closure|
|Where can I get cables to program a Lattice evaluation board?||690||All Mixed Signal||Hardware||Device Programming||Cables|
|Where can I find the Thermal Resistance values for the Lattice devices?||689||All Devices||Hardware||Architecture||Power|
|How can I view the internal DAC settings within the ispPAC-POWR1220AT8?||688||Power Manager II||Software||PAC-Designer||Schematic|
|Can the LatticeXP2 send or receive sub-LVDS signals?||682||LatticeXP2||Literature||Inquiries||Appnote/Technote|
|Can a LatticeECP2 dual boot application be set up to load the golden bitstream rather than the primary?||681||LatticeECP2||Hardware||Device Programming||Configuration/Programming|
|Why do I get the warning "Cannot write to selected Working directory. Select another one." when I start the ispVM System software tool?||679||All Devices||Software||Device Programming||ispVM System|
|How can I program a Lattice device that is not listed in ispVM System?
||678||All Devices||Software||Device Programming||ispVM System|
|What happens if I apply power to the POWR1014's VCCPROG pin while applying power to the VCCA and VCCD pins?||674||Power Manager II||Hardware||Customer Board Design||Schematic Review|
|Are there any differences between the VMON inputs on the POWR1208 and POWR1220?||673||All Power Management||Hardware||Customer Board Design||Schematic Review|
|What is the minimum reset pulse width needed to reset a POWR605?||671||Power Manager II||Hardware||Architecture||Power Sequence|
|What is the startup status of the timers in the POWR1014?||670||Power Manager II||Hardware||Architecture||Power Sequence|
|What happens during the shutdown sequence in a PAC-Designer LogiBuilder program? Do I have any control over what happens during the shutdown sequence?||669||All Power Management||Software||PAC-Designer||LogiBuilder|
|Can the ispClock5410D be used to clean jitter from a reference clock signal?||668||ispClock 5400D||Hardware||Architecture||PLL/DLL/Clock Routing|
|Why do I see "An SWT error occurred" when I try to run the LatticeMico32 tools after I've installed them on my Linux system?||663||All FPGA||Software||Installation||Linux|
|Where can I find the MTTF for a device?||662||All Devices||Hardware||Reliability and Materials||Reliability|
|Where can I find the Mean time between failures (MTBF) for a device?||660||All Devices||Hardware||Reliability and Materials||Reliability|
|Should I connect an external clock source to the PCLK pin or the PLL_T pin of my device?||656||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?||655||MachXO||Hardware||Architecture||General Logic|
|My top level design and testbench are in VHDL but some of my lower level modules are in Verilog. How do I perform mixed language simulation with Aldec generally?
|Why does my LogiBuilder design fail to compile? PAC-Designer fails with:
||651||All Power Management||Software||PAC-Designer||Compile/Fit|
|What are the available options for LVDS IO in the LatticeECP3?||646||LatticeECP3||Hardware||Architecture||IO|
|How can I preserve the list of waves that I have in my Active-HDL Waveform Editor for later use?||645||All FPGA||Software||Simulation||Aldec|
|How to show hierarchy of the signals that are listed in the Active-HDL Waveform Editor?||644||All Devices||Software||Simulation||Aldec|
|How to create a single bit file to program two FPGA's from one SPI Flash?||641||All FPGA||Software||Device Programming||ispVM System|
|Does Lattice do Machine Model ESD testing?||636||All Devices||Hardware||Reliability and Materials||Reliability|
|My device has a 3.3V VCCIO, can the device IO drive an LED directly?||635||All CPLD||Hardware||Architecture||IO|
|My application will subject the device to mechanical stress, how can I improve the BGA solder connections?||634||All Devices||Hardware||Architecture||Packaging|
|Where can I find a package view of my device?||632||All Devices||Hardware||Architecture||Packaging|
|Where can I find the "failure in time" (FIT) rate for a device?||631||All FPGA||Hardware||Reliability and Materials||Reliability|
|How can I read a lot code for a Lattice device?||630||All CPLD||Hardware||Architecture||Packaging|
|My application requires radiation hardened packaging, what are my options?||628||All Devices||Hardware||Reliability and Materials||Reliability|
|What is the PAR Strategy Auto Hold Time Correction used for?||627||All Devices||Software||Implementation||PAR|
|Why do I get a license error when I open Diamond through Windows Remote Desktop?||625||All CPLD||Software||Installation||Win Other|
|What is the detailed power-up sequence for a MachXO device?||619||MachXO||Hardware||Architecture||Power Sequence|
|Where do I find information on running ActiveHDL via command line?||615||All Devices||Software||Simulation||Aldec|
|How do I upgrade Synplify Software through "ispUpdate"?||613||All Devices||Software||Installation||Third Party Tools|
|My shift register is infered using RAM not LUTs how can I prevent this?||612||All Devices||Software||Implementation||PAR|
|Does ispVM Embedded support the Lattice device I am using?||607||All Devices||Software||Device Programming||ispVM Embedded|
|What could cause the "JTAG-NOP" error message in ispVM System tool?||606||All Devices||Software||Device Programming||ispVM System|
|Can ispVM control the JTAG TCK duty cycle and/or frequency?||605||All Devices||Software||Device Programming||ispVM System|
|Should I connect all the JTAG signals on the download cable to my board?||598||All CPLD||Hardware||Device Programming||Cables|
|Which Operating Systems are supported by ispVM?||596||All Devices||Software||Device Programming||ispVM System|
|I have an ispMACH 4000ZE Pico Development Kit. What programming cable type should be selected in ispVM System?||594||ispMACH 4000||Hardware||Lattice Evaluation Board||ispMACH 4000ZE Pico Dev Kit|
|What programming cable type should be selected in ispVM System when using the MachXO Control Development kit?||593||MachXO||Hardware||Lattice Evaluation Board||MachXO Control Dev Kit|
|What is the difference between the USB and USB2 cable types in ispVM System?||592||All Devices||Software||Device Programming||ispVM System|
|How can I determine if there is a lead free package option for a device?||587||All Devices||Hardware||Architecture||Packaging|
|What is the device package pin/ball composition?||586||All Devices||Hardware||Reliability and Materials||Device Materials|
|How can I determine if I have an authentic Lattice device?||582||All CPLD||Hardware||Reliability and Materials||Device Materials|
|How do I use the ispMach4000 global clocks?||578||ispMACH 4000||Hardware||Architecture||PLL/DLL/Clock Routing|
|Is there any Waveform Monitor setting affecting jitter measurement value?||563||LatticeECP3||IP/Reference Designs||Lattice IP/Reference Designs||Tri-Rate SDI PHY|
|What is "Repetitive Download" tool in the ispVM software?||559||All Devices||Software||Device Programming||ispVM System|
|Can I combine ABEL and HDL source codes in the same project?||558||All Devices||Software||Entry||Mixed Language|
|Under what conditions will the Leave Alone IO feature be active?||557||All Devices||Software||Device Programming||ispVM System|
How do I integrate Active-HDL in ispLEVER Starter?
Where can I find an explanation of the Syntax and Guidelines for manually editing preference files?
|549||All Devices||Literature||Inquiries||Help Files|
|Why do I get errors of the form "Failed to find 'GSR_INST' or 'PUR_INST' in hierarchical name." when I use the Modeslim MTI simulator?||546||All FPGA||Software||Simulation||MTI|
|Do Lattice FPGAs support Spread-Spectrum Clocking (SSC)?||543||All FPGA||Hardware||Architecture||PLL/DLL/Clock Routing|
|What is the recommended connection for the XRES pin for the LatticeECP2/M, LatticeECP3, and LatticeSC/M devices?||538||All FPGA||Hardware||Customer Board Design||Schematic Review|
|Why can't I scan or program the MachXO device on the MachXO Mini board after I programmed my pattern into the device?||534||MachXO||Hardware||Device Programming||Lattice Evaluation Boards|
|Can the LatticeECP3 still be programmed after setting the encryption key?||529||LatticeECP3||Hardware||Device Programming||Customer Board|
Where is LatticeECP2/M Serdes Reset RTL code ?
|What is the difference between POWR1014A-01 and POWR1014A-02?||521||Power Manager II||Literature||Inquiries||Datasheet|
|Can ispVM EMBEDDED be used to program Power Manager II devices?||520||All Power Management||Software||Device Programming||ispVM Embedded|
|Why can't I drive a long PCB trace with a low current setting and get good signal quality?||508||All FPGA||Hardware||Customer Board Design||Board Debug|
Why can't the Lattice SERDES directly connect to a 1000BASE-T network?
|How can I correct for routing errors on my board that caused swapping of some of the XAUI SERDES lanes when using the XAUI PCS IP?||495||All FPGA||Hardware||Architecture||SERDES/PCS|
Why do I get a License Checkout Failure message when I use my old license file and a new installation of the Lattice software on my new PC?
|494||All Devices||Software||Licensing||Lattice Diamond|
|Where can I find information about the Parameterized Module Instantiation (PMI) feature?
||493||All FPGA||Literature||Inquiries||User Guides|
|Where can I find the value of \u03B8JA/ThetaJA for Lattice devices such as LatticeECP2M, LatticeSCM or other devices?||486||All FPGA||Hardware||Architecture||Power|
|How do I setup my favorite synthesis, simulation and editors in ispLEVER?||475||All FPGA||Software||Installation||Third Party Tools|
|What is the meaning of a Vital Glitch warning and should I be concerned when I get it?||472||All Devices||Software||Simulation||Aldec|
|Is there a Clock device with adjustable skew that is controlled by I2C?||468||All ispClock||Hardware||Architecture||IO|
|How do I control the slew-rate of a MOSFET through HVOUT of a Power Manager II?||467||All Power Management||Hardware||Architecture||IO|
|How do I connect the POWR6AT6 Trim-DAC control to an analog-digital converter (ADC)?||466||Power Manager II||Software||PAC-Designer||TRIM Usage|
|How do I know which termination to use on the ispClock5406D evaluation board when measuring jitter?||464||ispClock 5400D||Hardware||Lattice Evaluation Board||ispClock 5312S|
|Is there an IBIS model for the POWR605?||463||Power Manager II||Hardware||Device Modeling||IBIS|
|What is the Vbpz Selection in the Trim Configuration Options of PAC-Designer?||462||Power Manager II||Software||PAC-Designer||TRIM Usage|
|Does Lattice support the programming of SPI FLASH memory via the JTAG port?||456||All FPGA||Hardware||Device Programming||ispVM Embedded|
|Why doesn't the USERCODE assigned using Spreadsheet View match the value retrieved from a LatticeXP2 programmed with an encrypted bitstream?||452||LatticeXP2||Hardware||Device Programming||Configuration/Programming|
|Why does PAC-Designer 5.2 fail to run and issue the following message? "C:\PAC-Designer52\PACD52.exe. This application has failed to start because the application configuration is incorrect. Reinstalling the application may fix the problem."||451||All Mixed Signal||Software||PAC-Designer||LogiBuilder|
|Which ispClock device can be used for high speed SERDES reference?||447||All ispClock||Hardware||Architecture||SERDES/PCS|
|What are the GP_OUTPUT registers in the POWR1220AT8 and POWR1014/A used for?||446||All Power Management||Hardware||Architecture||General Logic|
|When I measure the Power Manager II HVOUT voltage it is low, why?||445||All Power Management||Hardware||Architecture||IO|
|Can I read the value of NODES in the LA-ispPAC-POWR1014/A via I2C?||444||Power Manager II||Hardware||Architecture||General Logic|
|Can I read the value of NODES in the POWR1014/A via I2C?||443||Power Manager II||Hardware||Architecture||General Logic|
|Can I read the value of NODES in the POWR1220AT8 via I2C?||442||Power Manager II||Hardware||Architecture||General Logic|
|How can I regenerate the menu.hex file after I modify the mini_soc_demo_menu.txt file for the MachXO mini board Soc demo design?||441||MachXO||IP/Reference Designs||Lattice IP/Reference Designs||Mico8 Microcontroller|
|Why is Idk listed separately from other IO leakage currents in Lattice data sheets?||440||MachXO||Literature||Inquiries||Datasheet|
|How do I instantiate the ispMACH 4000ZE on-chip oscillator in VHDL source code?||439||ispMACH 4000||Software||Entry||VHDL|
|Why don't you have a SPI Flash programmer reference design for newer device families?
||437||All Devices||IP/Reference Designs||Lattice IP/Reference Designs||SPI WISHBONE Controller|
|How can I sense current with a Power Manager II?||433||All Power Management||Hardware||Architecture||IO|
|How to can I get an IBIS model for differential LVPECL IO when the generated model from ispLEVER is a single ended model?
||432||All Devices||Hardware||Device Modeling||IBIS|
|How is bitstream programming verification (Verify) performed within Lattice ispVM System?
||431||All Devices||Hardware||Device Programming||ispVM System|
|Does input threshold of an IO pin depend on Vcco value?||429||ispMACH 4000||Hardware||Architecture||IO|
|Why does synthesis tool prune counter bits away while they appear to be used in the equations?||427||All Devices||Software||Implementation||Synplicity|
|Why are the schematics missing from the ispClock5406D I2C Utility of PAC-Designer?||423||ispClock 5400D||Software||PAC-Designer||Design Utilities|
|How can I tell which Lattice devices contain Beryllium?||420||All Devices||Hardware||Reliability and Materials||Device Materials|
|Why does IPExpress in ispLEVER crash when launched in Windows Vista?||418||All FPGA||Software||Installation||Win Vista|
Why doesn't ispLEVER save paths to my favorite synthesis and simulation tools?
|417||All FPGA||Software||Installation||Win Vista|
How do I avoid Read Before Write (RBW) memory inference for LatticeECP2/M, LatticeXP2 using Synplify?
|How does one interpret the lotcode/datacode marking on Lattice Devices?||415||All CPLD||Hardware||Architecture||Packaging|
|How do I implement Power-Off Detection in a Power Manager II device ?||413||Power Manager II||Hardware||Architecture||IO|
|Does the VCCPROG pin have to be powered in order to program the LA-ispPAC-POWR1014/A?||412||Power Manager II||Hardware||Architecture||Configuration/Programming|
|Does the VCCPROG pin have to be powered in order to program the POWR1014/A?||411||Power Manager II||Hardware||Architecture||Configuration/Programming|
|Does the Die Pad of the POWR605 need to be grounded ?||410||Power Manager II||Hardware||Architecture||Packaging|
|Does the Die Pad of the POWR6AT6 need to be grounded?||409||Power Manager II||Hardware||Architecture||Packaging|
|Does the die pad of the POWR607 need to be grounded to my board?||408||Power Manager II||Hardware||Architecture||Packaging|
|Where is the Reset pin for the ProcessorPM - POWR605 ?||407||Power Manager II||Hardware||Architecture||Power Sequence|
|Where is the Reset pin for the Power Manager II - POW607 ?||406||Power Manager II||Hardware||Architecture||Power Sequence|
|Does the VCCPROG pin have to be powered to program the Power Manager II - POWR1220AT8?||405||Power Manager II||Hardware||Architecture||Configuration/Programming|
|Is it possible to run ispLEVER on Windows 7?||402||All Devices||Software||Installation||Win 7|
|Which Lattice devices have BSDL (boundary scan description files) files available?||399||All Mixed Signal||Hardware||Device Modeling||BSDL|
|Does Lattice provide symbol libraries for ORCAD schematic capture?||397||All Mixed Signal||Hardware||Customer Board Design||Schematic|
|Where do I find the physical packaging outlines and dimensions for Lattice products?||393||All Devices||Hardware||Architecture||Packaging|
|What is the difference between a hard-reset and a soft-reset on the ispCLOCK5400D device?||392||ispClock 5400D||Hardware||Architecture||PLL/DLL/Clock Routing|
|Can I use a Low-cost CMOS oscillator with ispClock5400D devices?||389||ispClock 5400D||Hardware||Architecture||IO|
|How do you set the security cell and electronic signature for the GAL or ispGAL devices?||388||GAL/ispGAL||Hardware||Device Programming||Configuration/Programming|
|What should I do with the LatticeECP3 DDR3 memory interface VTT termination?||387||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
What should I do with the unused VTT pads in LatticeECP3 when external VTT termination is implemented?
|386||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
How can I terminate a DDR2 or DDR3 memory interface to VTT in LatticeECP3?
|381||LatticeECP3||Hardware||Architecture||DDR Memory Interface|
|Can I use Reveal Logic Analyzer in a JTAG chain with multiple devices?||380||All FPGA||Software||Debugging||Reveal|
|Does Lattice offer 5V CPLD devices?||379||All CPLD||Hardware||Architecture||Power|
|Does ispVM System support Windows Vista(32-bit) for the USB and Parallel port drivers?||374||All Devices||Software||Device Programming||ispVM System|
|Where can I find the availability of a programming socket adapter for Lattice devices?||373||All Devices||Hardware||Device Programming||Adapters|
|What does it mean when I have a part that is "dual-marked"?||364||All Devices||Literature||Inquiries||Datasheet|
|What is the toggle frequency of Lattice devices?||363||All CPLD||Hardware||Architecture||General Logic|
|Does IO timing change with Vcc or Vccio level?||362||All Devices||Hardware||Architecture||IO|
|How to reduce IO power consumption?||361||All Devices||Hardware||Architecture||IO|
|How many power supply rails does MACHXO device need?||360||MachXO||Hardware||Architecture||Power|
|Where can I find definitions for schematic library macros?||359||All CPLD||Software||Implementation||Schematic|
|In a LatticeECP2/M part, can I use an SPLL dedicated FB input pad to connect to the SPLL IN pin?||358||LatticeECP2/M||Hardware||Architecture||PLL/DLL/Clock Routing|
|Is is OK to terminate VCCIB/VCCOB (VDDIB/VDDOB) to power on unused SERDES channels of all Lattice SERDES/PCS based devices (LatticeECP2M/LatticeECP3/LatticeSC/M)?||357||All FPGA||Hardware||Architecture||SERDES/PCS|
|In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?||356||All FPGA||Hardware||Architecture||SERDES/PCS|
What's the best, first step to debug looped-back 16-bit data with 8b10b encoding for SERDES/PCS applications in Lattice FPGA's?
|Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?||354||All FPGA||Hardware||Architecture||SERDES/PCS|
|What is the state of FPGA Flip Flop outputs at power-up? The reset pins of my design registers are tied to neither GSR nor LSR.||353||All FPGA||Hardware||Architecture||General Logic|
How do the VCCIB pins on the LatticeECP3 need to be connected if the SERDES receive inputs (HDIN) are not being used?
|Is it possible to create a design using the Tri-speed Media Access Controller (TSMAC) that can dynamically switch between SGMII & Gbe mode?||347||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Tri-Speed Ethernet MAC|
|Where can I find a description of Synplify errors and warnings?||346||All FPGA||Software||Implementation||Synplicity|
|What do I need in addition to the Tri-Speed Mac (TSMAC) core on the board (PHY, magnetics etc)?||345||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||Tri-Speed Ethernet MAC|
|For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?||344||All FPGA||Hardware||Architecture||SERDES/PCS|
|Can I edit the LatticeECP2/M PCS auto-configuration to support a SERDES clock multiplier that is not available in the IPexpress GUI?||342||LatticeECP2/M||Software||Implementation||IPExpress|
|Can I ignore Synplify Pro "Unrecognized synthesis directive attribute" warnings? Can I set a Synplify option to prevent reporting these warnings?||341||All FPGA||Software||Implementation||Synplicity|
|ELAB2 Fatal Error ELAB2_0036 Unresolved hierarchical reference to PUR_INST.PURNET from module (module not found), what to do with this simulation error in Active HDL?||340||All FPGA||Software||Simulation||Aldec|
|How long does it take for XP2 to complete self download configuration at power up?||337||LatticeXP2||Hardware||Device Programming||Configuration/Programming|
|Why does my static timing score not improve after adding place and route iterations?||336||All FPGA||Software||Implementation||PAR|
|How can I tell if a licensed IP is in my design?||335||All FPGA||Software||Licensing||IP|
|For dual boot, can I tell which image is loaded into FPGA if the primary and golden images are identical?||334||All FPGA||Hardware||Device Programming||Configuration/Programming|
|How can I generate application (design) specific BSDL file?||333||LatticeXP2||Hardware||Device Modeling||BSDL|
|Can I have the same logic assigned to different UGROUPs?||332||All FPGA||Software||Implementation||Design Planner|
|How can I estimate the pull up and pull down resistors of Lattice's CPLD and FPGA devices?||325||All FPGA||Hardware||Customer Board Design||Board Debug|
|How do I implement a multi-source interrupt?||324||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|What are the definitions of the BAR bits in PCI/PCIe application?||323||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|How do I evaluate the credit unit in PCI Express?||321||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|Is it possible to use DSP blocks as MUX function?||320||All FPGA||Hardware||Architecture||DSP|
|How does Time-Skew compare to Phase-Skew on the ispCLOCK5400D devices?||314||ispClock 5400D||Hardware||Architecture||PLL/DLL/Clock Routing|
|Which ispCLOCK devices are dynamically reconfigurable?||313||All ispClock||Hardware||Architecture||I2C|
Which Lattice devices have evaluation boards to try out my code?
|312||All Devices||Hardware||Lattice Evaluation Board||Platform Manager Development Kit|
|Does the Linux version of ispVM support the USB Download cable?||307||All Devices||Software||Device Programming||ispVM System|
|Can I program ispPAC-POWR or ispClock products with the Lattice USB ispDownload cable?||306||All Mixed Signal||Hardware||Device Programming||Cables|
Which VREF pad should I use between VREF1 and VREF2 for a DDR2 or DDR3 memory controller?
|305||All FPGA||Hardware||Architecture||DDR Memory Interface|
|What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?||304||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||DDR2 SDRAM Controller|
|Can I use all availabe DQS pad in a Lattice FPGA device for my DDR1/2/3 memory controller applications?||300||All FPGA||Hardware||Architecture||DDR/DDR2/DDR3|
|Is there a difference in size between an encrypted and unencrypted FPGA bitstream?
||298||All FPGA||Software||Device Programming||ispVM System|
How do I implement differential SSTL pads in software for my DDR memory interface design?
|297||All FPGA||Hardware||Architecture||DDR Memory Interface|
|Does the configuration file (such as an ECP3 bitstream) for SPI flash remain at fixed size regardless the size of the FPGA design?||296||LatticeECP3||Software||Device Programming||ispVM System|
|How do I generate a LatticeXP and LatticeXP2 device bit files for EPROM programming?||295||LatticeXP2||Software||Device Programming||ispVM System|
|What can I do if the VME file size is larger than the non-volatile memory?||293||All FPGA||Software||Device Programming||ispVM System|
|Can I evaluate a Lattice DDR IP core on a Lattice evaluation board without an IP license?||292||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||DDR2 SDRAM Controller|
|Can C code header naming conventions cause any issues with ispVM Embedded?||291||All FPGA||Software||Device Programming||ispVM Embedded|
|How do I build a SERDES External Link State Machine to perform word alignment?||290||All FPGA||Hardware||Architecture||SERDES/PCS|
|How many times can a FLASHBAK be done in the LatticeXP2?||289||LatticeXP2||Hardware||Device Programming||Data Retention|
|Where do I find information about the weight of a Lattice Semiconductor device?||286||All FPGA||Hardware||Reliability and Materials||Device Materials|
|Can I replace the dummy bits in the LatticeECP3 bitstream header with custom data (revision ID for example)?||285||LatticeECP3||Software||Device Programming||ispVM System|
|How can I compile and link LatticeMICO32 code so that it is position independent?||284||All FPGA||Software||Implementation||Mico32(MSB)|
|Can Reveal logic analyzer run without being connected to the Analyzer software?||281||All FPGA||Software||Debugging||Reveal|
|For the Power Manager-II devices, how many I2C loads can I put on an I2C chain?||280||Power Manager II||Hardware||Customer Board Design||Layout|
|Can I use an ispPAC-POWR6AT6 just to monitor voltages and not trim etc? If so, what is the simple way to do this?||279||Power Manager II||Hardware||Architecture||Power|
|Can I buy factory-programmed Power Manager parts?||278||All Power Management||Hardware||Device Programming||Customer Board|
|What is different about the ProcessorPM-POWR605 relative to the other Power Manager devices from Lattice?||276||Power Manager II||Hardware||Architecture||Power Sequence|
|How do I change the Timers on a ProcessorPM-PM605?||275||Power Manager II||Software||PAC-Designer||LogiBuilder|
|Can I simulate a ProcessorPM-POWR605?||273||Power Manager II||Software||PAC-Designer||Simulation|
Are there speed grades for different Power Manager-II Devices, such as ispPAC-POWR1220AT8 or ispPAC-POWR1014A?
|271||Power Manager II||Literature||Inquiries||Datasheet|
|How can I implement multiple ispPAC-POWR1220AT8 Power Manager devices on a board?||270||All Power Management||Software||PAC-Designer||LogiBuilder|
|Is there an easy way to get started learning Platform Manager devices and PAC-Designer?||267||Platform Manager||Software||Entry||Examples|
What is the meaning of "ff_rxiclk_ch0" and "ff_ebrd_clk_0" and how to connect them in HD-SDI mode?
How to use LatticeECP2M Serdes in XAUI mode? Does the channel 0-3 respectively correspond to the lane 0-3 only or is it possible to select any channel-to-lane mapping?
|265||LatticeECP2/M||IP/Reference Designs||Lattice IP/Reference Designs||XAUI 10Gb Ethernet AUI|
|In the detection of word alignment, what are the number of protection steps and the recovery conditions?||264||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
|What is the difference between Quad Based Protocol Mode and Channel Based Protocol Mode?||263||LatticeECP2/M||Hardware||Architecture||SERDES/PCS|
How do I use "CC_MATCH_MODE" and High and Low watermark setting in the Clock Tolerance Compensation (CTC) section of the IPExpress?
|Why is the maximum frequency Fmax in the Place and Route Trace report different from that in the Performance Analyst(PA) report?||261||All FPGA||Software||Implementation||Trace|
|Where do I find information for:
||260||All FPGA||Literature||Inquiries||Help Files|
|What is the origin of my device?||249||All CPLD||Literature||Inquiries||Datasheet|
|Is there ESD (Electro Staic Discharge) protection circuitry on the MachXO?||248||MachXO||Hardware||Architecture||IO|
|Is an external pull up required on the MachXO SleepN pin?||247||MachXO||Hardware||Architecture||IO|
|How is the TSALL pin used in the MachXO?||246||MachXO||Hardware||Architecture||IO|
|What is the difference between an ispGAL and a GAL device?||245||GAL/ispGAL||Hardware||Architecture||General Logic|
|What is the detailed power up sequence for a MachXO device?||242||MachXO||Hardware||Architecture||Power Sequence|
|How can I simulate open drain IO/s?||241||All Devices||Software||Entry||Mixed Language|
|How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?||235||All Devices||Hardware||Architecture||Memory EBR/Distributed|
|Which device is the number 1 device in the JTAG chain?||234||All Devices||Hardware||Device Programming||ispDaisy Chain Download|
|How to create a schematic symbol for a bus in an ABEL module?||232||All CPLD||Software||Entry||Schematic|
|Why are the registers being clocked at a faster rate than intended?||231||All Devices||Software||Implementation||Synplicity|
|Is there a way to include library scripts into ORCAstra scripts and the scripts associated with Visual Windows?||228||All FPGA||Software||Debugging||ORCAstra|
|Are there ispLEVER software tutorials and manuals in my ispLEVER installation?||227||All CPLD||Literature||Inquiries||Tutorials|
|Why am I having problems with my older LatticeMico32 System Builder after I installed a newer version LatticeMico32 System Builder?||225||All FPGA||Software||Implementation||Mico32(MSB)|
|How should I setup my SPI4.2 IP core power-on reset sequence?||222||All FPGA||IP/Reference Designs||Lattice IP/Reference Designs||SPI4.2|
|How can I find recommended replacements for a mature or obsolete Lattice device?||221||All CPLD||Literature||Inquiries||Web Site|
|Why am I having problems routing my SERDES/PCS interface clock in the LatticeECP3 FPGA?||219||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|Why am I getting an error in "map" when I want to reset my IP cores with different resets? The error occurs as: "ERROR - map: Multiple GSR components found, GSR_INST and /GSR_INST, but are not compatible to be merged. GSRs have different signal drivers. GSR inferencing terminated."||218||All FPGA||Hardware||Architecture||General Logic|
|Why do I get warning messages stating Edge or Primary clock is unroutable, occupied and uses general routing, or are not placed on sweet site?||217||All FPGA||Software||Implementation||PAR|
|Does Lattice perform product analysis with devices from the field?||215||All Devices||Hardware||Reliability and Materials||Device Materials|
|Why do I get an Iteration Limit Error when I try to simulate?||214||All FPGA||Software||Simulation||MTI|
|How can I perform setup and initialization tasks in an ORCAstra Visual Window?||213||All FPGA||Software||Debugging||ORCAstra|
|Why do I have items in my trace report with 0 timing score?||212||All FPGA||Software||Implementation||Trace|
|I am having installation problems with ispLEVER Starter.||208||All Devices||Software||Installation||Win-All|
|Can ORCAstra access and manipulate data in a file from a Script Window or Visual Window?||205||All FPGA||Software||Debugging||ORCAstra|
|What is the initial logic level of a register after power-up?||204||All FPGA||Hardware||Architecture||General Logic|
|What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or LatticeECP3 device?||203||All FPGA||Hardware||Customer Board Design||Layout Review|
|What are the pin location requirements when using an input clock to capture input data?||202||All FPGA||Hardware||Customer Board Design||Layout Review|
|How do I get a reasonable I/O timing report when PLL phase shift is very large?||200||All FPGA||Software||Implementation||Timing Analysis|
|How do I improve the performance of FPGA designs that use Embedded Block RAM (EBR)?||198||All FPGA||Software||Implementation||Timing Closure|
|How do I run the hold time correction when the number of hold time violations exceed 250?||196||All FPGA||Software||Implementation||PAR|
|Where can I find differences between the current and older versions of the ispVM System software?||195||All Devices||Software||Installation||ispVM System-Win XP|
|What is the meaning of the ispLEVER Classic warning
|How do you fix the library incompatibility error when running the Active HDL from ispLEVER?||190||All Devices||Software||Simulation||Aldec|
|What is the maximum number of devices ispVM programming chain supports?||188||All Devices||Software||Device Programming||ispVM System|
|How can I create a 10 second timer in an ispPAC-POWR1220AT8 device?||186||Power Manager II||Software||PAC-Designer||LogiBuilder|
|Can ispVM System program ispClock or ispPAC-POWR products?||185||All Mixed Signal||Software||Device Programming||ispVM System|
|What can you do with the I2C interface on the Power Manager II devices?||184||Power Manager II||Hardware||Architecture||General Logic|
|What is the supply/production status of the Lattice ispPAC10, ispPAC20, ispPAC30, and ispPAC80/81 devices?||183||ispPAC||Hardware||Reliability and Materials||Lifetime|
|Where can I find information about the reliability of Lattice Power Manager and ispClock devices?||182||All Mixed Signal||Hardware||Reliability and Materials||Device Materials|
|The voltage ranges in the IBIS model files typically extend beyond the limits specified in the device datasheets. Can these voltages be applied to the device?||178||All CPLD||Hardware||Device Modeling||IBIS|
|In IBIS models, the drive high, or "[pullup]" section lists strange voltage ranges and appears to be inverted. Why is this?||176||All Devices||Hardware||Device Modeling||IBIS|
|My 3rd party tool complains of unsupported SVF file commands. Why is this?||170||All Devices||Software||Device Programming||3rd Party|
|What is the difference between ispVM Embedded and the EPROM version?||163||All CPLD||Software||Device Programming||ispVM Embedded|
|How can the default/recent projects (.xcf) be cleared in the File menu of ispVM?||161||All FPGA||Software||Device Programming||ispVM System|
|I am migrating from one LatticeECP3 device/package to another LatticeECP3 device/package. Is there a description of the differences between the various devices and packages?||157||LatticeECP3||Literature||Inquiries||Datasheet|
|Why does the TRACE tool report look as though I entered a specific frequency preference (without my having adding any preference)?||153||All CPLD||Software||Implementation||Timing Analysis|
|Do the oscillator or timer outputs consume macrocell logic in the ispMACH4000ZE devices?||151||ispMACH 4000||Hardware||Architecture||PLL/DLL/Clock Routing|
|How can I generate vectors to program Lattice devices using Automated Test Equipment (ATE)?||150||All CPLD||Software||Device Programming||ispVM System|
|Where can I find the entire pinout list for the ECP3 device?
|Where do users find the reference examples for ispVMEmbedded code?||148||All FPGA||Software||Device Programming||ispVM Embedded|
|How should I connect the VCCIO pins when none of the I/O in a bank are being used?||145||All FPGA||Hardware||Architecture||Power|
|What is a Digital CDR? How is it different from a normal CDR?||143||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|What is a possible reason for the INITn pin going low while loading configuration image from SPI flash device?||142||LatticeECP3||Hardware||Architecture||Configuration/Programming|
|How can I determine which boundary scan operations are supported for a given device and package, and what the values are?||141||All Devices||Hardware||Customer Board Design||Board Debug|
|Why does my MAP Timing report have errors and my Place and Route Timing Report does not (and vise versa)? Is the MAP report completely useless?||139||All FPGA||Software||Implementation||MAP|
|Why is my Lattice FPGA getting very hot while debugging my board?||138||All FPGA||Hardware||Customer Board Design||Board Debug|
Why doesn't the test bench, included in the Basic Demo for the LatticeECP2M PCIe DevKit, simulate properly?
|137||LatticeECP2/M||IP/Reference Designs||Lattice IP/Reference Designs||PCIe|
|How can I block clock domain transfers where I already have my own synchronizer circuit?||134||All FPGA||Software||Implementation||Timing Analysis|
|Where can I find information on the clock domains in my design?||132||All FPGA||Software||Implementation||Timing Analysis|
When running a design using AIL, such as a SPI4.2 design, in ispLEVER using an LatticeSC/M device, why do I get an error in MAP?
ERROR - map: Delay cell rxgb/genblk1_u_15__CDLY has an invalid FDEL setting - when the delay cell is in CFGBIT (static) mode, and the IOLOGIC AIL is on, the valid FDEL value range is from 8 to 39.
|When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?||130||LatticeECP3||Hardware||Architecture||SERDES/PCS|
|How can I single out a specific path or transfer in the timing analysis TRACE report? There might be thousands of transfers for my FREQUENCY preference, how can I find a specific path or transfer?||129||All FPGA||Software||Implementation||Timing Analysis|
|What are VCC(VDD)IB and VCC(VDD)OB supply connections used for on LatticeECP2M/3 and LatticeSC/M devices?||128||All FPGA||Hardware||Architecture||SERDES/PCS|
|Why do TRACE and the Performance Analyst not agree on the Maximum Frequency (Fmax) of a design?||127||All FPGA||Software||Implementation||Timing Analysis|
|The IBIS model file is text, how can I view the output IO waveform?||121||All FPGA||Hardware||Device Modeling||IBIS|
Why do I get warnings when my design has Embedded Block RAM (EBR) in Asynchronous Reset Mode?
|Why doesn't Synplify retain hierarchy/instance names when small changes are made to the HDL?||116||All Devices||Software||Implementation||Synthesis|
Why do I get "ELAB2_0093" error in mixed Verilog/VHDL design simulation?
|Why does Active HDL hang after loading the waveforms?||114||All FPGA||Software||Simulation||Aldec|
|How to invoke and use Active-HDL Lattice Edition in Batch Mode?||113||All FPGA||Software||Simulation||Aldec|
|How do I invoke and use Active-HDL Lattice Edition in GUI Mode?||112||All FPGA||Software||Simulation||Aldec|
|Why do I get errors with Modelsim Library due to incompatible libraries?||111||All FPGA||Software||Simulation||MTI|
|Why do Aldec Active-HDL simulation database and simulation results, that are displayed in the Waveform window, fail to refresh automatically?||110||All Devices||Software||Simulation||Aldec|
Why doesn't Active-HDL Aldec license server start automatically at boot?
|How can I reprogram a Secured LatticeXP2?||106||LatticeXP2||Hardware||Architecture||Configuration/Programming|
|How can I determine if a LatticeXP2 FPGA configured from internal flash or from an external SPI flash?||105||LatticeXP2||Hardware||Architecture||Configuration/Programming|
|Why does my LatticeXP/XP2 device get hot after programming from Flash?||104||LatticeXP2||Hardware||Architecture||Configuration/Programming|
|Can the LatticeXP2 use encrypted configuration bitstreams supplied by an external SPI Master or SPI Slave?||103||LatticeXP2||Hardware||Architecture||Configuration/Programming|
|Does Dual Boot support Fast SPI loading in LatticeECP2/M?||102||LatticeECP2/M||Hardware||Architecture||Configuration/Programming|
|What do I do with VCCIBx connection of the SERDES channel in TX only mode?||82||LatticeECP3||Hardware||Architecture||SERDES/PCS|