Lattice FAQs

Do Lattice ispVM support the programming via Channel A and Channel B of FT2232H for Lattice MachXO2 devices?

In the PAC designer software is the number of "Outputs" used in a program related with the usage of macrocells in the Power Manager device  ?

Will the "PRIVATE" instructions in BSDL file have any impact on my BSCAN test? Do I need them to perform a BSCAN test?

For the POWR1220AT8 device can we switch between I2C and Closed Loop Trim modes dynamically without re-programming the device?

What is the recommended connection for the VCCIO pads on an unused LatticeECP3-EA bank, connected to a known state or left unconnected?

Do I need to connect a 100 ohm series resistor between monitored voltages and VMON pins on the POWR1220AT8 device?

What is the behavior of the Programn, Initn, and Done Pins when disabled on the MachXO2 in SDM Mode?

Why don't I see the IP core from the core list in the IPexpress main GUI after the core has been successfully installed?

What are the rules when locking DQ-DQS grouping pins?

How do I create a new Reveal Analyzer file without deleting an existing .rva file in my Lattice Diamond project directory?

What's the propagation delay inside LUTs of Lattice ECP3?

Can we short the inputs of two VMON comparators ( i.e. VMON1 and VMON2) of the Power Manager Device externally on the board for monitoring a supply rail ?

Why do I get the message "ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible" on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?

What is the behavior of the MachXO2 oscillator when transitioning between configuration and user mode?

How does slow slew rate on TCK input affect Lattice FPGA device programming?

Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?

Why does my ispVM System software not properly recognize Platform Manager?

Can Power Manager II Device  support Hot Socketing?

What does the "potential loop circuits" section of the Place and Route TRACE report mean?

Do Lattice's IBIS models include the RLC data for each pin?

The Lattice HDR-60 layout file is in Allegro .brd format, can Lattice translate the file to other formats?

What is best practice for the MachXO2 Slave SPI Chip Select (SN)?

What happens to the MachXO2 internal oscillator during background flash programming?

In the PAC Designer Trim Configuration Options what does "Open External Resistors(s) Threshold" impliy?

MachXO2 datasheet states that LVDS33 is supported but I cannot select this IO Type in the software and an error is generated if it is added manually to the .lpf file.

Why does an SVF file for LatticeXP2-17 Erase/Program/Verify operation take a longer time to perform the operations compared to the time of Diamond Programmer or ispVM?

Is there a low cost way to power the ProcessorPM-POWR605 off of a 5V rail?

What are DELPHI Compact Thermal Models, how can these be used and what is their scope?

What programming support is available for LatticeXO2 SSPI and I2C with the download cable?

How does the Clock Data Recovery (CDR) Loss of Lock pin on the LatticeECP3 behave when the reference clock is stopped?

How do I restore the LatticeECP3 IO Protocol evaluation board back to the original factory programming?

How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains? 

What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port? 

Is there a limit to the number of state machines implemented in the POWR1220AT8 in PAC-Designer?

How can I calculate the power consumption in a Platform Manager device?

The generated DDR3 IP core includes a DDR3 DIMM (dual in-line memory module) instantiation module (ddr3_dimm_32.v) in the testbench when the selected memory type is On-board Memory. How can I instantiate the DDR3 device memory model in my testbench for simulation?

Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?

What does "potential circuit loops found in timing analysis" in trace report mean?

What are the neccesary configurations for using the ispClock5600A with single ended input clocks?

In the PAC-Designer TRIM block, why does the Vbpz value sometimes change when the EIA Resistor Standard is changed in the options menu?

Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?

How can I connect the Platform Manager trim profile selection to Profile 0 in hardware?

When using the File->Import command in PAC-Designer, what information is imported from the JEDEC file?

Is it possible to manually assign TRIM DAC output voltages to Power Manager II Devices, rather than using the trim configuration calculator?

How does the DC-DC Converter library work with the TRIM resistor calculation in PAC-Designer when a project is opened but does not have access to the original DC-DC Converter library?

What are the recommendations for a flex cable that connects a sensor to the Lattice HDR-60?

Why can the total number of I/O pins not be used for the MachXO2 device?

Where can I find information about the package thermal resistance of the ispPAC-POWR1014/A device?

Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?

Does MACHXO2 support mixed voltage for LVCMOS and LVTTL I/O type?

Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors.  How can this happen?

Where can I find the process technology information for the Power Manager II products?

Can I use same JEDEC file or bit file to program different speed rating parts?

When running Reveal Analyzer what files are needed and where do I get the files?

What is the programming time for XO2 device, when use I2C bus to programm the chip?

How to cross trigger between multiple cores with Reveal?

Why do I get EDIF translation Errors when my EDIF file contains a Reveal Core?

Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?

What is the current sink capability of the LOCK pin in the ispClock 5600A?

Which Lattice parts are recommended for new designs in place of the POWR1208P1?

What is the allowed voltage at the VMON pins when the POWR607 is unpowered (hot socket scenario)?

During Trim configuration in PAC-Designer, I receive an error when calculating DAC settings for my target profiles. What can cause this?

Why do I see the EMI change when adding or removing an unprogrammed Lattice device to our parallel bus design?

What methods are available to initiate configuration for the LatticeXP2?

Why does multiple Place and Route report a syntax error and abort?

Which version of the HDMI specification does the LatticeECP3 HDMI/DVI Interface reference design support and does it pass HDMI compliance tests?

I got a static timing result, fMAX=300MHz, for a generic DDR X1 mode while the LatticeECP3 datasheet fMAX_GDDR(max)=250MHz. Can I safely use 300MHz for the generic DDR 1X interface?

I cannot assign the DDR3 memory clock (CK) pads to Bank 1 during the DDR3 core generation when the left side of a LatticeECP3 device is selected for a DDR3 interface running at 300MHz. How can I use the pins in Bank 1 for CK?

In the ispClock5400D family, how are the USER0-USER3 pins configured prior to programming?

Is it possible to use the PowerManager_1220_I2C_Utility.exe in Windows 7? I see a message stating "Error: Kernel Mode Driver is not loaded in memory" when I try to launch it.

What happens to MachXO2 configuration ports (JTAG/I2C/SSPI) when power is removed when reprogramming the Configuration Flash or User Flash memory?

Lattice Diamond Programmer isn't listing a new SPI Flash device I would like to use, is there a work around?

Does the FPGA section of the Platform Manager have an SPI or I2C interface? Where are the registers defined for these interfaces?

Can I run a DDR3 interface at frequencies as low as 100MHz using LatticeECP3?

After executing the orc_cmpl.bat ModelSim VHDL library compilation script, why do I get errors about unexpanded library elements when I compile my design?

Does the reference design "Fault Logging and Monitoring Using Platform Manager Devices", support SPI or I2C interface to the FPGA from a master Microcontroller? 

What are the allowed input currents for the Power Manager II VMON and digital inputs? Is there a specific recommendation for protecting those inputs?

The bitstream download time can vary for Lattice MachXO device programing mode. Does "debug" mode increase the download time?

LatticeECP3 device has a low power family.  Can the bitstream used for the regular device be programmed in the low power device?

How does the RX loss of signal detection circuitry in the LatticeECP3 PCS/SERDES react to  constant value or a drop in signal condition on the SERDES serial inputs?

What kind of models can I use to simulate Lattice IO packages parasitics?

An output pin in my PAC-Designer project is now assigned as a node. Why did it change and how can I change it back to an output?

Why does the Lattice software pick VCCIO bank voltages smaller than 3.3V when all my design IO buffers are of the 3.3V type?

What is the maximum size of the SSPI Embedded SEA/SED data files?

Can LatticeECP3 devices support sub-LVDS IO?

Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?

Is it possible to program the LatticeXP2 SRAM directly using slave SPI mode?

What are the differences between the specific SPI Flash devices listed in the Lattice programming  software tool?

How can I resolve the Reveal error: core0 incorrect signature (RVL: 154782948 != Device: 0)

What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

Why is there a Timing Rule Check violation in the trace report on a  ODDRX4B element for timing between the SCLK & ECLK inside this element?

What is the latency between absence of SERDES input data and Loss of Lock signal for Lattice ECP2M/ECP3 devices? 

Why can I only assign 7 SECONDARY clocks in a clock region instead of 8 SECONDARY clocks?

I migrated my design from DDR2 to DDR3 and noticed that there are two more edges on DQS during the write operation. Why does the DDR3 controller IP core behave like this?

Is it OK to loop XAUI data from the RX XGMII to the TX XGMII if the IPG is always between  5 and 8 bytes long?

I need to use four chip select signals while the Lattice DDR3 controller IP core supports only up to two. Can I extend the number of chip select from the core?

We would like to use a higher density device, but a DQ output becomes a PLL input on the larger device, is there a work around for this?

I am using DDR3 controller IP core v1.3 in my design. Why does the simulation result fail while the design works well without a failure on the board?

Why do I get an error  stating "FTDI port is busy", when ispVM System opens?

Where can I find the related documentation ans source code to program my Lattice Device using the JTAG interface in an embedded system?

Why do I get "Unknown Object" errors from the Spreadsheet View tool when I integrate a DDR3 IP core into my project?

Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

How to generate an input port on the schematic in Lattice Diamond Schematic Editor?

How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?

Will the LatticeECP3's read datavalid generation circuit work properly when I remove the VTT termination from the DQS pad?

What is the reason behind high supply transients during startup for the ispMACH 4000 device?

What are the main differences between Flash Programming Mode and Flash Background Mode?

Why does the XO2 IBIS model show lower edge rate difference (fast vs. slow) than the ECP3 IBIS model?

Can I connect an external LVDS25 clock output to a LatticeECP3 DDR3 bank which is 1.5V VCCIO bank?

Can I connect JTAGENB pin of MachXO2 device directly to the VCC or GND?

The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

Why do I have a netsanitycheck error when I make a dynamic clock selector drive DDR primitive components in my LatticeECP3 design?

My LatticeXP2 bitstream loads an initial TAG memory content. When I re-configure the TAG memory, how can I preserve it so it is not overwritten with the initial content the next time I re-load my original bitstream.

How does the Big/Little Endian switch effect the functionality of the FIFO_DC in IPExpress?

Can I read a 1.0 Volt signal from the ADC with attenuator setting 1 (divide by 3) on a PWR6AT6 device?

How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?

How do I check the coverage of my timing constraints?

Can the default BSDL file provided on the Lattice web site be used to test a programmed LatticeECP3 device after reinitialization?

What is the optimum PCB solder mask opening and pad diameter for a Lattice package?

What is the POR state of I2C controlled input and output pins in POWR1014A?

How do I get a DDR3 simulation result based on my mode register program values? I generated a DDR3 IP core with my mode register initialization values, but the evaluation simulation provides the results with different mode register settings.

Why does my regenerated DDR3 IP core have different CL and CWL values from the original LPC file that has CL=7 and CWL=6 at 400MHz?

Is there a way to implement a 4-bit DDR3 memory controller using the Lattice DDR3 controller IP core?

Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?

How do I place DDR3 interface pins to minimize SSO impact?

Which IBIS models should I use for the MachXO JTAG signal pins?

Which IBIS models should I use for the MachXO2 JTAG signal pins?

How do I select between the two Vol Max values 0.4V, or 0.2V documented in the LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics?

We are seeing the primary clock delay to multiple IO Logic elements are the same in the LatticeECP3 device, is this correct?

Why does the I/O vector editor in the Device Information window "Expand Option" not generate the I/O vector file (*.iov file), when I click "Apply" instead of "Save As"?

Why doesn't the delay time unit change  when I change the skew setting from fine to coarse for an ispPAC-CLK56xx device?

How many idle ordered sets will the SGMII and Gb Ethernet PCS IP Core Clock Tolerance Compensation logic insert or delete during an Inter packet Gap period?

What types of JTAG multi chain designs does the Lattice ispVM System software support? 

What is the delay value on each step for the MachXO2 input data delay DELAYE module?

Can the SERDES input voltage threshold be modified to force the SERDES into a reset state? 

Do the I2C inputs on the ispPAC-POWR1014 have hysteresis?

How can I generate a much smaller IBIS model file that only includes the IO types defined in my project?

Are ispClock products suitable for ITU-T G.8262 applications?

Why am I unable to view the simulation waveform window in PAC-Designer ?

Lattice SERDES based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?

Is FIFO bridge in the PCS used in the low latency CPRI IP core?

How do you reset the I2C interface on Power Manager II devices?

What would happen to the Delay Control bus (DCNTL) output of the DLL when the LatticeSC DLL looses lock?

I have given clock constraint in my constraint file (LPF), then why am I getting a warning in synthesis that the clock is not constrained?

Why are the D filp flop nodes are being assigned to IO pins and causing my ispGAL design not to fit.

Does the PAC-Designer I2C utility work with the Lattice USB Download cable?

I recently started seeing the Warranty Warning shown below whenever I start the ispLEVER software.  Does this mean my license is invalid or that I would no longer have access to certain tools?

What is the meaning of this warning in Active-HDL:

Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line breakpoints, code coverage, and assertion debug will not be available.

Can LatticeECP3 FPGA device's multiple I/Os be connected in parallel to produce higher combined output I/O current exceeding that of a single I/O?

Will I see a difference in duty cycle when I use IO set to FAST slew rate versus the SLOW slew rate? 

Can I make post Place and Route (PAR) changes to my design without having to run through the entire Lattice Diamond design flow?

How do I uninstall ispDev driver or prevent ispDEV from disabling the hibernate mode on the PC?

Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?

What are the differences of using syn_keep, syn_preserve, syn_noprune, NOCLIP and NOMERGE source constraints in an FPGA design?

Does Lattice provide IBIS model for SERDES inouts of LatticeECP3?

How I can use the DELAYB cell to add delay to a input port when a single register exists between the input and output ports?

Are there any special considerations to interface the LatticeECP3 SERDES to standard SFP transceiver modules?

When using Lattice's HDMI/DVI Interface reference design, do I have to use a TMDS Level Shifter for the HDMI Transmitter interface?

Can the MachXO2 device support PCI-compliant signaling on any GPIO?

How do I design a PCB land pattern for Power Manager to meet UL standards?

Do I need to use a clock cleaner when using CPRI IP core with Lattice SERDES based FPGA?

What are the mechanical positions of the mounting holes and J58 pin A1 on the LatticeECP3 IO Protocol Evaluation Board?

What are the functions of LatticeECP3 register bits tdrv_drvcur_set and tdrv_amp_boost?

When running my LatticeECP3 DDR design through software PAR, it fails with a "netsanity check" error like:

"ERROR - par: netsanitycheck: the clock buf_clk on comp Inst4_DLLDELB port CLKI is driven by general routing through comp clk. Please use the appropriate constraints when using general routing for clocks"

Can Lattice CPRI IP core support auto-negotiation?

How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?

When using the FREQUENCY preference, when would I want to use the HOLD_MARGIN keyword?

What is the start point of "input operation" and the start point of "output operation" after TransFR command in "Leave Alone" I/O State?

How do I use the ispPAC-POWR1220's on-board ADC through the I2C port?

Why do I have an error during the mapping of a DDR3 IP-based design, saying "Error: Output buffer drives output buffer: each IO pad requires one and only one buffer..."?

When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

Can I use the clock tolerance compensation (CTC) function of LatticeECP3 family SERDES/PCS in 10BSER mode?

Can LatticeECP3 support OC3/OC12/OC48 SONET/SDH framer or mapper applications?

What are minimum and maximum voltage levels of LatticeECP3 SERDES inputs?

Where can I find more information regarding the FPGA Loader reference design?

When implementing PCIe designs with Lattice devices that support SERDES, what should be done with the unused channels?

What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?

Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?

Does LatticeECP2/M support Programmable On-Chip Termination resistors for the LVDS Inputs?

What is the recommended coupling method for LVDS reference clock input signals with Lattice FPGA devices?

Can I use the RESETb pin on a POWR1014 or POWR1220 to reset other parts of my circuit?

Can the CLKP/CLKN outputs of the DDR3 memory controller be placed on the top side of the LatticeECP3 device?

In PAC-Designer, what is error F38190?

Error reports>> Signal not found in either the #$PINS or #$NODES list.

Where can I find more information about other manufacturer's new devices on the Lattice evaluation board?

Can the POWR1014A device support a Soft-Start/Enable pin on a DC/DC converter power supply?

How can I specify a LVPECL differential I/O in my RTL source code?

How to implement two cascading PLLs in a FPGA ?

When using the trim functions of a POWR6AT6, or POWR1220 what happens if I separately disable the LDO or DC-to-DC converter being controlled?

How do I measure the common mode voltage of LatticeECP3 SERDES current-mode logic (CML) signaling ?

Where can I find detailed information about the Lattice evaluation boards?

What should I do when I receive "Unexpected Error - Quitting" when running Orcastra in Windows 7, 64 bit mode?

In LatticeECP2M SerDes, I use continuous K character, BC as the training pattern in G8B10B mode. The received data is good but the ls_sync singal never goes high. What am doing wrong?

What are the ESD Voltage ratings with PCI Clamp "ON" in IOBUF Attributes?

How much duty cycle variation will a clock signal have at an output IO?

Why do post-fit equations differ from my design equations using PAC-Designer?

How or where can I learn to use ORCAstra in my ECP3 design?

What are the different factors that affect device speed, temperature and voltage selection during software timing analysis?

What is the recommended setting for PLL_LOL_SET?

In LatticeECP3, is it possible to change the serdes mode from 8b/10b to 10b serdes mode via the SCI on the fly when the data rates are same for both mode?

Why are the LatticeECP3 LVDS input terminations modeled as resistors to 1.25v in the IBIS model file?

Are all IOs of LatticeECP3 in high-impedance state when VCC, VCCIO and other power supplies do not have power applied?

Are drivers available for the LCD-Pro USB interface that are compatible with Windows7 64-bit operating system?

Which HDL entry methods are available for Lattice Platform Manager devices?

Are "Boundary Scan Descriptive Language ", ( BSDL ) files available for Lattice Power Manager devices?

What are the different synthesis options available for Lattice Diamond?

I tryed to generate a PLL module with the IPExpress tool of the Lattice Diamond but the generate button was grayed out. How can I generate a PLL in the IPExpress?

On a Platform Manager, what do I need to do to un-used pins?

Why can't I get the Aldec Active HDL simulator to start properly after  upgrading to the latest version of the Lattice Diamond software?

In LatticeECP2/M and LatticeECP3 device families,

what are the states of HDOUT pins during power down mode and power up mode?

Do the Platform Manager products contain more than one silicon die?

When using revision control in Diamond software, how to archive project files with minimum hard disk space usage?

How do I wire up VMONGS lines for the Power Manager II?

Does the Platform Manager support I2C?

Are the clocks in Platform Manager connected internally?

How many timers can I build in a Platform Manager LPTM10-12107?

How can I use Reveal along with Mico32 MSB to debug my system?

Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?

What does "Fatal : Obsolete library format for design unit" Modelsim error mean?

Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?

What is the best way to divide a clock by 2 in Lattice devices?

When replacing an expired ispLEVER license file, how do I clear the FlexLM licensing environment variable in Windows registry?

Why will a bitstream encrypted LatticeECP2/M "S" device configure using JTAG, but not by other methods of programming?

How to set LatticeECP3 FPGA IO in temporary tri-state when another partner device in line card doesn't support hot swap?

How to prevent the HDOUTP/N from sending out the pattern when ffc_quad_rst is asserted?

Can a SERDES recover clk(such as rxa_pclk or rxb_pclk or rx#_sclk in LatticeSC) be used to drive general purpose FPGA logic?

Why does the GbE PCS link state machine status signal regularly pulse low eventhough the SERDES/PCS receives valid 8b10b encoded characters?

Why does Map report errors about inputs connecting to both PAD and non PAD loads?