Article Details

ID: 424
Case Type: faq
Category: Architecture
Related To:
Family: LatticeECP2/M

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I configure a Lattice ECP2/M device with an Atmel SPI Flash. Supposedly the CCLK should run 120 cycles after the done signal become active and then become tri-stated, but in my case the CCLK never stops running. Why is this happening?

The continuously-running CCLK is caused by an instantiation of a SED (Soft Error Detect) module in the customer's design. The  Lattice ECP2/M internal OSC is the only available clock source for the SED module, and it will continuously run and drive CCLK output after the configuration is DONE. The user can stop the CCLK by disabling the SED module.
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