Lattice Solutions

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  • Key Phrase Detection

    Reference Design

    Key Phrase Detection

    Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
    Key Phrase Detection
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • CNN Compact Accelerator IP

    IP Core

    CNN Compact Accelerator IP

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    CNN Compact Accelerator IP
  • Single Wire Aggregation

    Reference Design

    Single Wire Aggregation

    Use a low-cost FPGA to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion, transmit a over single wire, and de-aggregate.
    Single Wire Aggregation
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
    UART 16550 IP Core
  • PDM Microphone Aggregation

    Reference Design

    PDM Microphone Aggregation

    Aggregate up to 8 PDM microphones and connection to a processor over I2S or SPI with no impact in audio quality. Ideal for beam-forming. PCM output at 48HKz.
    PDM Microphone Aggregation
  • Image Sensor Bridge

    Reference Design

    Image Sensor Bridge

    Interfaces a CMOS camera to a Digital Video Port (DVP) for a low-power low-footprint solution.
    Image Sensor Bridge
  • Infrared Remote Tx/Rx Reference Designs

    Reference Design

    Infrared Remote Tx/Rx Reference Designs

    Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
    Infrared Remote Tx/Rx Reference Designs
  • Long Range (LoRa) Wireless

    Reference Design

    Long Range (LoRa) Wireless

    Implement a LoRa compliant device using a tiny iCE40 UltraPlus FPGA, for low-power, low-footprint wireless communication over miles
    Long Range (LoRa) Wireless
  • Graphics Acceleration

    Reference Design

    Graphics Acceleration

    Enables a processor to save power in sleep mode while the low-power iCE40 UltraPlus drives a mobile DSI display, and monitors for wake-up signals.
    Graphics Acceleration
  • iCE40 UltraPlus I2S IP

    IP Core

    iCE40 UltraPlus I2S IP

    Customize and control an I2S bus - Transmit/Receive from 16 to 32 bits.
    iCE40 UltraPlus I2S IP
  • RGB LED Reference Design

    Reference Design

    RGB LED Reference Design

    A complete RGB LED design that controls the color, blinking rate, brightness and breathing of an RGB LED.
    RGB LED Reference Design
  • Sensor Data Buffer

    Reference Design

    Sensor Data Buffer

    Interfaces between multiple I2C-based sensors and a processor's UART. Saves power and resources by always collecting data, while the processor sleeps.
    Sensor Data Buffer
  • Doppler by Dadamachines

    Reference Design

    Doppler by Dadamachines

    The doppler is a Cortex M4F Microcontroller + FPGA development board. Open source design files and documentation are available on github.
    Doppler by Dadamachines
  • iCE Bling by Electronut Labs

    Reference Design

    iCE Bling by Electronut Labs

    Looking for a little fun and style? Electronut Labs has designed a pair of LED earings controlled with an iCE40UP5K FPGA. Design files are available on github.
    iCE Bling by Electronut Labs
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation
  • CAN-CTRL

    IP Core

    CAN-CTRL

    Compliant to CAN 2.0 and CAN FD (ISO 11898-1.2015). Similar to Philips SJA1000 - error analysis, diagnosis, system maintenance, and optimization features.
    CAN-CTRL
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