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I/O Solutions

In Detail

Lattice provides the industry’s highest performance parallel I/O for both its high performance (LatticeSC), low cost (Lattice ECP2/M) as well as non-volatile (Lattice XP/XP2) families. The LatticeSC family is equipped with PURESPEED I/O technology with differential I/O rates topping 2Gbps, while the LatticeECP2/M families have the sysIO blocks delivering an industry best differential I/O performance of 840Mbps.


LatticeSC PURESPEED I/O

The PURSEPEED I/O structure delivers the industry highest parallel I/O speeds by combing the following technologies:

  • The industry’s highest speed I/O buffers running at 2Gbps (LVDS)
  • Broadest range of on-chip termination choices, including a low power Vtt option
  • Dedicated gearing and mux-demux blocks
  • Dedicated low power clock dividers
  • Alignment logic consisting on an Input Delay (INDEL) block with a patented Adaptive Input logic (AIL) closed loop control circuitry
I/O Solutions Figure 1

Building Blocks of LatticeSC PURESPEED I/O System

 

The dedicated alignment logic combines a highly granular Input Delay block (144 delay elements in 70ps step sizes) with the AIL block. The AIL block examines the user defined setup and hold times (or the data valid window, including system jitter), and works with the INDEL block to adjust the data delay until the data edge falls outside the user defined window. This happens dynamically over process, voltage and temperature, and guarantees that setup and hold time violations do not occur. A truly set and forget system.

I/O Solutions Figure 2

Closed Loop Alignment Using INDEL and AIL Circuitry

 
Supported Electrical Standards
I/O Standard Buffer  Type Clock Frequency Pin Throughput Related links
Generic LVDS, Mini-LVDS, RSDS LVDS 1 GHz Up to 2 Gbps PURESPEED I/O
RapidIO Differential 125 - 500 MHz 620 Mb-1 Gbps  
HyperTransport LVDS 200 - 800 MHz 400 - 1600 Mbps  
SPI4.2 LVDS 311 - 450 MHz 622 - 900 Mbps MACO SPI4.2, Interop
SFI4/XSBI LVDS 622/645 MHz 622/645 Mbps  
XGMII HSTL 156 MHz 311 Mbps 10GbE MAC IP
QDR2 SRAM HSTL 300 MHz 600 Mbps Memory Solutions,
MACO Memory Controller
DDR1/2 SDRAM SSTL 333 MHz 667 Mbps Memory Solutions,
MACO Memory Controller
PCI/PCI-x LVTTL 66/133 MHz 66/133/266 Mbps PCI IP
RLDRAM 1/2 HSTL 300/400 MHz 600/800 Mbps Memory Solutions,
MACO Memory Controller

LatticeECP2/M and LatticeXP/XP2 sysIO


SysIO provides the industry’s highest performing I/Os for low cost FPGA. This is enabled by:

  • I/O buffers running at 840Mbps (LVDS)
  • Automatic mux/demux and gearing logic for DDR to SDR conversion
  • Automatic DQS and strobe alignment


I/O Solutions Figure 3

Building Blocks of Lattice ECP2/M sysIO

 

For memory interfaces, the sysIO block comes with a pre-engineered alignment block that aligns DQS with DQ over process, voltage and temperature, while ensuring seamless clock transition from the high speed I/O to the FPGA logic.

I/O Solutions Figure 4
 
Supported Electrical Standards
I/O Standard Buffer  Type Clock Frequency Pin Throughput Related links
Generic LVDS, Mini-LVDS, RSDS LVDS 420 MHz1 Up to 840 Mbps sysIO, Video 7:1 LVDS
SPI4.2 LVDS 311-350 MHz 620-700 Mbps SPI4.2 IP4
XGMII HSTL 156 MHz 311 Mbps 10 GbE MAC IP
DDR1/2 SDRAM SSTL 266 MHz2 533 Mbps3 Memory Solutions,
MACO Memory Controller
PCI/PCI-x LVTTL 66/133 MHz 66/133/266 Mbps PCI IP
1 For LatticeXP, Clock Frequency for LVDS is 350 MHz, Pin Throughput of 700 Mbps
2 For LatticeXP, Clock Frequency for DDR1/2 SDRAM is 166 MHz, Pin Throughput of 333 Mbps
3 For LatticeXP2, Clock Frequency for DDR1/2 SDRAM is 200 Mhz, Pin Throughput of 400 Mbps.
4 SPI4.2 IP is available only for ECP2/M family of devices.