Programmability

Lattice, the Pioneer of In-System Programming (isp) Technology

Lattice completely revolutionized the programmable logic market with its 1991 introduction of the high-density in-system programmable (ISP^TM) CPLD. Devices based on E2 and Flash technologies can be programmed and reprogrammed right on the board, effectively reducing time-to-market and production costs. Lattice has developed and refined its portfolio of ISP products, software, and utilities to provide a comprehensive programmable logic design and development solution. And now, we even offer Mixed-Signal products!

Expanded In-System Programmability (ispXP)

Lattice's ispXP^TM (eXpanded Programmability) technology combines the best features of non-volatile Flash and SRAM technologies. ispXP utilizes a combination of non-volatile Flash cells and SRAM technology to deliver a single-chip solution supporting "instant-on" start-up and infinite reconfigurability. A non-volatile Flash array distributed within an ispXP device stores the device configuration. At power-up this information is transferred in, a massively parallel fashion, into SRAM bits that control the operation of the device. ispXP technology^TM is available in the LatticeXP2^TM and LatticeXP^TM families of FPGAs and the MachXO^TM family of crossover PLDs. The LatticeXP2^TM offers FlashBAK Technology where the contents of the Embedded Ram Blocks may be written and restored from the Flash array.

Features and Benefits

• Instand-on at Power-up
  • With non-volatile memory, the PLD Logic is available in 1mS after power-up
  • PLD logic available before microprocessor reset release
  • Superior solution for microprocessor glue logic and decoder logic
  • Supports power-up control applications
• High Security - Eliminates External Configuration Bitstream
  • Excellent for military and security-sensitive applications
  • Non-volatile security bits protect configuration pattern
• Single-Chip Solution Eliminates Need for Boot PROM or External Storage Device
  • Simplified design process
  • Reduced board space
  • Reduced inventory, handling and manufacturing costs
  • Improved reliability
• Available in Three High-Performance Families Supporting 1.2, 1.8, 2.5 or 3.3V Power Supplies
  • LatticeXP2 and LatticeXP Families of FPGAs
  • MachXO Family of crossover PLDs
• Infinitely Reconfigurable SRAM via IEEE 1532 or sysCONFIG^TM (Microprocessor) Interface
• In-System Programmable E²PROM or Flash memories via IEEE 1532 Port and sysConfig port (LatticeXP2 and LatticeXP devices only)
• Boundary Scan Testable via IEEE 1149.1 (JTAG) Port

Flexible Programming and Configuration

• Reliable configuration by design
• Reprogram Non-volatile in background while running logic from SRAM (Real time reprogrammable)

Configuration in LatticeXP2 devices

• LatticeXP2 has Enhanced FlexiFlash Architecture
  • FlashBAK Technology store contents of EBR blocks in Flash
  • Serial TAG memory to store items such as Board ID, calibration and manufacturing data

High Security
	ispXP devices include security scheme to prevent readback No external bitstream - totally secure from bitstream "snooping" Excellent solution for security-sensitive application
Single Chip Solution
No External Boot PROM Needed for Configuration No Boot PROM noise issues No Boot PROM reliability issues No Boot PROM board space concerns Single-chip solution reduces inventory, handling, and manufacturing costs Simplified design
SRAM + FLASH
	Easy TransFR reprogramming in the field