High Speed Serial I/O Technology: SERDES

Lattice has implemented SERDES technologies in a variety of programmable products. A cost effective SERDES is implemented in the 65nm LatticeECP3 family and 90nm LatticeECP2M family of high-value FPGAs and Lattice's ispGDX2 programmable interconnect family. High performance SERDES are integrated into the 90nm LatticeSC FPGAs, and the prior generation Field Programmable System Chip FPSC devices. 

Lattice SERDES technology leads the programmable logic industry in terms of maximum bit rate, low TX jitter, RX jitter tolerance and power consumption per channel. With SERDES technology, Lattice products demonstrate the fastest bit rates and the longest error-free connections.

SERDES Devices

Lattice offers leading performance programmable SERDES and 10Gbps Ethernet solutions in its LatticeSC, FPSC, FPGA and Digital Crosspoint Switch devices:

• The LatticeSC (System Chip) family of FPGAs combines a high-performance FPGA fabric, 3.4Gbps SERDES and PCS, high-performance I/Os, large embedded RAM, and embedded ASIC blocks in a single industry-leading architecture.
• The LatticeECP3 lowest power, highest-value SERDES capable FPGA offers Mixed Protocol/Mixed Rate support, XAUI jitter compliance and a low 110mW per SERDES channel at 3.2Gbps.
• The LatticeECP2M low cost FPGA combines a cost optimized SERDES/PCS block with the industry's lowest cost FPGA fabric to provide the first and only low cost SERDES based FPGA in the world.
• The ORT82G5/ORT42G5 FPSCs offer demonstrated high performance (3.7 Gbps) SERDES backplane transceivers plus embedded 8b/10b encoding/decoding, FC and XAUI link state machines and channel bonding capabilities along with more than 400K usable FPGA functional gates.
• The ORSO82G5/ORSO42G5 provides high performance (2.7 Gbps) SERDES plus embedded SONET processing, optional user payload processing and channel bonding capabilities along with over 400K usable FPGA functional gates
• The ORSPI4 FPSC offers four channels of high performance (3.7 Gbps) SERDES backplane transceivers plus two embedded SPI4.2 interface blocks, a high-speed memory controller and over 16K programmable logic elements (up to 899K FPGA functional gates).
• The ORT8850 offers 8 channels of 850 Mbps transceivers with embedded full redundant SONET processors, along with up to 899K FPGA functional gates
• With 20 SERDES channels operating up to 850 Mbps, the ispXPGA is the world's first instant-on, non-volatile, infinitely reconfigurable FPGA
• The ispGDX2 is the next generation in-system programmable (ISP) high-performance digital crosspoint switch with up to 38 Gbps bandwidth and 800 Mbps SERDES

SERDES Device Selector Guide

Key Capabilities

• Wide Range of Bandwidth Supported
  • 126Mbps to 3.7Gbps
• Low TX Jitter
  • 0.17UI @ 3.7Gbps
• Good RX Jitter Tolerance
  • 0.8UI @ 3.7Gbps
• Programmable Pre-emphasis (FPSCs)
  • 0%, 12.5%, 25%
• Robust High Speed
  • Reliable Transmission of up to 60" of FR4 at 3.8Gbps
• Low Power CMOS Operation
  • 110mW per channel at 3.125Gbps
• Choice of Programmable Fabric
  • ispGDX2® - Programmable Digital Interconnect
  • ispXPGA - FPGA
  • FPSC - FPGA + Embedded Interface Core
  • LatticeSC - High Peformance Programmable System Chip
  • LatticeECP3, LatticeECP2M - High Value SERDES based FPGA
• Support For Multiple Standards
  • XAUI, Fibre channel, Gigabit Ethernet, SONET

Superior SERDES Performance

Lattice SERDES technology leads the programmable logic industry in terms of maximum bit rate and low jitter. The following actual eye diagram illustrates the outstanding characteristics of Lattice's SERDES technology.

ORT82G5/42G5 RX Eye Diagram over 20" of FR4 at 3.7Gbps