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OverviewField logic update continues to increase in importance in a wide variety of applications due to the unprecedented flexibility that it provides designers to fix bugs, respond to changing standards, upgrade equipment and add additional services. At the same time, system up-time requirements are increasing with "5 Nines" (99.999%) availability a reality in an increasing number of applications. Lattice's TransparentFieldReconfiguration TransFR/TFR solution uniquely allows logic to be updated in the field without interrupting system operation. Requirements For Seamless In Field Updates
There are four requirements that must be met to provide seamless in-system updates. First it must be possible to update the logic in-system from an embedded microprocessor. Second, the overall configuration time must be relatively short. Third, the device I/Os must be controlled during the update process. Finally the device state must be initialized after reconfiguration before I/O control is returned to the user. The LatticeXP/XP2 FPGAs and MachXO PLDs with their dual SRAM and Flash configuration space architecture are uniquely able to address the need for seamless field upgrade of logic. The dual configuration space allows the amount of time the FPGA is not able to process inputs to be be less than 2ms, an order of magnitude lower than competing solutions. Additionally, unique characteristics of the Boundary SCAN and programming circuitry allow the devices to be initialized to a suitable state prior to the FPGA or PLD resuming normal operation. The next section discusses the TFR process in more detail. For designers of SRAM FPGAs the LatticeECP2/M family offer a sub-set of the TransFR technology capability known as TransFR I/O. The LatticeECP2/M devices offer the same capabilities as TransFR technology with the exception that the reconfiguration takes place in 10s to 100s of milliseconds typical of SRAM FPGAs. Four Steps of TFR UpdateField updating the logic of a LatticeXP/XP2 or MachXO device using the TFR update process consists of four steps that can quickly be implemented as two commands in Lattice's ispVM Programming Tool Set. The four steps are outlined below:
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