Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. For the wireless space, a full suite of tested solutions are available that include:
| Low Cost Digital SERDES |
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| Up to 16 Channels per Device |
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| Very Low Power |
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| Low Cost, High Performance FPGA Fabric |
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| Low Cost, Small Form Factor Package |
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| Complete End to End Solution |
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Learn more about LatticeECP3 & LatticeECP2M
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Serial RapidIO Solutions Using LatticeECP3 FPGA Family
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RRH Solutions Using LatticeECP3 FPGA Family
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Lattice provides a comprehensive portfolio of soft and hard wireless IP including Connectivity support. Also available are reference designs in support of data conversion as well as other signal processing functionality. By targeting the LatticeECP3 and LatticeECP2M platforms, developers will drastically reduce cost, power and footprint over competitive solutions.
| Function | Vendor | ECP3 | ECP2M | |
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| Serial Baseband Interconnect | ||||
SRIO IP Core for Wireless Infrastructure Interconnect ![]() |
Lattice | ![]() |
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| Low Latency CPRI IP Core for Baseband Data Transport | Lattice | ![]() |
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| Gigabit Ethernet and SGMII IP Core | Lattice | ![]() |
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| PCI Express Endpoint IP Core | Lattice | ![]() |
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| Data Conversion | ||||
| JESD204A ADC Interface IP Core | Lattice | ![]() |
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| JESD204 ADC Interface reference design | Lattice | ![]() |
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| High Speed Serialized LVDS Interface Reference Design for TI ADS64XX family of ADCs | Lattice | ![]() |
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| High Speed Serialized LVDS Interface Reference Design and Evaluation Platform for TI ADS6000 family of ADCs | Lattice | ![]() |
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| Signal Processing Reference Designs and IP | ||||
Crest Factor Reduction IP core ![]() |
Affarii | ![]() |
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Digital Pre-Distortion IP core ![]() |
Affarii | ![]() |
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Digital Up/Down Converters (DUC, DDC)![]() |
Affarii | ![]() |
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| Digital Up/Down Converters (DUC, DDC) for 4G Reference Design | Lattice | ![]() |
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| 3GPP-LTE CTC Decoder IP Core | TurboConcept | ![]() |
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| WiMAX 802.16 CTC Decoder IP Core | TurboConcept | ![]() |
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| Block Viterbi Decoder IP Core | Lattice | ![]() |
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| Dynamic Block Reed-Solomon Encoder IP Core | Lattice | ![]() |
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| FFT compiler IP Core | Lattice | ![]() |
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| Numerically Controlled Oscillator (NCO) IP Core | Lattice | ![]() |
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| FIR Filter Generator IP Core | Lattice | ![]() |
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| Distributed Arithmetic FIR (DA FIR) IP Core | Lattice | ![]() |
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| CORDIC IP Core | Lattice | ![]() |
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| DSP Building Blocks | ||||
| Listing of DSP IP cores and reference designs from Lattice and our ispLeverCORE Connections Partners | Lattice / Partners | ![]() |
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| Embedded Processors | ||||
| LatticeMico8 open source microcontroller | Lattice | ![]() |
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| LatticeMico32 open source microprocessor | Lattice | ![]() |
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Lattice Development Kits combine application specific evaluation boards, IP and relevant reference designs in one comprehensive package. The Solution Kits allow a potential user to quickly and seamlessly evaluate the Lattice Wireless Solutions portfolio, and to use it as a basis for customer specific development.
| Family | Board | Connectors and Capabilities |
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| LatticeECP3 | AMC Evaluation Board![]() |
AMC PCB card edge interface, DDR2 |
| Serial Protocol Board | SMAs,CPRI/OBSAI, PCIe, GbE, DDR2/DDR3 (components) | |
| I/O Protocol Board | ADC/DAC, SPI4.2, DDR3 (two DIMMS) | |
| LatticeECP2M | Advanced Evaluation Board | mico32, SPI4.2, DDR2 SODIMM, ADC/DAC |
| SERDES Evaluation Board |
SMAs, CPRI/OBSAI, PCI Express (x1), SFP, DDR |
| LatticeECP3 |
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To ensure compliance to 1000BaseX standards, we have tested our SERDES Physical Medium Attachment (PMA) to relevant ANSI 11.2 and IEEE802.3 specifications. Testing methdology and results can be found below: