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Ready to Use Wireless Portfolio

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wireless Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box.  For the wireless space, a full suite of tested solutions are available that include:

  • FPGAs with Embedded SERDES compliant to CPRI, OBSAI, Serial RapidIO, JESD204, PCIe and GbE standards.
  • FPGAs with I/O to Support High-Speed Parallel Interfaces Found on Data Conversion Devices.
  • FPGAs with Embedded, High Performance DSP blocks.
  • A Portfolio of Soft IP Cores and reference designs.
  • Application Specific Development Boards and Demonstration Designs
  • Test and Interoperability Reports for PMA, PCS and Generic I/O.
  • Cooperation with leading ASSP Vendors and Intellectual Property (IP) Partners to Promote Joint System Solutions

 

LatticeECP3 & LatticeECP2M: Industry Leading Programmable Wireless Platforms

Low Cost Digital SERDES
  • Ideal for low cost chip-chip and small factor backplane applications
Up to 16 Channels per Device
  • Supports a wide variety of CPRI and OBSAI topologies
Very Low Power
  • ECP3: 110mw Per Channel (Typical @ 3.2Gbps)
  • ECP2M: 87mW Per Channel (Typical @ 2.5Gbps)
Low Cost, High Performance FPGA Fabric
  • High Performance DSP blocks
  • ECP3 enhancements:
    • Dual-slice architecture with cascadability for filter chains
    • Ternary add stage for improved performance
  • High Performance I/O
  • ECP3 enhancements:
    • DDR3 support
  • High Density Embedded Block Ram (EBR)
Low Cost, Small Form Factor Package
  • Proven 17x17 wirebond packages for SERDES based FPGAs
Complete End to End Solution
  • Soft IP implementations for connectivity and RF/BB processing applications

Learn more about LatticeECP3 & LatticeECP2M

 

 

ECP3 RRH Solution - header

Serial RapidIO Solutions Using LatticeECP3 FPGA Family New!

The LatticeECP3 FPGA based fully integrated evaluation and demonstration platform built on the industry standard Advanced Mezzanine Card (AMC) form factor supports Lattice’s Serial RapidIO 2.1 endpoint IP core and offers users the ability to investigate the lowest cost, lowest power programmable Serial RapidIO 2.1 solution in the industry.

Click here to:

  • Learn about the SRIO 2.1 IP core
  • Learn about the new LatticeECP3 AMC Evaluation Platform
  • Download Documents
  • Learn more about the LatticeECP3 FPGA

 

RRH Solutions Using LatticeECP3 FPGA Family

Click here to:

  • Watch a Demonstration of the RRH Solution
  • Download Product Briefs
  • Learn about the RRH Solution
  • Evaluate the LatticeECP3 FPGA

 

Intellectual Property: Rich Portfolio of Soft IP and Reference Designs

Lattice provides a comprehensive portfolio of soft and hard wireless IP including Connectivity support. Also available are reference designs in support of data conversion as well as other signal processing functionality.  By targeting the LatticeECP3 and LatticeECP2M platforms, developers will drastically reduce cost, power and footprint over competitive solutions.

Wireless IP Portfolio
Function Vendor ECP3 ECP2M
Serial Baseband Interconnect
  SRIO IP Core for Wireless Infrastructure Interconnect New! Lattice checkmark  
  Low Latency CPRI IP Core for Baseband Data Transport Lattice checkmark checkmark
  Gigabit Ethernet and SGMII IP Core Lattice checkmark checkmark
  PCI Express Endpoint IP Core Lattice checkmark checkmark
Data Conversion
  JESD204A ADC Interface IP Core Lattice checkmark  
  JESD204 ADC Interface reference design Lattice   checkmark
  High Speed Serialized LVDS Interface Reference Design for TI ADS64XX family of ADCs Lattice checkmark  
  High Speed Serialized LVDS Interface Reference Design and Evaluation Platform for TI ADS6000 family of ADCs Lattice   checkmark
Signal Processing Reference Designs and IP
  Crest Factor Reduction IP core New! Affarii checkmark  
  Digital Pre-Distortion IP core New! Affarii checkmark  
  Digital Up/Down Converters (DUC, DDC)New! Affarii checkmark  
  Digital Up/Down Converters (DUC, DDC) for 4G Reference Design Lattice checkmark checkmark
  3GPP-LTE CTC Decoder IP Core TurboConcept   checkmark
  WiMAX 802.16 CTC Decoder IP Core TurboConcept   checkmark
  Block Viterbi Decoder IP Core Lattice checkmark checkmark
  Dynamic Block Reed-Solomon Encoder IP Core Lattice checkmark checkmark
  FFT compiler IP Core Lattice checkmark checkmark
  Numerically Controlled Oscillator (NCO) IP Core Lattice checkmark checkmark
  FIR Filter Generator IP Core Lattice checkmark checkmark
  Distributed Arithmetic FIR (DA FIR) IP Core Lattice checkmark checkmark
  CORDIC IP Core Lattice checkmark checkmark
DSP Building Blocks
  Listing of DSP IP cores and reference designs from Lattice and our ispLeverCORE Connections Partners  Lattice / Partners checkmark checkmark
Embedded Processors
  LatticeMico8 open source microcontroller Lattice checkmark checkmark
  LatticeMico32 open source microprocessor Lattice checkmark checkmark

Development Boards and Demonstration Designs

Lattice Development Kits combine application specific evaluation boards, IP and relevant reference designs in one comprehensive package. The Solution Kits allow a potential user to quickly and seamlessly evaluate the Lattice Wireless Solutions portfolio, and to use it as a basis for customer specific development.

Wireless Evaluation Boards
Family Board Connectors and Capabilities
LatticeECP3 AMC Evaluation BoardNew! AMC PCB card edge interface, DDR2
  Serial Protocol Board SMAs,CPRI/OBSAI, PCIe, GbE, DDR2/DDR3 (components)
  I/O Protocol Board ADC/DAC, SPI4.2, DDR3 (two DIMMS)
LatticeECP2M Advanced Evaluation Board mico32, SPI4.2, DDR2 SODIMM, ADC/DAC
  SERDES Evaluation Board

SMAs, CPRI/OBSAI, PCI Express (x1), SFP, DDR
Wireless Demos
LatticeECP3

 

Electrical (PMA) Testing

To ensure compliance to 1000BaseX standards, we have tested our SERDES Physical Medium Attachment (PMA) to relevant ANSI 11.2 and IEEE802.3 specifications. Testing methdology and results can be found below:

PMA Electrical Characterization

  • TN1084 and Supplements (available under NDA) for PCI Express Transmit Jitter Specifications.