Power Manager II - POWR607

The ispPAC-POWR607 monitors up to six circuit board power supplies and provides up to seven open-drain digital outputs. The device can generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD and four programmable timers. Two of the seven outputs can be configured as high-voltage MOSFET drivers, and five of the seven outputs can be configured as inputs. There are also two general-purpose digital inputs, which can be used for other control functions.

The ispPAC-POWR607 includes a power-down feature, which is ideal for applications with very low standby power requirements. The device can either be powered down using an external logic signal or by an internally generated signal. Once in the powered down state the device draws less than 10μA from the power supply.

Download the POWR607 Data Sheet

• Key Features
• Typical Application
• Evaluation Board

Please select a document category from the selection on the left-hand side of this page for more information on ispPAC-POWR607.

Block Diagram

Key Features

• Power-Down Mode I_CC < 10μA

• Programmable Threshold Monitors
  
  • Simultaneously monitors up to six power supplies
  • Programmable analog trip points (1% step size; 192 steps)
  • Programmable glitch filter
  • Power-off detection (75mV)
    

• Embedded Programmable Timers
  
  • Four independent timers
  • 32μs to 2 second intervals for timing sequences
    

• Embedded PLD for Logical Control
  
  • Rugged 16-macrocell CPLD architecture
  • 81 product terms / 28 inputs
  • Implements state machines and combinatorial functions
    

• Digital I/O
  
  • Two dedicated digital inputs
  • Five programmable digital I/O pins
    

• Two High-Voltage FET Drivers
  
  • Power supply ramp up/down control
  • Independently configurable for FET control or digital output
    

• Wide Supply Range (2.64V to 3.96V)
  
  • In-system programmable through JTAG
  • Industrial temperature range: -40°C to +85°C
  • 32-pin QFN package, lead free option

Typical Application

When power is applied to the POWR607, it first checks to see if a power-down pin is active. If the power-down signal is active, then the POWR607 will proceed immediately to the power-down state. If the power-down signal is not active, then the POWR607 turns on the MOSFET to power the DC/DC converters. After all supplies are stabilized the POWR607 generates a CPU reset signal. The voltage supervisor continuously monitors the power supply bus and interrupts the CPU within 12μS if a fault is detected. This allows the CPU to store critical data before it is affected by the fault.

Download the Power Manager II and ispClock Application Examples Brochure

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Evaluation Board

The PAC-POWR607 evaluation board allows the designer to quickly configure and evaluate the ispPAC-POWR607 device on a fully assembled printed-circuit board.

The ispPAC-POWR607 Evaluation Board includes ispPAC-POWR607, Power Manager II, 32-pin QFN package Pads for user I/O, LED, and switches ispDOWNLOAD Cable (HW-DLN-3C) 9V Battery with DC adapter plug for power Programmable with PAC-Designer and ispVM System software