In-System Programmable Clock Generator

Integrated Universal Fan-out Buffer offers Programmable Skew and Output Impedance Control

Imagine designing your clock nets without using an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice's revolutionary ispClock5500/5600 family. Lattice's ispClock5500 devices can be programmed to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements - all while meeting stringent skew and jitter standards!

Lattice's PAC-Designer® software, a PC-based software tool, provides simple and intuitive pull-down menus for configuring all programmable features of the device. In addition, design utilities like the Skew Editor, Frequency Calculator and Frequency Synthesizer enable easy configuration of various counters and other options. Configurations can be downloaded into ispClock5500 devices from a PC parallel port.

The ispClock5500 architecture is built around a high performance PLL with programmable input, feedback, and five output dividers (5-bit) providing the flexibility to generate up to five different clock frequencies and route them to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with different I/O standards. Each output's skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. There are also four configuration profiles stored on-chip for dynamically altering output frequencies for power savings, test modes and other purposes.