The LatticeECPTM (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice's first generation FPGA to implement this approach, the LatticeECP-DSP (EConomy Plus DSP) family, provides dedicated high-performance DSP blocks on-chip. The LatticeECTM (EConomy) FPGA supports all the general-purpose features of LatticeECP devices without dedicated function blocks to achieve even lower cost.
The LatticeECP-DSP FPGA is ideal for use in applications in which cost-effective DSP functionality is needed. Such applications include software defined radio, wireless communications, military applications and video processing equipment. The LatticeEC FPGA is ideal for general non-DSP applications such as low-cost networking, blade servers, network access equipment, consumer electronics, industrial, medical and automotive applications.
Lattice offers two evaluation boards boards for the LatticeECP-DSP and LatticeEC FPGA devices. These boards provide ready-made platforms for evaluating the features and performance of the LatticeECP-DSP and LatticeEC FPGA devices, or aiding in the development of your design:
LatticeEC Standard Evaluation Board: This board is an efficient design featuring a 484-ball fpBGA FPGA device, on-board oscillator, SPI Flash configuration, PCI fingers, on-board power control, prototyping area, various LEDs and more.
LatticeEC Advanced Evaluation Board: Designed for more advanced evaluation and development, this board includes all the features of the LatticeEC Standard Evaluation Board, plus a DDR memory interface, SPI4.2 connectors, on-board FCRAM, general purpose RJ-45 connector, additional power options, SMA connectors and more.
| EC1 | EC3 | ECP6 EC6 |
ECP10 EC10 |
ECP15 EC15 |
ECP20 EC20 |
ECP33 EC33 |
|
|---|---|---|---|---|---|---|---|
| Vcc Voltage (V) | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 |
| PFU Rows | 12 | 16 | 24 | 32 | 40 | 44 | 64 |
| PFU Columns | 16 | 24 | 32 | 40 | 48 | 56 | 64 |
| # of PFU | 192 | 384 | 768 | 1280 | 1920 | 2464 | 4096 |
| sysDSP Blocks1 | - | - | 4 | 5 | 6 | 7 | 8 |
| 18x18 Multiplier1 | - | - | 16 | 20 | 24 | 28 | 32 |
| LUTs (K) | 1.5 | 3.1 | 6.1 | 10.2 | 15.4 | 19.7 | 32.8 |
| Dist. RAM (K bits) |
6 | 12 | 25 | 41 | 61 | 79 | 131 |
| EBR SRAM (K bits) |
18 | 55 | 92 | 276 | 350 | 424 | 498 |
| # of EBR SRAM Blocks | 2 | 6 | 10 | 30 | 38 | 46 | 54 |
| # of PLLs | 2 | 2 | 2 | 4 | 4 | 4 | 4 |
| Maximum User I/O | 112 | 160 | 224 | 288 | 352 | 400 | 496 |
| Packaging | |||||||
| 100-pin TQFP (14 x 14 mm) | 67![]() |
67![]() |
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| 144-pin TQFP (20 x 20 mm) | 97![]() |
97![]() |
97![]() |
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| 208-pin PQFP (28 x 28 mm) | 112![]() |
145![]() |
147![]() |
147![]() |
|||
| 256-ball fpBGA (17 x 17 mm) | 160![]() |
195![]() |
195![]() |
195![]() |
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| 484-ball fpBGA (23 x 23 mm) | 224![]() |
288![]() |
352![]() |
360![]() |
360![]() |
||
| 672-ball fpBGA (27 x 27 mm) | 400![]() |
496![]() |
|||||
1 ECP-DSP devices only