ispClock5600A

Features

• 8MHz to 400MHz Input/Output Operation
• Low Output to Output Skew (<50ps)
• Low Jitter Peak-to-Peak
• Up to 20 Programmable Fan-out Buffers
  
  • Programmable output standards and individual enable controls
    
    • LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL
  • Programmable output impedance
    
    • 40 to 70Ω in 5Ω increments
  • Programmable slew rate
  • Up to 10 banks with individual V_CCO and GND
    
    • 1.5V, 1.8V, 2.5V, 3.3V

• Fully Integrated High-Performance PLL
  
  • Programmable lock detect
  • Multiply and divide ratio controlled by
    
    • Input divider (1 to 40)
    • Feedback divider (1 to 40)
    • Five output dividers (2 to 80 even multiples)
  • Programmable on-chip loop filter
  • Compatible with spread spectrum clocks
• Precision Programmable Phase Adjustment (Skew) Per Output
  
  • 16 settings; minimum step size 156ps
    
    • Locked to VCO frequency
  • Up to +/- 12ns skew range
  • Coarse and fine adjustment modes

• Up to Five Clock Frequency Domains
• Flexible Clock Reference and External Feedback Inputs
  
  • Programmable input standards
    
    • LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, SSTL
  • Clock A/B selection multiplexer
  • Feedback A/B selection multiplexer
  • Programmable termination
• All Inputs and Outputs are Hot Socket Compliant
• Four User-programmable Profiles Stored in E²CMOS^® Memory
  
  • Supports both test and multiple operating configurations
• Full JTAG Boundary Scan Test In-System Programming Support
• Exceptional Power Supply Noise Immunity
• Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• 100-pin and 48-pin TQFP Packages
• Applications
  
  • Circuit board common clock generation and distribution
  • PLL-based frequency generation
  • High fan-out clock buffer
  • Zero-delay clock buffer