The ispClock5406D and ispClock5410D are in-system-programmable differential clock distribution ICs designed for use in high performance communications and computing applications. The ispClock5400D family features the CleanClock™ ultra-low phase noise, third generation PLL. The FlexiClock™ output section supports multiple logic standards and dual skew control features.
The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I2C interface.
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The need for a reference clock source for FPGAs and ASICs with SERDES, such as the LatticeECP3, traditionally has been addressed by expensive crystal oscillators with differential outputs. The ispClock5400D enables the use of a lower cost, lower frequency CMOS oscillator clock source, reducing the overall cost of implementation.
Converts edge-aligned clock output from FPGA to data-centered clock (90° phase skew) for receiver. Use Time Skew feature to dynamically adapt to PVT variation of setup and hold times.
The ispClock5400D can be used to measure timing margin in a given system. In order to ensure that the data transfer between transmitter and receiver takes place reliably across device voltage and operating temperature, system designers usually measure the timing margin indirectly by increasing or decreasing the operating frequency. This is called frequency margining.
The ispClock5400D provides accurate and very fine timing skew control which can be controlled by the I2C bus interface. Using this feature, the receiving clock can be skewed independently from the transmit clock. By adjusting clock skew hold time (tH), setup time (tSU), and clock-to-out (tCO) margins measurements can be obtained.
|CleanClock™ PLL Performance
||Up to 10 Programmable Fan-Out Buffers
|Input Operating Frequency Range||40 to 400MHz|
|Output Operating Frequency Range||
50 to 400MHz
|VCO Operation||400 to 800MHz|
|Programmable Input Types||LVDS, LVPECL, HSTL, SSTL, HCSL|
|Programmable Output and
Feedback Interface Types
|LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS|
|Type of PLL Feedback||Internal/External|
|Number of V Dividers||4|
|V Divider Count Range||2 to 16 (power of 2)|
|Maximum Cycle-Cycle Jitter||29ps (peak-peak)|
|Maximum Period Jitter (RMS)||2.5ps|
|Typical Phase Jitter (RMS)||6ps|
|Maximum Static Phase Offset||0ps to 100ps|
|Programmable Skew||156ps to 12ns|
|Fan-out Buffer Mode||Yes|
The ispClock 5400D evaluation board allows the designer to quickly configure and evaluate the ispPAC-CLK5406D device on a fully assembled printed-circuit board.