ispClock5400D 

The ispClock5406D and ispClock5410D are in-system-programmable differential clock distribution ICs designed for use in high performance communications and computing applications. The ispClock5400D family features the CleanClock™ ultra-low phase noise, third generation PLL. The FlexiClock™ output section supports multiple logic standards and dual skew control features.

The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I2C interface.

• Applications
• Features
• Selector Guide
• Evaluation Board

Please select a document category from the selection on the left-hand side of this page for more information on ispClock5400D.

Applications 

• Low-cost clock source for SERDES
• ATCA, MicroTCA, AMC, PCI Express
• Differential clock distribution
• Generic source synchronous clock management
• High fan-out clock buffer
• Zero-delay clock buffer

SERDES Reference Clock

The need for a reference clock source for FPGAs and ASICs with SERDES, such as the LatticeECP3, traditionally has been addressed by expensive crystal oscillators with differential outputs. The ispClock5400D enables the use of a lower cost, lower frequency CMOS oscillator clock source, reducing the overall cost of implementation.

Clock Management for High-Speed Source Synchronous Interfaces

Converts edge-aligned clock output from FPGA to data-centered clock (90° phase skew) for receiver. Use Time Skew feature to dynamically adapt to PVT variation of setup and hold times.

Timing Margin Measurement

The ispClock5400D can be used to measure timing margin in a given system. In order to ensure that the data transfer between transmitter and receiver takes place reliably across device voltage and operating temperature, system designers usually measure the timing margin indirectly by increasing or decreasing the operating frequency. This is called frequency margining.

The ispClock5400D provides accurate and very fine timing skew control which can be controlled by the I2C bus interface. Using this feature, the receiving clock can be skewed independently from the transmit clock. By adjusting clock skew hold time (tH), setup time (tSU), and clock-to-out (tCO) margins measurements can be obtained.

 

Features 

CleanClock™ PLL Performance Ultra Low Cycle-to-Cycle Jitter (29ps p-p) Ultra Low Period Jitter (2.5ps) Low Output to Output Skew (<100ps) Fully Integrated High-Performance PLL Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with spread spectrum clocks Internal/external feedback Flexible Clock Reference and External Feedback Inputs Programmable differential input reference / feedback standards: LVDS, LVPECL, HSTL, SSTL, HCSL Programmable termination Clock A/B selection multiplexer FlexiClock™ I/O 50MHz to 400MHz Input/Output operation Dual programmable skew per output Dynamic skew control through I2C Low output to output skew (<100ps)

Up to 10 Programmable Fan-Out Buffers Programmable differential output standards and individual enable controls: LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS Up to 10 banks with individual VCCO and GND: 1.5V, 1.8V, 2.5V, 3.3V All inputs and outputs are hot socket compliant Operating Modes Fan-out buffer with programmable output skew control Zero delay buffer with dual programmable skew controls Programmability and Packaging Full JTAG Boundary Scan Test In-System Programming Support Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges 48-Pin and 64-pin QFNS Package

Selector Guide 

ispClock5400D Product Family Selector Guide

Feature	ispClock5400D Family
	5410D	5406D
Outputs	10	6
Input Operating Frequency Range	40 to 400MHz
Output Operating Frequency Range	50 to 400MHz
VCO Operation	400 to 800MHz
Spread-Spectrum Compatibility	Yes
Programmable Input Types	LVDS, LVPECL, HSTL, SSTL, HCSL
Programmable Output and Feedback Interface Types	LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
Type of PLL Feedback	Internal/External
Number of V Dividers	4
V Divider Count Range	2 to 16 (power of 2)
Maximum Cycle-Cycle Jitter	29ps (peak-peak)
Maximum Period Jitter (RMS)	2.5ps
Typical Phase Jitter (RMS)	6ps
Maximum Static Phase Offset	0ps to 100ps
Frequencies Generated	4
Programmable Skew	156ps to 12ns
Fan-out Buffer Mode	Yes

Evaluation Board 

The ispClock 5400D evaluation board allows the designer to quickly configure and evaluate the ispPAC-CLK5406D device on a fully assembled printed-circuit board.

The ispClock-5400D Evaluation Board includes ispClock5406D programmable clock (ispPAC-CLK5406D-01SN48I) Crystal oscillator circuits ispDOWNLOAD Cable (HW-DLN-3C) Universal power supply kit Can oscillator circuits Resistor networks SMA connectors Power jack I2C, JTAG, and test interface headers Programmable with PAC-Designer and ispVM System software