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In-System Programmable Clock


ispClock™– Standard Clock Net Solution

Imagine designing your clock nets without using an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice’s revolutionary ispClock5600A family for complex clock nets and ispClock5300S family for simple clock nets. Lattice’s ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements – all while meeting stringent skew and jitter standards!

ispClock Integration Diagram

The ispClock architecture is built around a high performance PLL with programmable input, feedback, and output circuitry providing the flexibility to generate up to five different clock frequencies and route them to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with different I/O standards. Each output’s skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices.

In ispClock5600A devices there are four configuration profiles stored on-chip for dynamically altering output frequencies for power savings, test modes and other purposes.

The ispClock5300S supports implementation of zero delay and non-zero delay fanout buffers in a single device.

PAC-Designer Software

The PAC-Designer PC-Based design tool provides comprehensive support for ispClock devices.

Key Features and Benefits

  • Reduced Board Space
    • A single ispClock device replaces multiple types of clock devices
    • Eliminates need for serpentine traces and termination resistors
  • Improved Clock Net Performance
    • Low jitter and skew
    • Improved signal integrity
  • Increased Timing Margin
    • ispClock devices reduce timing uncertainty
    • Reduced Time-to-Market
  • Windows / PC based design
    • JTAG programming and Boundary Scan

Feature  ispClock5600A Family ispClock5300S Family
5620A  5610A  5320S 5316S 5312S 5308S 5304S
 Outputs 20 10 20 16 12
8 4
 Input Operating Frequency Range 8 to 400MHz 8 to 267MHz
 Output Operating Frequency Range
4 to 400MHz
5 to 267MHz
 VCO Operation 320 to 800MHz 160 to 400MHz
 Spread Spectrum Compatibility Yes Yes
 Programmable Input Types LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL
 Programmable Output and
Feedback Interface Types
LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL LVTTL, LVCMOS, SSTL, HSTL
 Type of PLL Feedback Internal/External External
 M, N Dividers Count from 1 to 40
None
 Number of V Dividers 5
3
 V Divider Count Range 2 to 80 (in steps of 2)
1 to 32 (in powers of 2)
 Maximum Cycle-Cycle Jitter 70ps (peak-peak) 70ps (peak-peak)
 Maximum Period Jitter (RMS) 12ps 12ps
 Maximum Phase Jitter (RMS) 50ps 50ps
 Maximum Static Phase Offset -100ps to 200ps -40ps to 100ps
 Frequencies Generated 5 3
 Programmable Skew 156ps to 12ns 156ps to 5ns
 Fan-out Buffer Mode No
Yes
 Programmable Termination 40 to 70Ω & 20Ω Setting 40 to 70Ω & 20Ω Setting