ispClock™– Standard Clock Net SolutionImagine designing your clock nets without using an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice’s revolutionary ispClock5600A family for complex clock nets and ispClock5300S family for simple clock nets. Lattice’s ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements – all while meeting stringent skew and jitter standards! ![]() The ispClock architecture is built around a high performance PLL with programmable input, feedback, and output circuitry providing the flexibility to generate up to five different clock frequencies and route them to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with different I/O standards. Each output’s skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. In ispClock5600A devices there are four configuration profiles stored on-chip for dynamically altering output frequencies for power savings, test modes and other purposes. The ispClock5300S supports implementation of zero delay and non-zero delay fanout buffers in a single device. PAC-Designer SoftwareThe PAC-Designer PC-Based design tool provides comprehensive support for ispClock devices. Key Features and Benefits
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