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Clock solutions from Lattice provide superior integration, signal quality, and flexibility over traditional discrete clock generators, buffers, and PCB layout "design tricks". A single device can replace an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts. The ispClock™ Family of devices provide a standard clock net solution for a variety of clocking scenarios. ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedance and drive clock nets with different signaling requirements – all while meeting stringent skew and jitter standards.
Clock Generator
- ispClock5600A devices integrate multiple clock generation and distribution ICs including: Clock Generation, Differential Clock Drivers, Single-Ended Clock Drivers, Zero Delay Buffers, and Termination circuitry. ispClock5600A devices provide four configuration profiles for dynamically altering output frequencies for power savings, test modes and other purposes. See example applications of the ispClock5600A in the Power Manager II and ispClock Application Examples Brochure.
Differential Clock Distribution
- ispClock5400D devices integrate multiple differential logic interfaces, zero delay, and non-zero delay fan-out buffers in a single device. ispClock5400D provides ultra-low jitter performance required for SERDES clock source applications such as PCI Express.
Single-Ended Clock Distribution
Benefits
Reduced Board Space
- Single chip replaces multiple discrete clock and buffer ICs
- Reduced circuit board area waste due to serpentine traces and termination resistors
 Clock and Buffer Component Integration Improved Clock Net Performance
- Low jitter and skew
- Improved signal integrity
- Increased timing margin
Reprogrammable
- Reduce component inventory
- Software-based design
- JTAG programming and boundary scan
ispClock Product Family Selector Guide
| Feature |
ispClock5600A Family |
ispClock5400D Family |
ispClock5300S Family |
| |
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| Outputs |
20 or 10 |
10 or 6 |
20, 16, 12, 8, or 4 |
| Input Operating Frequency Range |
8 to 400MHz |
50 TO 400MHz |
8 to 267MHz |
| Output Operating Frequency Range |
4 to 400MHz |
50 TO 400MHz |
5 to 267MHz |
| VCO Operation |
320 to 800MHz |
400 TO 800MHz |
160 to 400MHz |
| Spread Spectrum Compatibility |
Yes |
Yes |
Yes |
| Single-Ended Fan-out Buffer Interfaces |
LVTTL, LVCMOS, HSTL, eHSTL, SSTL |
None |
LVTTL, LVCMOS, HSTL, eHSTL, SSTL |
| Single-Ended Clock Reference and Feedback Interfaces |
LVTTL, LVCMOS, SSTL, HSTL |
LVCMOS |
LVTTL, LVCMOS, HSTL, eHSTL, SSTL |
| Differential Fan-out Buffer Interfaces |
SSTL, HSTL, LVDS, LVPECL |
LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS |
None |
| Differential Clock Reference and Feedback Interfaces |
HSTL, SSTL, LVDS, LVPECL |
LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS |
LVDS, LVPECL, HSTL, SSTL |
| Type of PLL Feedback |
Internal/External |
Internal/External |
External |
| M, N Dividers |
Count from 1 to 40 |
None |
None |
| Number of V Dividers |
5 |
4 |
3 |
| V Divider Count Range |
2 to 80 (in steps of 2) |
2 to 16 (in powers of 2) |
1 to 32 (in powers of 2) |
| Maximum Cycle-Cycle Jitter |
70ps (peak-peak) |
29ps (peak-peak) |
70ps (peak-peak) |
| Maximum Period Jitter (RMS) |
12ps |
2.5ps |
12ps |
| Maximum Phase Jitter (RMS) |
50ps |
6ps Typ. |
50ps |
| Maximum Static Phase Offset |
-100ps to 200ps |
-5ps to 95ps |
-40ps to 100ps |
| Frequencies Generated |
5 |
4 |
3 |
| Programmable Phase Skew |
156ps to 12ns |
156ps to 12ns |
156ps to 5ns |
| Programmable Time Skew |
None |
0ps to 288ps |
None |
| Fan-out Buffer Mode |
No |
Yes |
Yes |
| Programmable Termination |
40 to 70Ω & 20Ω Setting |
None |
40 to 70Ω & 20Ω Setting |
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