LCD Controller - WISHBONE Compatible

Lattice Reference Designs This reference design provides a processor interface to the common dot-matrix LCD module. The on-chip oscillator available on some Lattice CPLD or FPGA families can further simplify the implementation by eliminating the need for an external clock source. This design is also suitable for low-power applications together with Lattice zero-power CPLDs.

Tested Devices*	Language	Performance	I/O Pins	Design Size	Revision
LCMXO2-1200HC-4TG100C	Verilog	clk_i > 50 MHz	33	25 LUTs	1.2
LCMXO2-1200HC-4TG100C	VHDL	clk_i > 50 MHz	33	25 LUTs	1.2
LCMXO2280C-3FT256C	Verilog	clk_i > 50 MHz	33	23 LUTs	1.2
LCMXO2280C-3FT256C	VHDL	clk_i > 50 MHz	33	23 LUTs	1.2
LFXP2-5E-5TN144C	Verilog	clk_i > 50 MHz	33	25 LUTs	1.2
LFXP2-5E-5TN144C	VHDL	clk_i > 50 MHz	33	25 LUTs	1.2

download design documentation (RD1053)

download source code

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.