This reference design implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master. A simple back-end parallel interface provides the flexibility to interface with any system. This reference design instantly adds SPI bus capability to a device in an embedded system.
|Device Family||Tested Devices*||Language||Performance||I/O Pins||Design Size||Revision|
|MachXO™||LCMXO640C-3T100C||Verilog/VHDL||>80 MHz||28||37 LUTs||1.1|
|ispMACH® 4000ZE||LC4064ZE-4TN100C||Verilog/VHDL||>80 MHz||28||60 Macrocells||1.1|
|Platform Manager™||LPTM10-12107-3FTG208CES||Verilog/VHDL||>80 MHz||28||37 LUTs||1.1|
1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.