This reference design is intended to read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash with non-volatile FPGA/CPLD devices. It provides a way to fetch design or manufacturing information without interrupting the normal operation of the system. UES is supported by Lattice devices such as MachXO and LatticeXP2 to store simple data for identification purposes. It provides a small “writing pad” for engineering and manufacturing to manage revision control in silicon. The Usercode can be defined during the design stage or the programming stage. During power up, Usercode is programmed into SRAM along with the design.
| Device Family | Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| MachXO2TM 1 | LCMXO2-1200HC-6TG144C | >30MHz | 72 |
78 LUTs (Verilog Source) 81 LUTs (VHDL Source) |
1.2 |
| MachXOTM 1 | LCMXO1200C-3T144C | >30MHz | 72 |
75 LUTs (Verilog Source) 79 LUTs (VHDL Source) |
1.2 |
| ispMACH® 4000ZETM 2 | LC4128ZE-5TN144C | >30MHz | 72 | 54 Macrocells (Verilog/VHDL source) | 1.2 |
1. Performance and utilization characteristics generated using the specified test device and Lattice Diamond™ 1.2 software.
2. Performance and utilization characteristics generated using the specified test device with ispLEVER Classic 1.4 software.
download design documentation (RD1041)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2012
