The Power Management Bus (PMBus) is an open standard protocol that was defined as a means to communicate with power conversion and other devices. As an industry standard serial communication interface based on SMBus protocols, it is viewed as an extension of the System Management Bus and supports many new functions. Like SMBus, the PMBus protocol defines three layers, the Physical Layer, the Data Link Layer and the Network Layer.
This design contains a WISHBONE interface and focuses on the implementation of the Data Link Layer protocol. It is convenient to connect this design with a microcontroller which implements the Network Layer protocol.
This design is based on Lattice reference design RD1046: I2C Master with WISHBONE Bus Interface. It is available in both Verilog and VHDL languages.
| Device Family | Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|---|
| MachXO2™ | LCMXO2-2000HC-4TG100CES | Verilog/VHDL | > 50 MHz | 31 | 299/290 LUTs | 1.1 |
| MachXO™ | LCMXO1200C-3T100C | Verilog/VHDL | > 50 MHz | 31 | 292/288 LUTs | 1.1 |
| Platform Manager™ | LPTM10-12107-3FTG208CES | Verilog/VHDL | > 50 MHz | 31 | 292/288 LUTs | 1.1 |
download design documentation (RD1100)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
