The POS PHY Level 3 specification defines the interconnection of Physical Layer (PHY) devices to Link Layer devices, implementing Packet over SONET (POS). The POS PHY Level 3 interface covers all application bit rates up to 2.4 Gbit/s. This specification identifies the features and requirements of the design intended to be used in Link Layer devices. The design implements a POS PHY Level 3 Link Layer interface on one side while, on the other side, it talks to generic FIFOs. It is intended that the user application (Link Layer device) will interface with the generic FIFOs based on the interface described in this specification.
POS PHY Level 3 Link Reference Design Features
- Conforms to the Packet over SONET (POS) PHY Level 3 specifications
- Supports single and multiple PHY operations. Theoretical maximum PHY ports that can be supported as per the POS PHY Level 3 specification is limited to 256; however, the current version of this design only supports 4 ports
- Separate sets of Transmit and Receive FIFOs, where the FIFO size is programmable
- Support for an 8-bit or a 32-bit bus interface running at a maximum speed of 104 MHz
- Supports Byte or Double word (4 bytes) data format to accommodate variable size packets
- Programmable threshold indication from FIFO for packet available signal generation
- Programmable Burst length per PHY port on Transmit side
- Synchronous design running at 104 MHz. Asynchronous FIFOs (different read and write clocks) would be used to provide easy and flexible interface to the user
- Parity Generation and Checking for data integrity on the bus interface
POS PHY Level 3 Link Resources
POS PHY Level 3 Link Reference Design
For Additional Information
To find out how to obtain the POS PHY Level 3 Link Reference Design, please contact your local Lattice Sales Office.