This reference design provides an interface between the Lattice PCI Target 32-bit/33MHz Reference Design and a WISHBONE slave device to take advantage of both standards. It provides a bridging function between multiple IP cores to a common PCI interface.
| Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|
| LCMXO2280C-3FT324C | PCI Clock: 33MHz WISHBONE Clock: >80MHz |
146 | 422 LUTs, 2 EBRs | 1.3 |
| LFE3-70E-8FN484C | PCI Clock: 33MHz WISHBONE Clock: >80MHz |
146 | 627 LUTs, 2 EBRs | 1.3 |
| LFXP2-5E-5FT256C | PCI Clock: 33MHz WISHBONE Clock: >80MHz |
146 | 628 LUTs, 2 EBRs | 1.3 |
download design documentation (RD1045)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
