SRAM-based FPGA devices are volatile and require configuration at power up, with the configuration data held in an external device. Systems often task an embedded microprocessor with FPGA configuration, transferring the data from an on-board ROM or Flash memory. However, on systems that require fast configurations, or systems that do not have microprocessor resources readily available, a dedicated PROM is commonly used. Such PROM devices are typically expensive and are usually sourced from a single vendor.
An alternative solution is to use a Lattice non-volatile PLD or FPGA as an FPGA Loader. The FPGA Loader reference design, coupled with a standard parallel Flash memory can perform the function of a PROM or microprocessor. The design provides the JTAG programming interface to the Flash, as well as control of data to the other FPGAs for configuration.
| Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|
| LCMXO256C-4T100C | 59 MHz | 48 | 147 LUTs | (Programmer Only) 1.1 |
| LCMXO256C-4T100C | 52 MHz | 52 | 197 LUTs | (Programmer Only + Serial) 1.1 |
| LCMXO256C-4T100C | 56 MHz | 62 | 211 LUTs | (Programmer Only + Parallel) 1.1 |
download design documentation (AN8077)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
