According to the IEEE 1149.1 Boundary Scan System, every complex system can have more than one boundary-scan-compliant scan port. If each of these scan ports are linked together, then the chances of enhancing the scan capability would definitely increase. In this design, the multiple scan ports are linked together by implementing instructions feed in to the IEEE 1149.1 port. The MSP (Multiple Scan Port) device can be used to link the four local scan ports or it can be completely bypassed. An ENABLE signal is provided, when low, the device outputs are tri-stated so a Lattice ispDOWNLOAD® Cable can be used directly on the secondary chains for in-system programming.
| Device Family | Tested Devices* | Performance | I/O Pins | Utilization | Revision | |
|---|---|---|---|---|---|---|
| 4-Port Implementation | ||||||
| MachXO2™ 1 | LCMXO2-256HC-4TG100C | >30MHz | 30 | 138 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.4 | |
| MachXO™ 1 | LCMXO256C-5T100C | >30MHz | 30 | 138 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.4 | |
| LatticeXP2™ 1 | LFXP2-5E-5M132C | >30MHz | 30 | 138 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.4 | |
| ispMACH® 4000ZE™ 2 | LC4128ZE-5TN100C | >30MHz | 30 | 60 Macrocells (Verilog/VHDL Source) |
4.4 | |
| ispMACH® 4000V/B/C/Z™ 2 | LC4128V-27T100C | >30MHz | 30 | 60 Macrocells (Verilog/VHDL Source) |
4.4 | |
| Platform Manager™ 3 | LPTM10-1247-3TG128CES | >30MHz | 30 | 138 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.4 | |
| 8-Port Asset Implementation | ||||||
| MachXO2™ 1 | LCMXO2-256HC-4TG100C | >30MHz | 50 | 211 LUTs (Verilog Source) 212 LUTs (VHDL Source) |
4.4 | |
| MachXO™ 1 | LCMXO256C-5T100C | >30MHz | 50 | 211 LUTs (Verilog Source) 212 LUTs (VHDL Source) |
4.4 | |
| LatticeXP2™ 1 | LFXP2-5E-5M132C | >30MHz | 50 | 211 LUTs (Verilog Source) 212 LUTs (VHDL Source) |
4.4 | |
| ispMACH® 4000ZE™ 2 | LC4128ZE-5TN100C | >30MHz | 50 | 108 Macrocells (Verilog/VHDL Source) |
4.4 | |
| ispMACH® 4000V/B/C/Z™ 2 | LC4128V-27T100C | >30MHZ | 50 | 108 Macrocells (Verilog/VHDL Source) |
4.4 | |
| Platform Manager™ 3 | LPTM10-12107-3FTG208CES | >30MHz | 50 | 211 LUTs (Verilog Source) 212 LUTs (VHDL Source) |
4.4 | |
| 8-Port JTAG Implementation | ||||||
| MachXO2™ 1 | LCMXO2-640HC-4TG100C | >30MHz | 50 | 263 LUTs (Verilog Source) 264 LUTs (VHDL Source) |
4.4 | |
| MachXO™ 1 | LCMXO640C-5T100C | >30MHz | 50 | 263 LUTs (Verilog Source) 264 LUTs (VHDL Source) |
4.4 | |
| LatticeXP2™ 1 | LFXP2-5E-5M132C | >30MHz | 50 | 263 LUTs (Verilog Source) 264 LUTs (VHDL Source) |
4.4 | |
| ispMACH® 4000ZE™ 2 | LC4128ZE-5TN100C | >30MHz | 50 | 127 Macrocells (Verilog/VHDL Source) |
4.4 | |
| ispMACH® 4000V/B/C/Z™ | LC4128V-27T100C | >30MHz | 50 | 127 Macrocells (Verilog/VHDL Source) |
4.4 | |
| Platform Manager™ 3 | LPTM10-12107-3FTG208CES | >30MHz | 50 | 263 LUTs (Verilog Source) 264 LUTs (VHDL Source) |
4.4 | |
1. Performance and utilization characteristics generated using the specified test device and Lattice Diamond™ 1.2 software.
2. Performance and utilization characteristics generated using the specified test device with ispLEVER Classic 1.4 software.
3. Performance and utilization characteristics generated using the specified test device with ispLEVER 8.1 SP1 software (Starter or full license version).
download design documentation (RD1002)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
