The Lattice BSCAN-1 is a multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface. With three Local Scan Ports (LSP), the BSCAN-1 function can be structured as hierarchical ports with the ability to add and remove local scan chains to improve test throughput. The LSP can also be accessed individually or in combination of two or three ports at a time to streamline the test flow of similar devices. As defined in IEEE Standard 1149.1, the instruction register and various test data registers can be scanned to exercise the functions of the Lattice BSCAN-1. The 16-state state machine TAP controller provides the main control for the device.
| Device Family | Test Device* | Language | Speed Grade |
Utilization | fMAX (MHz) |
I/O | Architecture Resources |
|---|---|---|---|---|---|---|---|
| MachXO2™1 | LCMXO2-256HC-5TG100C | Verilog & VHDL | -5 | 182 LUTs | >30 | 24 | N/A |
| MachXO™1 | LCMXO256C-3T100C | Verilog & VHDL | -3 | 182 LUTs | >30 | 24 | N/A |
| LatticeXP2™1 | LFXP2-5E-5M132C | Verilog & VHDL | -5 | 182 LUTs | >30 | 24 | N/A |
| ispMACH® 4000ZE2 | LC4128ZE-5TN100C | Verilog & VHDL | -5 (ns) | 101 Macrocells | >40 | 24 | N/A |
| ispMACH 4000V/B/C/Z2 | LC4128V-27T100C | Verilog & VHDL | -2.7 (ns) | 101 Macrocells | >70 | 24 | N/A |
| Platform Manager™3 | LPTM10-1247-3TG128CES | Verilog & VHDL | -3 | 182 LUTs | >30 | 24 | N/A |
1. Performance and utilization characteristics generated using the specified test device and Lattice Diamond™ 1.2 software.
2. Performance and utilization characteristics generated using the specified test device with ispLEVER Classic 1.4 software.
3. Performance and utilization characteristics generated using the specified test device with ispLEVER 8.1 SP1 software (Starter or full license version).
download design documentation (RD1001)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. When using this design in a different device, density, speed, or grade, performance and utilization may vary. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
